tree: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-4.18 head: 89027d9ebb5948392dd5a4ccc72d5a4eaa865537 commit: bcd9a325f0b0f407c4559779a94e802977c67274 [139/159] ASoC: Intel: bytcr_rt5640: Configure PLL1 before using it config: x86_64-federa-25 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: git checkout bcd9a325f0b0f407c4559779a94e802977c67274 # save the attached .config to linux build tree make ARCH=x86_64
All errors (new ones prefixed by >>):
sound/soc/intel/boards/bytcr_rt5640.c: In function 'byt_rt5640_prepare_and_enable_pll1':
sound/soc/intel/boards/bytcr_rt5640.c:177:20: error: 'struct snd_soc_dai' has no member named 'codec'
dev_err(codec_dai->codec->dev, "can't set pll: %d\n", ret); ^~ sound/soc/intel/boards/bytcr_rt5640.c:184:20: error: 'struct snd_soc_dai' has no member named 'codec' dev_err(codec_dai->codec->dev, "can't set clock %d\n", ret); ^~
vim +177 sound/soc/intel/boards/bytcr_rt5640.c
143 144 static int byt_rt5640_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai, 145 int rate) 146 { 147 int ret; 148 149 /* Configure the PLL before selecting it */ 150 if (!(byt_rt5640_quirk & BYT_RT5640_MCLK_EN)) { 151 /* use bitclock as PLL input */ 152 if ((byt_rt5640_quirk & BYT_RT5640_SSP0_AIF1) || 153 (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF2)) { 154 /* 2x16 bit slots on SSP0 */ 155 ret = snd_soc_dai_set_pll(codec_dai, 0, 156 RT5640_PLL1_S_BCLK1, 157 rate * 32, rate * 512); 158 } else { 159 /* 2x15 bit slots on SSP2 */ 160 ret = snd_soc_dai_set_pll(codec_dai, 0, 161 RT5640_PLL1_S_BCLK1, 162 rate * 50, rate * 512); 163 } 164 } else { 165 if (byt_rt5640_quirk & BYT_RT5640_MCLK_25MHZ) { 166 ret = snd_soc_dai_set_pll(codec_dai, 0, 167 RT5640_PLL1_S_MCLK, 168 25000000, rate * 512); 169 } else { 170 ret = snd_soc_dai_set_pll(codec_dai, 0, 171 RT5640_PLL1_S_MCLK, 172 19200000, rate * 512); 173 } 174 } 175 176 if (ret < 0) {
177 dev_err(codec_dai->codec->dev, "can't set pll: %d\n", ret);
178 return ret; 179 } 180 181 ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_PLL1, 182 rate * 512, SND_SOC_CLOCK_IN); 183 if (ret < 0) { 184 dev_err(codec_dai->codec->dev, "can't set clock %d\n", ret); 185 return ret; 186 } 187 188 return 0; 189 } 190
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