<6>omap_mcbsp_dai_startup: cpu_dai_active: 0 cpu_dai:c0351900 c039a71c mcbsp_data->bus_id = 0 err = 0 omap_mcbsp_dai_startup: cpu_dai_active: 0 cpu_dai:c0351900 c039a71c mcbsp_data->bus_id = 0 err = 0 <6>omap_mcbsp_request: id = 0 omap_mcbsp_request: id = 0 <6>omap2_mcbsp_request: id = 0 omap2_mcbsp_request: id = 0 <6>omap_mcbsp_request: returns 0 omap_mcbsp_request: returns 0 wm8978_write: addr: 0x06 (6) val: 16d wm8978_write: addr: 0x06 (6) val: 16d wm8978_write: addr: 0x04 (4) val: 010 wm8978_write: addr: 0x04 (4) val: 010 <6>omap_mcbsp_dai_set_fmt: format: 00000000 dai format: SND_SOC_DAIFMT_I2S omap_mcbsp_dai_set_fmt: format: 00000000 dai format: SND_SOC_DAIFMT_I2S <6>snd_soc_set_pll: 11289600 snd_soc_set_pll: 11289600 wm8978_write: addr: 0x24 (36) val: 00a wm8978_write: addr: 0x24 (36) val: 00a wm8978_write: addr: 0x25 (37) val: 01a wm8978_write: addr: 0x25 (37) val: 01a wm8978_write: addr: 0x26 (38) val: 1e8 wm8978_write: addr: 0x26 (38) val: 1e8 wm8978_write: addr: 0x27 (39) val: 1bf wm8978_write: addr: 0x27 (39) val: 1bf <6>wm8978_set_dai_clkdiv: div_id = WM8978_MCLKDIV div = 0060 wm8978_set_dai_clkdiv: div_id = WM8978_MCLKDIV div = 0060 wm8978_write: addr: 0x06 (6) val: 16d wm8978_write: addr: 0x06 (6) val: 16d <6>wm8978_set_dai_clkdiv: div_id = WM8978_BCLKDIV div = 000c wm8978_set_dai_clkdiv: div_id = WM8978_BCLKDIV div = 000c wm8978_write: addr: 0x06 (6) val: 16d wm8978_write: addr: 0x06 (6) val: 16d wm8978_write: addr: 0x01 (1) val: 1fd wm8978_write: addr: 0x01 (1) val: 1fd <6>wm8978_set_dai_clkdiv: div_id = WM8978_MCLKSEL div = 0100 wm8978_set_dai_clkdiv: div_id = WM8978_MCLKSEL div = 0100 wm8978_write: addr: 0x06 (6) val: 16d wm8978_write: addr: 0x06 (6) val: 16d <6>omap_mcbsp_dai_set_dai_sysclk: clk_id = OMAP_MCBSP_SYSCLK_CLKX_EXT omap_mcbsp_dai_set_dai_sysclk: clk_id = OMAP_MCBSP_SYSCLK_CLKX_EXT <6>omap_mcbsp_dai_set_clkdiv: omap_mcbsp_dai_set_clkdiv: wm8978_write: addr: 0x04 (4) val: 010 wm8978_write: addr: 0x04 (4) val: 010 wm8978_write: addr: 0x07 (7) val: 000 wm8978_write: addr: 0x07 (7) val: 000 <6>omap_mcbsp_dai_hw_params: omap_mcbsp_dai_hw_params: <6>omap_mcbsp_dai_hw_params: channels = 2 omap_mcbsp_dai_hw_params: channels = 2 <6>omap_mcbsp_config: id = 0 omap_mcbsp_config: id = 0 <7>omap-mcbsp omap-mcbsp.1: Configuring McBSP1 phys_base: 0x48074000 <4>omap_pcm_prepare: enable irq for dma_ch 0 omap_pcm_prepare: enable irq for dma_ch 0 wm8978_write: addr: 0x01 (1) val: 1fd wm8978_write: addr: 0x01 (1) val: 1fd wm8978_write: addr: 0x02 (2) val: 1bf wm8978_write: addr: 0x02 (2) val: 1bf wm8978_write: addr: 0x03 (3) val: 1ef wm8978_write: addr: 0x03 (3) val: 1ef wm8978_write: addr: 0x0a (10) val: 000 wm8978_write: addr: 0x0a (10) val: 000 <6>omap_mcbsp_dai_trigger: cmd = SNDRV_PCM_TRIGGER_START omap_mcbsp_dai_trigger: cmd = SNDRV_PCM_TRIGGER_START <6>omap_mcbsp_start: id = 0 omap_mcbsp_start: id = 0 <7>omap-mcbsp omap-mcbsp.1: **** McBSP1 regs **** <7>omap-mcbsp omap-mcbsp.1: DRR2: 0xfff7 <7>omap-mcbsp omap-mcbsp.1: DRR1: 0x0000 <7>omap-mcbsp omap-mcbsp.1: DXR2: 0x0000 <7>omap-mcbsp omap-mcbsp.1: DXR1: 0x0000 <7>omap-mcbsp omap-mcbsp.1: SPCR2: 0x02f5 <7>omap-mcbsp omap-mcbsp.1: SPCR1: 0x0037 <7>omap-mcbsp omap-mcbsp.1: RCR2: 0x8041 <7>omap-mcbsp omap-mcbsp.1: RCR1: 0x0040 <7>omap-mcbsp omap-mcbsp.1: XCR2: 0x8041 <7>omap-mcbsp omap-mcbsp.1: XCR1: 0x0040 <7>omap-mcbsp omap-mcbsp.1: SRGR2: 0x201f <7>omap-mcbsp omap-mcbsp.1: SRGR1: 0x0f01 <7>omap-mcbsp omap-mcbsp.1: PCR0: 0x008f <7>omap-mcbsp omap-mcbsp.1: *********************** <6>omap_mcbsp_dai_trigger: return 0 omap_mcbsp_dai_trigger: return 0 <4>__ratelimit: 20 callbacks suppressed __ratelimit: 20 callbacks suppressed <4>omap2_dma_handle_ch: new DMA IRQ for lch 0 omap2_dma_handle_ch: new DMA IRQ for lch 0 <4>omap_pcm_dma_irq: dma_ch 0 omap_pcm_dma_irq: dma_ch cbsp_dai_trigger: cmd = SNDRV_PCM_TRIGGER_STOP omap_mcbsp_dai_trigger: cmd = SNDRV_PCM_TRIGGER_STOP <6>omap_mcbsp_stop: id = 0 omap_mcbsp_stop: id = 0 <6>omap_mcbsp_dai_trigger: return 0 omap_mcbsp_dai_trigger: return 0 <4>omap2_dma_handle_ch: new DMA IRQ for lch 0 omap2_dma_handle_ch: new DMA IRQ for lch 0 <4>omap_pcm_dma_irq: dma_ch 0 omap_pcm_dma_irq: dma_ch 0 <4>omap_pcm_prepare: enable irq for dma_ch 0 omap_pcm_prepare: enable irq for dma_ch 0 wm8978_write: addr: 0x0a (10) val: 000 wm8978_write: addr: 0x0a (10) val: 000