On Tue, Apr 14, 2009 at 01:34:33PM +0300, Peter Ujfalusi wrote:
To have the DSP_B mode correctly (for the tvl320aic32 codec used in osk5912 board) the FS polarity has to be handled by the mcbsp as it has been inverted. If we don't do this, there is no way to have the MSB at the correct place (it has to be available when the FS is high).
The DSP_A mode can use the FS polarity 'correctly' - as it is. Or we can also consider to require to invert the FS polarity, than add 1 bit delay for DSP_A mode.
As Jarkko says the driver should be hiding all this from users - it should just set the port up as best it can, refusing to do anything that can't be supported by the hardware. The default polarity the hardware uses shouldn't be visible outside the driver.
a) The proposal in the series DSP_B mode (the MSB is transmitted when the FS is high, the length for the pulse is 1):
DSP_A mode (the MSB is transmitted when the FS went low, the length for the pulse is still 1, but the FS stays low for (wlen * channels - 1) cycles):
The difference between the two modes shouldn't be edge of FS used, it should be a clock cycle, though with a 1 BCLK pulse on FS the effect will probably line up. The MSB data needs to be available for sampling on the appropriate rising edge of BCLK.