From: Pardha Saradhi K pardha.saradhi.kesapragada@intel.com
As per HW recommendation, after setting the RUN bit, software must read a 1 from the RUN bit, before modifying related control registers/re-starting the DMA engine.
Signed-off-by: Pardha Saradhi K pardha.saradhi.kesapragada@intel.com Signed-off-by: Sriram Periyasamy sriramx.periyasamy@intel.com --- sound/hda/hdac_stream.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c index 2000ea6f48fa..33c8ced528f6 100644 --- a/sound/hda/hdac_stream.c +++ b/sound/hda/hdac_stream.c @@ -48,6 +48,8 @@ EXPORT_SYMBOL_GPL(snd_hdac_stream_init); void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start) { struct hdac_bus *bus = azx_dev->bus; + int timeout = 300; + unsigned char val;
trace_snd_hdac_stream_start(bus, azx_dev);
@@ -60,6 +62,20 @@ void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start) /* set DMA start and interrupt mask */ snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_DMA_START | SD_INT_MASK); + + do { + udelay(3); + val = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START; + if (val) + break; + } while (--timeout); + + if (!timeout) { + azx_dev->running = false; + dev_err(azx_dev->bus->dev, "unable to start the stream\n"); + return; + } + azx_dev->running = true; } EXPORT_SYMBOL_GPL(snd_hdac_stream_start);