On Sun, Sep 01, 2019 at 01:26:48AM +0900, Katsuhiro Suzuki wrote:
This patch change the judge timing about playing/capturing PCM rate.
Original code set constraints list of PCM rate limits at set_sysclk. This strategy works well if system is using fixed rate clock.
But some boards and SoC (such as RockPro64 and RockChip I2S) has connected SoC MCLK out to ES8316 MCLK in. In this case, SoC side I2S will choose suitable frequency of MCLK such as fs * mclk-fs when user starts playing or capturing.
The best way to handle this is to try to support both fixed and variable clock rates, some other drivers do this by setting constraints based on MCLK only if the MCLK has been set to a non-zero value. They have the machine drivers reset the clock rate to 0 when it goes idle so that no constraints are applied then. This means that if the machine has a fixed clock there will be constraints, and that constraints get applied if one direction has started and fixed the clock, but still allows the clock to be varied where possible.