Hello.
I found some mistakes. - AUDMUX configuration : Tx clock/fs direction I noticed this mistake when checking i.MX21's applicaton note #2628. The descriptions in the reference manual is very hard to understand the AUDMUX's specfications. - in ADS board, TOUT/SSI2_MCLK is used to receive IRQ from MC13783, there is a conflict and the pin configuration was overwritten when register IRQ handler.
After correct the above mistakes, I could see the signals: SSI_CLK,FS,TxDAT and MCLK. But, still I have a problem. Though I want to provide an oversampling clock with MCLK to the codec device, now the frequency of MCLK is same as SSI_CLK. Can't the MCLK provide the oversampling frequency?
Now I'm porting WM8728 driver with i.MX27ADS, based on Freescale's BSP kernel(2.6.22) and refering to ALSA SoC git repository.
I checked SSI-3 signal set with an oscilloscope, no clock signal appears on SSI3_CLK. I tried the various SSI setting, I2S normal, I2S master, asychronous/synchronous, normal mode/network mode, ... But, I can't see clock signal, yet.