On Fri, Sep 10, 2010 at 08:32:46PM +0900, Jassi Brar wrote:
On Fri, Sep 10, 2010 at 6:39 PM, Mark Brown
On Fri, Sep 10, 2010 at 05:43:14PM +0900, Jassi Brar wrote:
As I've said in the past the concern I have with all this stuff is that outside of Samsung there's no documentation of the IIS block versions or their relationships, the only references I've seen to versions have been for chips with multiple versions (like the 6410) and there it's just a mention that versions exist and the register documentation is completely
cut'n'pasted.
All this info could be gotten by comparing the I2S chapters of relevant SoCs... which is what I do. I don't have any special documentation either.... there is none. The only luxury I have is to be able to get clarifications via appropriate channels of info.
You appear to be at least aware of the versions :) Most of us were going on naming based on CPU names.
It would be good if you could make sure that any platform data for identifying the versions is sufficiently clear to allow someone to go from datasheet to knowing which IP version they have.
Actually I plan to use enum for I2S types and assign them alongside platform_device definition of I2S blocks and their platform_data. Any I2S block that matches register description of 2-channel block of 6410 is v3, that with 5.1 is v4 and that with 5.1 of C100 is v5.
Including a listing of the registers you look at when doing the comparison would be useful here - some sort of flow chart to work through, for example. Bear in mind that the datasheets for the CPUs aren't (all?) public either so people might not be able to look at the register maps for older CPUs if they only have the datasheet for the CPU they have been working on.
There are no differentiating IDs to be read from any register.
Yup, I'm aware of this.