16 Jan
2015
16 Jan
'15
10:09 a.m.
Hi
On Thu, Jan 15, 2015 at 11:28:21PM +0100, Thomas Niederprüm wrote:
This patch fixes faulty behaviour in a setup where the input clock for the SRG is fed through the CLKR pin but the McBSP is configured to be master (SND_SOC_DAIFMT_CBS_CFS). In that case of course CLKR must not be configured as output pin. Otherwise the input clock is messed up horribly. The same reasoning applies if CLKX is configured as input for the SRG.
Signed-off-by: Thomas Niederprüm niederp@physik.uni-kl.de
sound/soc/omap/omap-mcbsp.c | 4 ++++ 1 file changed, 4 insertions(+)
I cannot check at the moment but is this actually a contradictory configuration if McBSP is set to bit clock master but at the same want to use it as an input also? Should you use SND_SOC_DAIFMT_CBM_CFS instead?
Peter: care to check?
--
Jarkko