19 Jul
2011
19 Jul
'11
11:04 a.m.
Hi,
pls check http://comments.gmane.org/gmane.linux.alsa.devel/83781 I think Mark is right, sgtl5000 already declared its register_step is 2, soc_cache.c should generate a dense cache layout instead of padding it by driver.
Thanks for the pointer. I can follow Mark's reasoning. In fact, I was wondering why ASoC does not consider the step, but I assumed it was intentional. With my holidays coming along, nothing I am going to tackle in the next time, though ;)
But after check soc_cache.c, ASoC mix up index and register address to index cache, and many places need to modify to correct it, so I think we should re-consider if register_step != 1 is not a common case.
I think it should be properly fixed in ASoC. It should be carefully done, but otherwise not be a major task IMO. Note that sgtl5000 will need adaptions nonetheless. Which brings me back to the question: In what setup did the driver work for you? Did you have regulators on that board? I am still trying to understand the side-effects of what I am seeing...
Mark: Will you pick up patches 1 and 2 nonetheless?
Thanks,
Wolfram
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