msleep(1) is not so accurate and may cause almost 15ms delay in azx_reset(). usleep_range() can reduce ~30ms loading time for Intel Haswell which has two HDA controllers.
Signed-off-by: Wang Xingchao wangxingchao2011@gmail.com --- sound/pci/hda/hda_intel.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index eb48109..865df90 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -1075,22 +1075,22 @@ static int azx_reset(struct azx *chip, int full_reset)
count = 50; while (azx_readb(chip, GCTL) && --count) - msleep(1); + usleep_range(1000, 1500);
/* delay for >= 100us for codec PLL to settle per spec * Rev 0.9 section 5.5.1 */ - msleep(1); + usleep_range(1000, 1500);
/* Bring controller out of reset */ azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
count = 50; while (!azx_readb(chip, GCTL) && --count) - msleep(1); + usleep_range(1000, 1500);
/* Brent Chartrand said to wait >= 540us for codecs to initialize */ - msleep(1); + usleep_range(1000, 1500);
__skip: /* check to see if controller is ready */