[...] a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
new file mode 100644 index 0000000..a655800 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt @@ -0,0 +1,63 @@ +Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
+The Freescale S/PDIF audio block is a stereo transceiver that allows the +processor to receive and transmit digital audio via an coaxial cable or +a fibre cable.
+Required properties:
- compatible : Compatible list, contains "fsl,spdif".
That's not what the driver says though.
- reg : Offset and length of the register set for the device.
- interrupts : <a b> where a is the interrupt number and b is a field that
- represents an encoding of the sense and level information for the interrupt.
- This should be encoded based on the information in section 2) depending on
- the type of interrupt controller you have.
The exact layout of the cell depends on the parent interrupt controller, so you probably shouldn't describe it here.
- clocks : The phandle for the clock ID number registered in clock tree.
- fsl,spdif-dma-events: The dma event ID numbers for Tx and Rx.
Use the generic DMA bindings.
+Optional properties:
- rx-clk-source : The clock cource for Rx. Need to set this source according
- to the SoC datasheet in SPDIF_SRPC section. If absent, the default source is
- value 0x0 - if (DPLL Locked) SPDIF_RxClk else extal.
- tx-clk-source : The clock cources for Tx. There're three sources, each for
- different supported sample rate, sequentially 32000Hz, 44100Hz and 48000Hz.
- Need to set this source according to the SoC datasheet in SPDIF_STC section.
- If absent, the default source is value 0x1 - CCM spdif0_clk_root input.
- tx-clk-div : The clock divider factor for Tx clock. There're three values,
- each for different supported sample rate, sequentially 32000Hz 44100Hz 48000Hz.
- Need to set this source according to the clock rate from the clock source.
- If absent, the default divider factor is <37 23 37> by using spdif0_clk source.
Can't the driver figure out the divider values on its own based on the input clock rate?
- Lars