On Tue, 30 Sep 2008 12:11:45 +0530 "ext Arun KS" arunks@mistralsolutions.com wrote:
I think this is not enough. The word clock length equals to one BCLK cycle in DSP mode. Not n channel bit BCLK cycles like in I2S.
In DSP Mode, Frame sync is followed by two data words. I tested this patch and its working. Am i missing something ?
I meant length of FS/LRC[IN | OUT] signal itself. E.g. see figures 3-7 and 3-8 in AIC23 data manual:
http://www.ti.com/lit/gpn/tlv320aic23
Now omap-mcbsp.c sets this FS length to 16 BCLK periods in omap_mcbsp_dai_hw_params. Currently code is pretty much tailored for 16-bit stereo I2S so probably some McBSP configuration bits are better set in another function than currently :-)
Jarkko -- To unsubscribe from this list: send the line "unsubscribe alsa-devel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html