18 Apr
2008
18 Apr
'08
7:59 a.m.
2008/4/17 Daniel Mack daniel@caiaq.org:
On Thu, Apr 17, 2008 at 09:12:45PM +0200, Daniel Mack wrote:
This patch makes the tlv320aic33 driver skip the initialisation of the PLL in case the sysclk is 256 * samplerate. Had to do some minor refactoring too - the check whether a sysclk set by set_sysclk() is valid is now done in set_hw_params().
Sorry, there was a small typo in the patch I just submitted. Use this one instead.
I had a quick look to your patch and AIC33 spec.
Is this the same than 256-clock transfer mode? Should you set the bit 3 in AIC3X_ASD_INTF_CTRLB in this case? Should you also still write the AIC3X_SAMPLE_RATE_SEL_REG?
Jarkko