10 Dec
2012
10 Dec
'12
8:58 p.m.
Hi!
On Mon, 2012-12-10 at 10:30 +0100, Daniel Mack wrote:
The CS4271 requires its LRCLK and MCLK to be stable before its RESET line is de-asserted. That also means that clocks cannot be changed without putting the chip back into hardware reset, which also requires a complete re-initialization of all registers.
One (undocumented) workaround is to assert and de-assert the PDN bit in the MODE2 register.
This patch adds a new flag to both the DT bindings as well as to the platform data to enable that workaround.
Signed-off-by: Daniel Mack zonque@gmail.com
Looks good to me.
Acked-by: Alexander Sverdlin subaparts@yandex.ru
-- Regards, Alexander.