On Fri 15 Mar 2024 at 02:21, Jan Dakinevich jan.dakinevich@salutedevices.com wrote:
Existing values were insufficient to produce accurate clock for audio devices. New values are safe and most suitable to produce 48000Hz sample rate.
The hifi pll is not about 48k only. I see no reason to restrict the PLL to a single setting.
You've provided no justification why the PLL driver can't reach the same setting for 48k. The setting below is just the crude part. the fine tuning is done done with the frac parameter so I doubt this provides a more accurate rate.
Signed-off-by: Jan Dakinevich jan.dakinevich@salutedevices.com
drivers/clk/meson/a1-pll.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 4325e8a6a3ef..00e06d03445b 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -74,9 +74,9 @@ static struct clk_regmap fixed_pll = { }, };
-static const struct pll_mult_range hifi_pll_mult_range = {
- .min = 32,
- .max = 64,
+static const struct pll_params_table hifi_pll_params_table[] = {
- PLL_PARAMS(128, 5),
- { },
};
static const struct reg_sequence hifi_init_regs[] = { @@ -124,7 +124,7 @@ static struct clk_regmap hifi_pll = { .shift = 6, .width = 1, },
.range = &hifi_pll_mult_range,
.table = hifi_pll_params_table,