Re: [alsa-devel] [PATCH v2 02/10] clk: ccu-sun8i-a33: Add CLK_SET_RATE_PARENT to ac-dig

Hi,

On Tue, Jan 17, 2017 at 03:02:22PM +0100, Mylène Josserand wrote:

The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_PARENT" flag.

Signed-off-by: Mylène Josserand mylene.josserand@free-electrons.com

Please make sure to look at the prefixes usually used in the commit titles of the area you're working on. In this case that would have been "clk: sunxi-ng:". I fixed it, and applied.

Thanks! Maxime