Mark,
On Mon, Dec 22, 2008 at 12:06:05PM +0530, Medisetty, Naresh wrote:
Still I find difficulty to agree with Troy regarding the meaning
change of
SND_SOC_DAIFMT_NB_NF, since the existing meaning is correct w.r.t
davinci
McBSP.
Could you expand on that a bit - what are you referring to as the standard here? This could just be a case of different hardware manufacturers implementing slightly different things and giving them the same name.
Yes, Exactly it's just a case of different manufacturers implementing the same thing in different way.
I am referring the davinci ASP default polarities (without inversion) of FS and BCLK as standard. In davinci ASP Frame sync signals internal to the ASP are active high. The Frame sync clock (either FSX or FSR) is XORed with Frame sync polarity bit (FSXP or FSRP). So if the requirement is for frame sync active low FSXP and FSRP bits in PCR register should be set.
Similarly the BCLK (CLKX and CLKR) is XORed with BCLK polarity bit (CLKXP and CLKRP). Internally the transmit data driven on rising edge of CLKX and receive data sampled on falling edge of CLKR. To inverse this CLKXP and CLKRP should be set.
According to this the existing code is proper since it is not setting any polarity bits in _SOC_DAIFMT_NB_NF (Normal bit and Normal Frame )case.
And also in AIC33 codec there is no question of polarities since it is directly configurable through modes (either I2S or DSP).
Regards Naresh