Wolfson recommends using a higher frequency REFCLK for best performance rather than the default 32kHz reference clock source. We should set a good example and do so.
Signed-off-by: Charles Keepax ckeepax@opensource.wolfsonmicro.com --- sound/soc/samsung/bells.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/sound/soc/samsung/bells.c b/sound/soc/samsung/bells.c index 84f5d8b..89ad1d7 100644 --- a/sound/soc/samsung/bells.c +++ b/sound/soc/samsung/bells.c @@ -181,6 +181,24 @@ static int bells_late_probe(struct snd_soc_card *card) return ret; }
+ ret = snd_soc_codec_set_pll(codec, WM5102_FLL1_REFCLK, + ARIZONA_FLL_SRC_MCLK1, + MCLK_RATE, + bells->sysclk_rate); + if (ret != 0) { + dev_err(codec->dev, "Failed to set REFCLK for FLL1: %d\n", ret); + return ret; + } + + ret = snd_soc_codec_set_pll(codec, WM5102_FLL2_REFCLK, + ARIZONA_FLL_SRC_MCLK1, + MCLK_RATE, + bells->asyncclk_rate); + if (ret != 0) { + dev_err(codec->dev, "Failed to set REFCLK for FLL2: %d\n", ret); + return ret; + } + aif2_dai = card->rtd[DAI_CODEC_CP].cpu_dai;
ret = snd_soc_dai_set_sysclk(aif2_dai, ARIZONA_CLK_ASYNCCLK, 0, 0);