Thanks for taking the time to review this series of patches.
Mark Brown broonie@kernel.org writes:
On Mon, Mar 20, 2023 at 10:35:16PM +0200, Marian Postevca wrote:
To properly support a line of Huawei laptops with AMD CPU and a ES8336 codec connected to the ACP3X module we need to enable the S32 LE format and the codec option to divide the MCLK by 2.
The 32 bit support and MCLK division are two separate changes so should be two separate patches.
Ok, no problem, I just thought that a separate commit for one line was overkill.
- lrck_divider = es8316->sysclk / params_rate(params);
- mclk_div_option = device_property_read_bool(component->dev,
"everest,mclk-div-by-2");- if (mclk_div_option) {
This introduces a DT property but there's no documentation for it, but I don't see why we'd want this in the bindings - the driver should be able to tell from the input clock rate and required output/internal clocks if it needs to divide MCLK.
The problem here is that I have no knowledge what is the maximum MCLK that the codec accepts. According to the datasheet the maximum supported frequency of MCLK is 51.2 Mhz. But this doesn't seem to be the case in practice since a MCLK of 48Mhz causes noises in the sound output. The idea to divide the MCLK by 2 was proposed by a Everest Semiconductor engineer. So I don't know how to make this generic enough to be activated from the codec driver.
I cced the Everest Semiconductor engineers, maybe they have a proposal on how to activate this.