Hi Mark
Thank you for your review
- Gen1
- SRU : Sound Routing Unit
- SRC : Sampling Rate Converter
- CMD
- CTU : Channel Count Conversion Unit
- MIX : Mixer
- DVC : Digital Volume and Mute Function
- SSI : Serial Sound Interface
- Gen2
- SCU : Sampling Rate Converter Unit
- SRC : Sampling Rate Converter
- CMD
- CTU : Channel Count Conversion Unit
- MIX : Mixer
- DVC : Digital Volume and Mute Function
- SSIU : Serial Sound Interface Unit
- SSI : Serial Sound Interface
So, this hardware looks like something that should be using the soc-pcm framework or representing the SCU as a CODEC device but it seems that the final result here is going to be something that is open coded inside the CPU driver. This stuff doesn't all need to be added in the first version but it does need to be where we're heading.
I think it'd help review here to strip out a lot of the stubs that are in place and focus on just getting the basic functionality up and running then build up the functionality later. Right now it seems like there's a lot of internal structure in here that's not connected to the ASoC frameworks at all.
Please give me apology time
This SCU/SRU part do nothing on "feature point" in 1st patch set. But it has "SCU/SRU" register which will be used on SSI part. Yes, this Renesas sound IP has mixed register. And unfortunately, this mixed register mapping is different in Gen1/Gen2. (This register mapping difference between Gen1/Gen2 is absorbed in gen.c)
And additionally, the main feature of this SCU/SRU part is "sampling rate convert", but it has data path control register, and SSI-MODE setting register.
The main purpose of SCU/SRU part in 1st patch is... 1) to mapping register in the right position. (SCU/SRU register is handled in SCU/SRU patch) 2) to indicate it will control SCU/SRU feature in this driver. (in 2nd patch set) 3) to check function call timing. (SCU/SRU/SSI calling timing check)
I'm so sorry that I didn't explain about it.
Yes, this Renesas R-Car sound mixed register mapping (SCU/SRU/SSI) is one of my headache. 2nd headache is Gen1/Gen2 feature/register mapping difference.
Anyway, this 1st patch set has very basic playback/capture feature only ADG controls SSI clock, SCU/SRU has SSI mode register.
The image of these file/feature is like this
ASoC -> core -> SSI -> ADG/SCU/SRU
Best regards --- Kuninori Morimoto