Hi Mike,
On 07/01/2013 01:10 AM, Mike Looijmans wrote: [..]
The trouble with the current davinci driver is that the IRQ handler has a real-time requirement, it must finish before the next DMA block completes. This
I looked into this a little more.
I think you are picturing the following:
DMA transfer -> IRQ has to complete -> DMA transfer -> IRQ has to complete.. etc.
This is not really true in the davinci-pcm driver, the normal case without IRAM works more like..
DMA ----> DMA ---> DMA \ \ \ __ IRQ __ IRQ __ IRQ
The only hard requirement is the IRQ handler much finish updating before the next DMA transfer, or we're in trouble. Is this what you mean by real-time requirement, or did you mean something else?
Either way I'm sure your multi-slot approach is superior, but I don't see how you can get away with not updating the DMA addresses on every IRQ with the current davinci-pcm or EDMA controller (Unless you use a complicated mechanism like ping-pong where the address updates take care of itself). If you are using a set of chained slots, you only have so many slots so you have to continuously change addresses of the slots at some point or the other for a large transfer.
Thanks,
-Joel