Eliminate the follow smatch warning:
sound/soc/codecs/max98088.c:1112 max98088_dai_set_sysclk() warn: inconsistent indenting.
Reported-by: Abaci Robot abaci@linux.alibaba.com Signed-off-by: Jiapeng Chong jiapeng.chong@linux.alibaba.com --- sound/soc/codecs/max98088.c | 56 ++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c index 429717d4ac5a..bc03ecd749f9 100644 --- a/sound/soc/codecs/max98088.c +++ b/sound/soc/codecs/max98088.c @@ -1102,44 +1102,44 @@ static int max98088_dai2_hw_params(struct snd_pcm_substream *substream, static int max98088_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir) { - struct snd_soc_component *component = dai->component; - struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); + struct snd_soc_component *component = dai->component; + struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
- /* Requested clock frequency is already setup */ - if (freq == max98088->sysclk) - return 0; + /* Requested clock frequency is already setup */ + if (freq == max98088->sysclk) + return 0;
if (!IS_ERR(max98088->mclk)) { freq = clk_round_rate(max98088->mclk, freq); clk_set_rate(max98088->mclk, freq); }
- /* Setup clocks for slave mode, and using the PLL - * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) - * 0x02 (when master clk is 20MHz to 30MHz).. - */ - if ((freq >= 10000000) && (freq < 20000000)) { - snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10); - max98088->mclk_prescaler = 1; - } else if ((freq >= 20000000) && (freq < 30000000)) { - snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20); - max98088->mclk_prescaler = 2; - } else { - dev_err(component->dev, "Invalid master clock frequency\n"); - return -EINVAL; - } + /* Setup clocks for slave mode, and using the PLL + * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) + * 0x02 (when master clk is 20MHz to 30MHz).. + */ + if ((freq >= 10000000) && (freq < 20000000)) { + snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10); + max98088->mclk_prescaler = 1; + } else if ((freq >= 20000000) && (freq < 30000000)) { + snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20); + max98088->mclk_prescaler = 2; + } else { + dev_err(component->dev, "Invalid master clock frequency\n"); + return -EINVAL; + }
- if (snd_soc_component_read(component, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) { - snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, - M98088_SHDNRUN, 0); - snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, - M98088_SHDNRUN, M98088_SHDNRUN); - } + if (snd_soc_component_read(component, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) { + snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, + M98088_SHDNRUN, 0); + snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, + M98088_SHDNRUN, M98088_SHDNRUN); + }
- dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); + dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
- max98088->sysclk = freq; - return 0; + max98088->sysclk = freq; + return 0; }
static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,