July 2021 - Alsa-devel - mailman.alsa-project.org

[PATCH] ALSA: hda/realtek: add mic quirk for Acer SF314-42
by Alexander Monakov 03 Aug '21

03 Aug '21

The Acer Swift SF314-42 laptop is using Realtek ALC255 codec. Add a quirk so microphone in a headset connected via the right-hand side jack is usable. Signed-off-by: Alexander Monakov <amonakov(a)ispras.ru> Cc: Jaroslav Kysela <perex(a)perex.cz> Cc: Takashi Iwai <tiwai(a)suse.com> Cc: Hui Wang <hui.wang(a)canonical.com> Cc: Kailang Yang <kailang(a)realtek.com> Cc: Jeremy Szu <jeremy.szu(a)canonical.com> Cc: Jian-Hong Pan <jhp(a)endlessos.org> Cc: Chris Chiu <chris.chiu(a)canonical.com> Cc: PeiSen Hou <pshou(a)realtek.com> Cc: alsa-devel(a)alsa-project.org --- Hello, Acer Swift SF314-42 laptop is using AMD Ryzen SoC audio with Realtek ALC255 codec. The are three ALSA cards: HDMI audio, AMD ACP card, and AMD HDA card. There is an internal stereo microphone connected to the ACP card, and a mini-jack connected to the Realtek codec. There are no LEDs. I'd like to be able to use a mic+headphones headset. Unfortunately, out of the box ALSA does not correctly detect the microphone input of the Realtek codec. The suggested patch fixes that, though I cannot be sure it's 100% correct. With the patch, the experience is unfortunately still not ideal. I have noticed a couple of issues: 1) at high enough gain, recording the microphone is picking up what is being played via the headphones; maybe it's supposed to be like that, but it surprised me; 2) there is a very noticeable "pop" when plugging the headset in/out, accompanied by pcieport 0000:00:08.1: PME: Spurious native interrupt! pcieport 0000:00:08.1: PME: Spurious native interrupt! in dmesg. I'd appreciate info and any help about this issue. Thanks. Alexander sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index ab5113cccffa..87ad8469dbc5 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -8191,6 +8191,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1025, 0x1308, "Acer Aspire Z24-890", ALC286_FIXUP_ACER_AIO_HEADSET_MIC), SND_PCI_QUIRK(0x1025, 0x132a, "Acer TravelMate B114-21", ALC233_FIXUP_ACER_HEADSET_MIC), SND_PCI_QUIRK(0x1025, 0x1330, "Acer TravelMate X514-51T", ALC255_FIXUP_ACER_HEADSET_MIC), + SND_PCI_QUIRK(0x1025, 0x142b, "Acer Swift SF314-42", ALC255_FIXUP_ACER_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1025, 0x1430, "Acer TravelMate B311R-31", ALC256_FIXUP_ACER_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1025, 0x1466, "Acer Aspire A515-56", ALC255_FIXUP_ACER_HEADPHONE_AND_MIC), SND_PCI_QUIRK(0x1028, 0x0470, "Dell M101z", ALC269_FIXUP_DELL_M101Z), base-commit: 62fb9874f5da54fdb243003b386128037319b219 -- 2.31.1

3 7

Re: [PATCH v2 5/8] ASoC: mediatek: mt8195: add platform driver
by Chen-Yu Tsai 03 Aug '21

03 Aug '21

are all internal Hi, On Tue, Jun 29, 2021 at 9:49 AM Trevor Wu <trevor.wu(a)mediatek.com> wrote: > > This patch adds mt8195 platform and affiliated driver. > > Signed-off-by: Trevor Wu <trevor.wu(a)mediatek.com> > --- > sound/soc/mediatek/Kconfig | 9 + > sound/soc/mediatek/Makefile | 1 + > sound/soc/mediatek/mt8195/Makefile | 11 + > sound/soc/mediatek/mt8195/mt8195-afe-clk.c | 899 +++++ > sound/soc/mediatek/mt8195/mt8195-afe-clk.h | 201 + > sound/soc/mediatek/mt8195/mt8195-afe-common.h | 200 + > sound/soc/mediatek/mt8195/mt8195-afe-pcm.c | 3264 +++++++++++++++++ > sound/soc/mediatek/mt8195/mt8195-reg.h | 2793 ++++++++++++++ > 8 files changed, 7378 insertions(+) > create mode 100644 sound/soc/mediatek/mt8195/Makefile > create mode 100644 sound/soc/mediatek/mt8195/mt8195-afe-clk.c > create mode 100644 sound/soc/mediatek/mt8195/mt8195-afe-clk.h > create mode 100644 sound/soc/mediatek/mt8195/mt8195-afe-common.h > create mode 100644 sound/soc/mediatek/mt8195/mt8195-afe-pcm.c > create mode 100644 sound/soc/mediatek/mt8195/mt8195-reg.h > > diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig > index 74dae4332d17..3389f382be06 100644 > --- a/sound/soc/mediatek/Kconfig > +++ b/sound/soc/mediatek/Kconfig > @@ -184,3 +184,12 @@ config SND_SOC_MT8192_MT6359_RT1015_RT5682 > with the MT6359 RT1015 RT5682 audio codec. > Select Y if you have such device. > If unsure select "N". > + > +config SND_SOC_MT8195 > + tristate "ASoC support for Mediatek MT8195 chip" > + select SND_SOC_MEDIATEK > + help > + This adds ASoC platform driver support for Mediatek MT8195 chip > + that can be used with other codecs. > + Select Y if you have such device. > + If unsure select "N". > diff --git a/sound/soc/mediatek/Makefile b/sound/soc/mediatek/Makefile > index f6cb6b8508e3..34778ca12106 100644 > --- a/sound/soc/mediatek/Makefile > +++ b/sound/soc/mediatek/Makefile > @@ -5,3 +5,4 @@ obj-$(CONFIG_SND_SOC_MT6797) += mt6797/ > obj-$(CONFIG_SND_SOC_MT8173) += mt8173/ > obj-$(CONFIG_SND_SOC_MT8183) += mt8183/ > obj-$(CONFIG_SND_SOC_MT8192) += mt8192/ > +obj-$(CONFIG_SND_SOC_MT8195) += mt8195/ > diff --git a/sound/soc/mediatek/mt8195/Makefile b/sound/soc/mediatek/mt8195/Makefile > new file mode 100644 > index 000000000000..b2c9fd88f39e > --- /dev/null > +++ b/sound/soc/mediatek/mt8195/Makefile > @@ -0,0 +1,11 @@ > +# SPDX-License-Identifier: GPL-2.0 > + > +# platform driver > +snd-soc-mt8195-afe-objs := \ > + mt8195-afe-clk.o \ > + mt8195-afe-pcm.o \ > + mt8195-dai-adda.o \ > + mt8195-dai-etdm.o \ > + mt8195-dai-pcm.o > + > +obj-$(CONFIG_SND_SOC_MT8195) += snd-soc-mt8195-afe.o > diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c > new file mode 100644 > index 000000000000..57aa799b4f41 > --- /dev/null > +++ b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c > @@ -0,0 +1,899 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl > + * > + * Copyright (c) 2021 MediaTek Inc. > + * Author: Bicycle Tsai <bicycle.tsai(a)mediatek.com> > + * Trevor Wu <trevor.wu(a)mediatek.com> > + */ > + > +#include <linux/clk.h> > + > +#include "mt8195-afe-common.h" > +#include "mt8195-afe-clk.h" > +#include "mt8195-reg.h" > + > +static const char *aud_clks[MT8195_CLK_NUM] = { Most of these clocks are not described in the device tree binding. If the driver needs to reference them, they should be described. We should not be hard-coding clock names across different drivers. The more important question is, why does the driver need to reference all of them? Maybe we should take a step back and draw out a clock tree diagram for the hardware? > + /* xtal */ > + [MT8195_CLK_XTAL_26M] = "clk26m", > + /* pll */ > + [MT8195_CLK_APMIXED_APLL1] = "apll1", > + [MT8195_CLK_APMIXED_APLL2] = "apll2", > + [MT8195_CLK_APMIXED_APLL3] = "apll3", > + [MT8195_CLK_APMIXED_APLL4] = "apll4", > + [MT8195_CLK_APMIXED_APLL5] = "apll5", > + [MT8195_CLK_APMIXED_HDMIRX_APLL] = "hdmirx_apll", > + /* divider */ > + [MT8195_CLK_TOP_APLL1] = "apll1_ck", > + [MT8195_CLK_TOP_APLL1_D4] = "apll1_d4", > + [MT8195_CLK_TOP_APLL2] = "apll2_ck", > + [MT8195_CLK_TOP_APLL2_D4] = "apll2_d4", > + [MT8195_CLK_TOP_APLL3] = "apll3_ck", > + [MT8195_CLK_TOP_APLL3_D4] = "apll3_d4", > + [MT8195_CLK_TOP_APLL4] = "apll4_ck", > + [MT8195_CLK_TOP_APLL4_D4] = "apll4_d4", > + [MT8195_CLK_TOP_APLL5] = "apll5_ck", > + [MT8195_CLK_TOP_APLL5_D4] = "apll5_d4", > + [MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0", > + [MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1", > + [MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2", > + [MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3", > + [MT8195_CLK_TOP_APLL12_DIV4] = "apll12_div4", > + [MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9", > + [MT8195_CLK_TOP_HDMIRX_APLL] = "hdmirx_apll_ck", > + [MT8195_CLK_TOP_MAINPLL_D4_D4] = "mainpll_d4_d4", > + [MT8195_CLK_TOP_MAINPLL_D5_D2] = "mainpll_d5_d2", > + [MT8195_CLK_TOP_MAINPLL_D7_D2] = "mainpll_d7_d2", > + [MT8195_CLK_TOP_UNIVPLL_D4] = "univpll_d4", > + /* mux */ > + [MT8195_CLK_TOP_APLL1_SEL] = "apll1_sel", > + [MT8195_CLK_TOP_APLL2_SEL] = "apll2_sel", > + [MT8195_CLK_TOP_APLL3_SEL] = "apll3_sel", > + [MT8195_CLK_TOP_APLL4_SEL] = "apll4_sel", > + [MT8195_CLK_TOP_APLL5_SEL] = "apll5_sel", > + [MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel", > + [MT8195_CLK_TOP_A2SYS_SEL] = "a2sys_sel", > + [MT8195_CLK_TOP_A3SYS_SEL] = "a3sys_sel", > + [MT8195_CLK_TOP_A4SYS_SEL] = "a4sys_sel", > + [MT8195_CLK_TOP_ASM_H_SEL] = "asm_h_sel", > + [MT8195_CLK_TOP_ASM_M_SEL] = "asm_m_sel", > + [MT8195_CLK_TOP_ASM_L_SEL] = "asm_l_sel", > + [MT8195_CLK_TOP_AUD_IEC_SEL] = "aud_iec_sel", > + [MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel", > + [MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel", > + [MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel", > + [MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel", > + [MT8195_CLK_TOP_INTDIR_SEL] = "intdir_sel", > + [MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel", > + [MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel", > + [MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel", > + [MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel", > + /* clock gate */ > + [MT8195_CLK_TOP_MPHONE_SLAVE_B] = "mphone_slave_b", > + [MT8195_CLK_TOP_CFG_26M_AUD] = "cfg_26m_aud", > + [MT8195_CLK_INFRA_AO_AUDIO] = "infra_ao_audio", > + [MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b", > + [MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp", > + [MT8195_CLK_AUD_AFE] = "aud_afe", > + [MT8195_CLK_AUD_LRCK_CNT] = "aud_lrck_cnt", > + [MT8195_CLK_AUD_SPDIFIN_TUNER_APLL] = "aud_spdifin_tuner_apll", > + [MT8195_CLK_AUD_SPDIFIN_TUNER_DBG] = "aud_spdifin_tuner_dbg", > + [MT8195_CLK_AUD_UL_TML] = "aud_ul_tml", > + [MT8195_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner", > + [MT8195_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner", > + [MT8195_CLK_AUD_TOP0_SPDF] = "aud_top0_spdf", > + [MT8195_CLK_AUD_APLL] = "aud_apll", > + [MT8195_CLK_AUD_APLL2] = "aud_apll2", > + [MT8195_CLK_AUD_DAC] = "aud_dac", > + [MT8195_CLK_AUD_DAC_PREDIS] = "aud_dac_predis", > + [MT8195_CLK_AUD_TML] = "aud_tml", > + [MT8195_CLK_AUD_ADC] = "aud_adc", > + [MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires", > + [MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp", > + [MT8195_CLK_AUD_AFE_DMIC1] = "aud_afe_dmic1", > + [MT8195_CLK_AUD_AFE_DMIC2] = "aud_afe_dmic2", > + [MT8195_CLK_AUD_AFE_DMIC3] = "aud_afe_dmic3", > + [MT8195_CLK_AUD_AFE_DMIC4] = "aud_afe_dmic4", > + [MT8195_CLK_AUD_AFE_26M_DMIC_TM] = "aud_afe_26m_dmic_tm", > + [MT8195_CLK_AUD_UL_TML_HIRES] = "aud_ul_tml_hires", > + [MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires", > + [MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc", > + [MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires", > + [MT8195_CLK_AUD_LINEIN_TUNER] = "aud_linein_tuner", > + [MT8195_CLK_AUD_EARC_TUNER] = "aud_earc_tuner", > + [MT8195_CLK_AUD_I2SIN] = "aud_i2sin", > + [MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in", > + [MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out", > + [MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out", > + [MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out", > + [MT8195_CLK_AUD_ASRC11] = "aud_asrc11", > + [MT8195_CLK_AUD_ASRC12] = "aud_asrc12", > + [MT8195_CLK_AUD_MULTI_IN] = "aud_multi_in", > + [MT8195_CLK_AUD_INTDIR] = "aud_intdir", > + [MT8195_CLK_AUD_A1SYS] = "aud_a1sys", > + [MT8195_CLK_AUD_A2SYS] = "aud_a2sys", > + [MT8195_CLK_AUD_PCMIF] = "aud_pcmif", > + [MT8195_CLK_AUD_A3SYS] = "aud_a3sys", > + [MT8195_CLK_AUD_A4SYS] = "aud_a4sys", > + [MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1", > + [MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2", > + [MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3", > + [MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4", > + [MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5", > + [MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6", > + [MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8", > + [MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9", > + [MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10", > + [MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2", > + [MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3", > + [MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6", > + [MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7", > + [MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8", > + [MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10", > + [MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11", > + [MT8195_CLK_AUD_GASRC0] = "aud_gasrc0", > + [MT8195_CLK_AUD_GASRC1] = "aud_gasrc1", > + [MT8195_CLK_AUD_GASRC2] = "aud_gasrc2", > + [MT8195_CLK_AUD_GASRC3] = "aud_gasrc3", > + [MT8195_CLK_AUD_GASRC4] = "aud_gasrc4", > + [MT8195_CLK_AUD_GASRC5] = "aud_gasrc5", > + [MT8195_CLK_AUD_GASRC6] = "aud_gasrc6", > + [MT8195_CLK_AUD_GASRC7] = "aud_gasrc7", > + [MT8195_CLK_AUD_GASRC8] = "aud_gasrc8", > + [MT8195_CLK_AUD_GASRC9] = "aud_gasrc9", > + [MT8195_CLK_AUD_GASRC10] = "aud_gasrc10", > + [MT8195_CLK_AUD_GASRC11] = "aud_gasrc11", > + [MT8195_CLK_AUD_GASRC12] = "aud_gasrc12", > + [MT8195_CLK_AUD_GASRC13] = "aud_gasrc13", > + [MT8195_CLK_AUD_GASRC14] = "aud_gasrc14", > + [MT8195_CLK_AUD_GASRC15] = "aud_gasrc15", > + [MT8195_CLK_AUD_GASRC16] = "aud_gasrc16", > + [MT8195_CLK_AUD_GASRC17] = "aud_gasrc17", > + [MT8195_CLK_AUD_GASRC18] = "aud_gasrc18", > + [MT8195_CLK_AUD_GASRC19] = "aud_gasrc19", The MT8195_CLK_AUD_* clocks are all internal to the audio subsystem: the bits that control these clock gates are in the same address space as the audio parts. Would it be possible to model them as internal ASoC SUPPLY widgets? The external ones could be modeled using ASoC CLK_SUPPLY widgets, and the dependencies could be modeled with ASoC routes. The ASoC core could then handle power sequencing, which the driver currently does manually. IMO this is better than having two drivers handling two aspects of the same piece of hardware, while the two aspects are intertwined. Regards ChenYu

2 9

[PATCH v3 0/4] ASoC: codecs: wcd934x: add Headset and button detection support
by Srinivas Kandagatla 03 Aug '21

03 Aug '21

This patchset adds support to MBHC(Multi Button Headset Control) block found in Qualcomm WCD codecs. MBHC support headset type detection, both Mechanical and electrical insert/removal detection along with 8 buttons detection, Over current interrupts on HPHL/R, Impedance Measurements on HPHL/R. Eventhough MBHC block supports things like OverCurrent detection, Currently its reported as a kernel debug message. Should this be reported as an uevent to userspace? like the way USB reports? Any suggestions? First patch adds a common mbhc driver and the second one wcd934x specific driver changes along with sdm845 soundcard related changes. Common wcd-mbhc-v2 driver should be reusable across multiple codecs like WCD9335, WCD934x, WCD937x and WCD938x. Most of the work is derived from downstream Qualcomm kernels. Credits to various Qualcomm authors from Patrick Lai's team who have contributed to this code. Changes since v2: - switched to EXPORT_SYMBOL_GPL from EXPORT_SYMBOL - converted one of the if else to switch case. Srinivas Kandagatla (4): ASoC: dt-bindings: wcd934x: add bindings for Headset Button detection ASoC: codecs: wcd: add multi button Headset detection support ASoC: codecs: wcd934x: add mbhc support ASoC: qcom: sdm845: add jack support for WCD934x .../bindings/sound/qcom,wcd934x.yaml | 30 + include/linux/mfd/wcd934x/registers.h | 57 + sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/wcd-mbhc-v2.c | 1475 +++++++++++++++++ sound/soc/codecs/wcd-mbhc-v2.h | 340 ++++ sound/soc/codecs/wcd934x.c | 884 +++++++++- sound/soc/qcom/sdm845.c | 8 + 8 files changed, 2785 insertions(+), 15 deletions(-) create mode 100644 sound/soc/codecs/wcd-mbhc-v2.c create mode 100644 sound/soc/codecs/wcd-mbhc-v2.h -- 2.21.0

3 6

[PATCH v2 0/6] soundwire/ASoC: abstract platform-dependent bases
by Bard Liao 02 Aug '21

02 Aug '21

shim base and alh base are platform-dependent. This series suggests to use variables for those bases. It allows us to use different bases for new platforms. v2: - Update the commit message of "soundwire: move intel sdw register definitions to sdw_intel.h" Bard Liao (6): soundwire: move intel sdw register definitions to sdw_intel.h ASoC: SOF: intel: add sdw_shim/alh_base to sof_intel_dsp_desc ASoC: SOF: intel: hda: remove HDA_DSP_REG_SNDW_WAKE_STS definition ASoC: SOF: intel: move sof_intel_dsp_desc() forward ASoC: SOF: intel: add snd_sof_dsp_check_sdw_irq ops soundwire: intel: introduce shim and alh base drivers/soundwire/intel.c | 74 ------------------------ drivers/soundwire/intel_init.c | 14 ++--- include/linux/soundwire/sdw_intel.h | 87 +++++++++++++++++++++++++++++ sound/soc/sof/intel/cnl.c | 6 ++ sound/soc/sof/intel/hda.c | 39 ++++++++----- sound/soc/sof/intel/hda.h | 8 ++- sound/soc/sof/intel/icl.c | 3 + sound/soc/sof/intel/shim.h | 3 + sound/soc/sof/intel/tgl.c | 12 ++++ 9 files changed, 149 insertions(+), 97 deletions(-) -- 2.17.1

4 12

[PATCH v2] ASoC: amd: Fix reference to PCM buffer address
by Takashi Iwai 02 Aug '21

02 Aug '21

PCM buffers might be allocated dynamically when the buffer preallocation failed or a larger buffer is requested, and it's not guaranteed that substream->dma_buffer points to the actually used buffer. The driver needs to refer to substream->runtime->dma_addr instead for the buffer address. Cc: <stable(a)vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- v1->v2: Fix build error of renoir driver sound/soc/amd/acp-pcm-dma.c | 2 +- sound/soc/amd/raven/acp3x-pcm-dma.c | 2 +- sound/soc/amd/renoir/acp3x-pdm-dma.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c index 143155a840ac..cc1ce6f22caa 100644 --- a/sound/soc/amd/acp-pcm-dma.c +++ b/sound/soc/amd/acp-pcm-dma.c @@ -969,7 +969,7 @@ static int acp_dma_hw_params(struct snd_soc_component *component, acp_set_sram_bank_state(rtd->acp_mmio, 0, true); /* Save for runtime private data */ - rtd->dma_addr = substream->dma_buffer.addr; + rtd->dma_addr = runtime->dma_addr; rtd->order = get_order(size); /* Fill the page table entries in ACP SRAM */ diff --git a/sound/soc/amd/raven/acp3x-pcm-dma.c b/sound/soc/amd/raven/acp3x-pcm-dma.c index 8148b0d22e88..597d7c4b2a6b 100644 --- a/sound/soc/amd/raven/acp3x-pcm-dma.c +++ b/sound/soc/amd/raven/acp3x-pcm-dma.c @@ -286,7 +286,7 @@ static int acp3x_dma_hw_params(struct snd_soc_component *component, pr_err("pinfo failed\n"); } size = params_buffer_bytes(params); - rtd->dma_addr = substream->dma_buffer.addr; + rtd->dma_addr = substream->runtime->dma_addr; rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT); config_acp3x_dma(rtd, substream->stream); return 0; diff --git a/sound/soc/amd/renoir/acp3x-pdm-dma.c b/sound/soc/amd/renoir/acp3x-pdm-dma.c index bd20622b0933..0391c28dd078 100644 --- a/sound/soc/amd/renoir/acp3x-pdm-dma.c +++ b/sound/soc/amd/renoir/acp3x-pdm-dma.c @@ -242,7 +242,7 @@ static int acp_pdm_dma_hw_params(struct snd_soc_component *component, return -EINVAL; size = params_buffer_bytes(params); period_bytes = params_period_bytes(params); - rtd->dma_addr = substream->dma_buffer.addr; + rtd->dma_addr = substream->runtime->dma_addr; rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT); config_acp_dma(rtd, substream->stream); init_pdm_ring_buffer(MEM_WINDOW_START, size, period_bytes, -- 2.26.2

2 1

[PATCH v2 0/8] Add RZ/G2L Sound support
by Biju Das 02 Aug '21

02 Aug '21

This patch series aims to add ASoC support on RZ/G2L SoC's. It is based on the work done by Chris Brandt for RZ/A ASoC driver. Biju Das (8): ASoC: dt-bindings: Document RZ/G2L bindings sound: soc: sh: Add RZ/G2L SSIF-2 driver arm64: dts: renesas: r9a07g044: Add external audio clock nodes arm64: dts: renesas: r9a07g044: Add SSI support arm64: defconfig: Enable ASoC sound support for RZ/G2L SoC ASoC: dt-bindings: sound: renesas,rz-ssi: Document DMA support sound: sh: rz-ssi: Add SSI DMAC support arm64: dts: renesas: r9a07g044: Add SSI DMA support .../bindings/sound/renesas,rz-ssi.yaml | 100 ++ arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 105 ++ arch/arm64/configs/defconfig | 1 + sound/soc/sh/Kconfig | 10 + sound/soc/sh/Makefile | 4 + sound/soc/sh/rz-ssi.c | 1078 +++++++++++++++++ 6 files changed, 1298 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml create mode 100644 sound/soc/sh/rz-ssi.c -- 2.17.1

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[PATCH] ASoC: intel: skylake: Drop superfluous mmap callback
by Takashi Iwai 02 Aug '21

02 Aug '21

skl_platform_soc_mmap() just calls the standard mmap helper, hence it's superfluous. Let's drop it. Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/soc/intel/skylake/skl-pcm.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c index b1ca64d2f7ea..c604200de80e 100644 --- a/sound/soc/intel/skylake/skl-pcm.c +++ b/sound/soc/intel/skylake/skl-pcm.c @@ -1214,13 +1214,6 @@ static snd_pcm_uframes_t skl_platform_soc_pointer( return bytes_to_frames(substream->runtime, pos); } -static int skl_platform_soc_mmap(struct snd_soc_component *component, - struct snd_pcm_substream *substream, - struct vm_area_struct *area) -{ - return snd_pcm_lib_default_mmap(substream, area); -} - static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream, u64 nsec) { @@ -1460,7 +1453,6 @@ static const struct snd_soc_component_driver skl_component = { .trigger = skl_platform_soc_trigger, .pointer = skl_platform_soc_pointer, .get_time_info = skl_platform_soc_get_time_info, - .mmap = skl_platform_soc_mmap, .pcm_construct = skl_platform_soc_new, .module_get_upon_open = 1, /* increment refcount when a pcm is opened */ }; -- 2.26.2

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[PATCH 0/5] ASoC: Fix reference to PCM buffer address
by Takashi Iwai 02 Aug '21

02 Aug '21

Hi, while updating the memory allocation API for WC pages, I casually stumbled on quite a few drivers dealing with the PCM buffer address wrongly via substream->dma_buffer.addr. This patch series corrects those usages. Takashi === Takashi Iwai (5): ASoC: amd: Fix reference to PCM buffer address ASoC: intel: atom: Fix reference to PCM buffer address ASoC: xilinx: Fix reference to PCM buffer address ASoC: uniphier: Fix reference to PCM buffer address ASoC: kirkwood: Fix reference to PCM buffer address sound/soc/amd/acp-pcm-dma.c | 2 +- sound/soc/amd/raven/acp3x-pcm-dma.c | 2 +- sound/soc/amd/renoir/acp3x-pdm-dma.c | 2 +- sound/soc/intel/atom/sst-mfld-platform-pcm.c | 3 +-- sound/soc/kirkwood/kirkwood-dma.c | 26 ++++++++++++++------ sound/soc/uniphier/aio-dma.c | 2 +- sound/soc/xilinx/xlnx_formatter_pcm.c | 4 +-- 7 files changed, 25 insertions(+), 16 deletions(-) -- 2.26.2

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[PATCH 00/10] soundwire/ASoC: add mockup codec support
by Bard Liao 02 Aug '21

02 Aug '21

Adding mockup SoundWire codec is useful to debug driver/topology changes without having any actual device connected. Bard Liao (2): soundwire: stream: don't abort bank switch on Command_Ignored/-ENODATA soundwire: stream: don't program mockup device ports Pierre-Louis Bossart (8): ASoC: codecs: add SoundWire mockup device support ASoC: soc-acpi: cnl: add table for SoundWire mockup devices ASoC: soc-acpi: tgl: add table for SoundWire mockup devices ASoC: Intel: boards: sof_sdw: add SoundWire mockup codecs for tests soundwire: add flag to ignore all command/control for mockup devices soundwire: bus: squelch error returned by mockup devices soundwire: cadence: add debugfs interface for PDI loopbacks soundwire: cadence: override PDI configurations to create loopback drivers/soundwire/bus.c | 10 +- drivers/soundwire/cadence_master.c | 174 ++++++++-- drivers/soundwire/cadence_master.h | 3 + drivers/soundwire/stream.c | 5 +- include/linux/soundwire/sdw.h | 3 + sound/soc/codecs/Kconfig | 18 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/sdw-mockup.c | 312 ++++++++++++++++++ sound/soc/intel/boards/Kconfig | 1 + sound/soc/intel/boards/sof_sdw.c | 41 +++ sound/soc/intel/common/Makefile | 3 +- .../intel/common/soc-acpi-intel-cnl-match.c | 15 + .../common/soc-acpi-intel-sdw-mockup-match.c | 166 ++++++++++ .../common/soc-acpi-intel-sdw-mockup-match.h | 17 + .../intel/common/soc-acpi-intel-tgl-match.c | 23 ++ 15 files changed, 754 insertions(+), 39 deletions(-) create mode 100644 sound/soc/codecs/sdw-mockup.c create mode 100644 sound/soc/intel/common/soc-acpi-intel-sdw-mockup-match.c create mode 100644 sound/soc/intel/common/soc-acpi-intel-sdw-mockup-match.h -- 2.17.1

4 15

[PATCH] soundwire: cadence: add paranoid check on self-clearing bits
by Bard Liao 02 Aug '21

02 Aug '21

From: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> The Cadence IP exposes a small number of self-clearing bits in the MCP_CONTROL and MCP_CONFIG_UPDATE registers. We currently do not check that those bits are indeed cleared, e.g. during resume operations. That could lead to resuming peripheral devices too early. In addition, if we happen to read these registers, update one of the fields and write the register back, we may be writing stale data that might have been cleared in hardware. These sort of race conditions could lead to e.g. doing a hw_reset twice or stopping a clock that just restarted. There is no clear way of avoiding these potential race conditions other than making sure that these registers fields are cleared before any read-modify-write sequence. If we detect this sort of errors, we only log them since there is no clear recovery possible. The only way out is likely to restart the IP with a suspend/resume cycle. Note that the checks are performed before updating the registers, as well as after the Intel 'sync go' sequence in multi-link mode. That should cover both the start and end of suspend/resume hardware configurations. The Multi-Master mode gates the configuration updates until the 'sync go' signal is asserted, so we only check on init and after the end of the 'sync go' sequence. The duration of the usleep_range() was defined by the GSYNC frequency used in multi-master mode. With a 4kHz frequency, any configuration change might be deferred by up to 250us. Extending the range to 1000-1500us should guarantee that the configuration change is completed without any significant impact on the overall resume time. Suggested-by: Bard Liao <yung-chuan.liao(a)linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao(a)linux.intel.com> --- drivers/soundwire/cadence_master.c | 47 ++++++++++++++++++++++++++++++ drivers/soundwire/cadence_master.h | 4 +++ drivers/soundwire/intel.c | 14 +++++++++ 3 files changed, 65 insertions(+) diff --git a/drivers/soundwire/cadence_master.c b/drivers/soundwire/cadence_master.c index c7372519452b..0b7f037e6cd0 100644 --- a/drivers/soundwire/cadence_master.c +++ b/drivers/soundwire/cadence_master.c @@ -979,6 +979,49 @@ static void cdns_update_slave_status_work(struct work_struct *work) } +/* paranoia check to make sure self-cleared bits are indeed cleared */ +void sdw_cdns_check_self_clearing_bits(struct sdw_cdns *cdns, const char *string, + bool initial_delay, int reset_iterations) +{ + u32 mcp_control; + u32 mcp_config_update; + int i; + + if (initial_delay) + usleep_range(1000, 1500); + + mcp_control = cdns_readl(cdns, CDNS_MCP_CONTROL); + + /* the following bits should be cleared immediately */ + if (mcp_control & CDNS_MCP_CONTROL_CMD_RST) + dev_err(cdns->dev, "%s failed: MCP_CONTROL_CMD_RST is not cleared\n", string); + if (mcp_control & CDNS_MCP_CONTROL_SOFT_RST) + dev_err(cdns->dev, "%s failed: MCP_CONTROL_SOFT_RST is not cleared\n", string); + if (mcp_control & CDNS_MCP_CONTROL_SW_RST) + dev_err(cdns->dev, "%s failed: MCP_CONTROL_SW_RST is not cleared\n", string); + if (mcp_control & CDNS_MCP_CONTROL_CLK_STOP_CLR) + dev_err(cdns->dev, "%s failed: MCP_CONTROL_CLK_STOP_CLR is not cleared\n", string); + mcp_config_update = cdns_readl(cdns, CDNS_MCP_CONFIG_UPDATE); + if (mcp_config_update & CDNS_MCP_CONFIG_UPDATE_BIT) + dev_err(cdns->dev, "%s failed: MCP_CONFIG_UPDATE_BIT is not cleared\n", string); + + i = 0; + while (mcp_control & CDNS_MCP_CONTROL_HW_RST) { + if (i == reset_iterations) { + dev_err(cdns->dev, "%s failed: MCP_CONTROL_HW_RST is not cleared\n", string); + break; + } + + dev_dbg(cdns->dev, "%s: MCP_CONTROL_HW_RST is not cleared at iteration %d\n", string, i); + i++; + + usleep_range(1000, 1500); + mcp_control = cdns_readl(cdns, CDNS_MCP_CONTROL); + } + +} +EXPORT_SYMBOL(sdw_cdns_check_self_clearing_bits); + /* * init routines */ @@ -1256,6 +1299,8 @@ int sdw_cdns_init(struct sdw_cdns *cdns) cdns_init_clock_ctrl(cdns); + sdw_cdns_check_self_clearing_bits(cdns, __func__, false, 0); + /* reset msg_count to default value of FIFOLEVEL */ cdns->msg_count = cdns_readl(cdns, CDNS_MCP_FIFOLEVEL); @@ -1500,6 +1545,8 @@ int sdw_cdns_clock_stop(struct sdw_cdns *cdns, bool block_wake) struct sdw_slave *slave; int ret; + sdw_cdns_check_self_clearing_bits(cdns, __func__, false, 0); + /* Check suspend status */ if (sdw_cdns_is_clock_stop(cdns)) { dev_dbg(cdns->dev, "Clock is already stopped\n"); diff --git a/drivers/soundwire/cadence_master.h b/drivers/soundwire/cadence_master.h index 6c039d456ba8..e587aede63bf 100644 --- a/drivers/soundwire/cadence_master.h +++ b/drivers/soundwire/cadence_master.h @@ -187,4 +187,8 @@ int cdns_bus_conf(struct sdw_bus *bus, struct sdw_bus_params *params); int cdns_set_sdw_stream(struct snd_soc_dai *dai, void *stream, bool pcm, int direction); + +void sdw_cdns_check_self_clearing_bits(struct sdw_cdns *cdns, const char *string, + bool initial_delay, int reset_iterations); + #endif /* __SDW_CADENCE_H */ diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c index 15668d6fecd6..fb9c23e13206 100644 --- a/drivers/soundwire/intel.c +++ b/drivers/soundwire/intel.c @@ -23,6 +23,7 @@ #include "intel.h" #define INTEL_MASTER_SUSPEND_DELAY_MS 3000 +#define INTEL_MASTER_RESET_ITERATIONS 10 /* * debug/config flags for the Intel SoundWire Master. @@ -1393,6 +1394,8 @@ int intel_link_startup(struct auxiliary_device *auxdev) goto err_interrupt; } } + sdw_cdns_check_self_clearing_bits(cdns, __func__, + true, INTEL_MASTER_RESET_ITERATIONS); /* Register DAIs */ ret = intel_register_dai(sdw); @@ -1709,6 +1712,8 @@ static int __maybe_unused intel_resume(struct device *dev) return ret; } } + sdw_cdns_check_self_clearing_bits(cdns, __func__, + true, INTEL_MASTER_RESET_ITERATIONS); /* * after system resume, the pm_runtime suspend() may kick in @@ -1793,6 +1798,9 @@ static int __maybe_unused intel_resume_runtime(struct device *dev) return ret; } } + sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime TEARDOWN", + true, INTEL_MASTER_RESET_ITERATIONS); + } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) { ret = intel_init(sdw); if (ret) { @@ -1866,6 +1874,9 @@ static int __maybe_unused intel_resume_runtime(struct device *dev) } } } + sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime BUS_RESET", + true, INTEL_MASTER_RESET_ITERATIONS); + } else if (!clock_stop_quirks) { clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); @@ -1889,6 +1900,9 @@ static int __maybe_unused intel_resume_runtime(struct device *dev) dev_err(dev, "unable to resume master during resume\n"); return ret; } + + sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime no_quirks", + true, INTEL_MASTER_RESET_ITERATIONS); } else { dev_err(dev, "%s clock_stop_quirks %x unsupported\n", __func__, clock_stop_quirks); -- 2.17.1

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