June 2020 - Alsa-devel - mailman.alsa-project.org

[Resend PATCH] Add implicit feedback quirk for SSL2.
by Laurence Tratt 21 Jun '20

21 Jun '20

As expected, this requires the same quirk as the SSL2+ in order for the clock to sync. This was suggested by, and tested on an SSL2, by Dmitry. Suggested-by: Dmitry <dpavlushko(a)gmail.com> Signed-off-by: Laurence Tratt <laurie(a)tratt.net> --- sound/usb/pcm.c | 1 + 1 file changed, 1 insertion(+) diff --git sound/usb/pcm.c sound/usb/pcm.c index 84c0ae4319..dc1608bdf6 100644 --- sound/usb/pcm.c +++ sound/usb/pcm.c @@ -367,6 +367,7 @@ static int set_sync_ep_implicit_fb_quirk(struct snd_usb_substream *subs, ifnum = 0; goto add_sync_ep_from_ifnum; case USB_ID(0x07fd, 0x0008): /* MOTU M Series */ + case USB_ID(0x31e9, 0x0001): /* Solid State Logic SSL2 */ case USB_ID(0x31e9, 0x0002): /* Solid State Logic SSL2+ */ ep = 0x81; ifnum = 2; -- 2.27.0

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[HDAudio][ALC295] speakers not working on Acer Travelmate P614
by Stanislav Kazmin 21 Jun '20

21 Jun '20

Hello, I have the following problem on my Acer TravelMate P614-51T-G2: I have all the audio sinks correctly identified (like HDMI, DMic, Headphones) but the internal speakers do not produce any sound. What I have tried so far: - hard/soft shutdown on Windows and reboot - disable/re-enable speakers and microphone in BIOS - uninstall pulseaudio and test alsa alone (so it is defeitely **not** a pulseaudio issue) - switch from sof-hda-dsp to snd-hda-intel driver (without Dmic support) - retask pins 0x14, 0x16, 0x1b to "Internal Speakers" through hdajackretask (only basic, without advanced features) - removed/reconnected the headphones `alsamixer` shows all needed sinks and nothing is muted. I already discussed the issue at sof github https://github.com/thesofproject/ sof/issues/3058 but since the same issue occurs on `snd-hda-intel` legacy river, I was advised to communicate with alsa-devel team. The alsa-info.sh result are linked at http://alsa-project.org/db/? f=252f92c7a1df3c755d16ee69353b26d2535a4d81 I have tested the kernel 5.8-rc1 but it does not make any difference. Let me know if I can do anything else to test the issue.

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Lock-free dmix considered harmful
by Maarten Baert 20 Jun '20

20 Jun '20

I'm in the process of adding monitoring support to dmix (i.e. the ability for applications to capture the sound being played back through the speakers) - expect patches for this soon. However while reading the dmix source code I came across something weird. Dmix uses a lock-free mixing implementation based on (architecture-dependent) atomic operations such as atomic addition and compare-exchange. However at the same time dmix also uses a semaphore to prevent multiple processes from accessing the shared memory buffers simultaneously. This is redundant and makes the lock-free implementation rather pointless. Out of curiosity I decided to measure the time it takes to execute snd_pcm_dmix_sync_area for these three cases: - A simple locked implementation, which acquires the semaphore and then does mixing using the non-concurrent code from pcm_dmix_generic.c. - The current (redundant) implementation, which acquires the semaphore and then does atomic mixing. - A lock-free implementation, which does not acquire the semaphore and does atomic mixing. The resulting sound is identical in all three cases. (As a sanity check I also tested the 4th case, non-concurrent code without locking, which as expected produces audio with glitches.) I tested each case with 1, 4 and 20 simultaneous playback streams (multiple instances of 'aplay') on a system with 4 physical CPU cores (Intel Core i7-4770). You can see the results here: https://misc.maartenbaert.be/dmix_perf_locked_atomic.png The results are quite surprising: - The locked implementation is 3 to 6 times *faster* than the current redundant implementation. - The lock-free implementation is usually about as fast as the current redundant implementation, but has extreme outliers that are up to 3 times *slower* than the redundant implementation when there are multiple threads. It seems that the overhead of the atomic operations is so high that it completely negates the theoretical advantage of being able to mix from multiple threads simultaneously. This may be the result of 'false sharing' when multiple threads are accessing different words in the same cache line (which is almost impossible to avoid when mixing audio). On a related note, I believe that I have also found a bug in the lock-free implementation. The logic which is used to clear the 'sum' buffer is as follows: sample = *src; old_sample = *sum; if (ARCH_CMPXCHG(dst, 0, 1) == 0) sample -= old_sample; ARCH_ADD(sum, sample); This takes advantage of the fact that the hardware driver clears the playback buffer after reading it. However it does not account for the possibility that 'dst' might be zero for other reasons, such as: - An application plays back silence. - An application plays back sound, but then rewinds it. - Multiple applications play back sound which just happens to sum to zero occasionally. These all result in situations where 'dst' is changed from 0 to 1 by the compare-exchange operation, but then changed back to zero later, resulting in the classic 'ABA problem'. However this problem is currently hidden by the fact that the lock-free implementation is in fact still locked. Because of these reasons I think it would be better to drop the lock-free implementation entirely and just use the existing non-concurrent architecture-independent implementation from pcm_dmix_generic.c. Aside from being faster, it would also eliminate a lot of architecture-dependent code and inline assembly. Should I submit a patch for this? Best regards, Maarten Baert

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[PATCH] snd-usb-audio: add quirk for MacroSilicon MS2109
by Hector Martin 20 Jun '20

20 Jun '20

These devices claim to be 96kHz mono, but actually are 48kHz stereo with swapped channels and unaligned transfers. Signed-off-by: Hector Martin <marcan(a)marcan.st> Cc: stable(a)vger.kernel.org --- sound/usb/quirks-table.h | 52 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h index 4ec491011b19..9092cc0aa807 100644 --- a/sound/usb/quirks-table.h +++ b/sound/usb/quirks-table.h @@ -3633,4 +3633,56 @@ ALC1220_VB_DESKTOP(0x26ce, 0x0a01), /* Asrock TRX40 Creator */ } }, +/* + * MacroSilicon MS2109 based HDMI capture cards + * + * These claim 96kHz 1ch in the descriptors, but are actually 48kHz 2ch. + * They also need QUIRK_AUDIO_ALIGN_TRANSFER, which makes one wonder if + * they pretend to be 96kHz mono as a workaround for stereo being broken + * by that... + * + * They also have swapped L-R channels, but that's for userspace to deal + * with. + */ +{ + USB_DEVICE(0x534d, 0x2109), + .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) { + .vendor_name = "MacroSilicon", + .product_name = "MS2109", + .ifnum = QUIRK_ANY_INTERFACE, + .type = QUIRK_COMPOSITE, + .data = &(const struct snd_usb_audio_quirk[]) { + { + .ifnum = 2, + .type = QUIRK_AUDIO_ALIGN_TRANSFER, + }, + { + .ifnum = 2, + .type = QUIRK_AUDIO_STANDARD_MIXER, + }, + { + .ifnum = 3, + .type = QUIRK_AUDIO_FIXED_ENDPOINT, + .data = &(const struct audioformat) { + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .channels = 2, + .iface = 3, + .altsetting = 1, + .altset_idx = 1, + .attributes = 0, + .endpoint = 0x82, + .ep_attr = USB_ENDPOINT_XFER_ISOC | + USB_ENDPOINT_SYNC_ASYNC, + .rates = SNDRV_PCM_RATE_CONTINUOUS, + .rate_min = 48000, + .rate_max = 48000, + } + }, + { + .ifnum = -1 + } + } + } +}, + #undef USB_DEVICE_VENDOR_SPEC -- 2.27.0

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How to populate required string as audio endpoint name in gnome audio devices tab
by Mukunda,Vijendar 20 Jun '20

20 Jun '20

Renoir platform has onboard dmic + south bridge HD Audio endpoint support. For onboard Dmic, Audio endpoint name is populated as "Analog Input" in Audio input devices. How can we populate name as "Internal Mic" or "Dmic" in audio input devices tab in sound settings? Alsa info link: https://pastebin.ubuntu.com/p/4kprhDZYbg/ Pluse audio info output: https://pastebin.ubuntu.com/p/sdx9Xs234C/ Thanks, Vijendar

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Re: [PATCH 2/2] ASoC: qcom: add apq8039 sound card support
by kernel test robot 20 Jun '20

20 Jun '20

Hi Pantelis, I love your patch! Perhaps something to improve: [auto build test WARNING on asoc/for-next] [also build test WARNING on sound/for-next v5.8-rc1 next-20200618] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Pantelis-Antoniou/ASoC-qcom-add-ap… base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next config: i386-allyesconfig (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 reproduce (this is a W=1 build): # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com> All warnings (new ones prefixed by >>, old ones prefixed by <<): In file included from arch/x86/include/asm/page_32.h:35, from arch/x86/include/asm/page.h:14, from arch/x86/include/asm/thread_info.h:12, from include/linux/thread_info.h:38, from arch/x86/include/asm/preempt.h:7, from include/linux/preempt.h:78, from include/linux/rcupdate.h:27, from include/linux/rculist.h:11, from include/linux/pid.h:5, from include/linux/sched.h:14, from include/linux/ratelimit.h:6, from include/linux/dev_printk.h:16, from include/linux/device.h:15, from sound/soc/qcom/apq8039.c:5: In function 'strncpy', inlined from 'snd_soc_card_ctl_getset.constprop' at sound/soc/qcom/apq8039.c:176:5: >> include/linux/string.h:297:30: warning: '__builtin_strncpy' destination unchanged after copying no bytes [-Wstringop-truncation] 297 | #define __underlying_strncpy __builtin_strncpy | ^ include/linux/string.h:307:9: note: in expansion of macro '__underlying_strncpy' 307 | return __underlying_strncpy(p, q, size); | ^~~~~~~~~~~~~~~~~~~~ vim +/__builtin_strncpy +297 include/linux/string.h 47227d27e2fcb0 Daniel Axtens 2020-06-03 275 47227d27e2fcb0 Daniel Axtens 2020-06-03 276 #ifdef CONFIG_KASAN 47227d27e2fcb0 Daniel Axtens 2020-06-03 277 extern void *__underlying_memchr(const void *p, int c, __kernel_size_t size) __RENAME(memchr); 47227d27e2fcb0 Daniel Axtens 2020-06-03 278 extern int __underlying_memcmp(const void *p, const void *q, __kernel_size_t size) __RENAME(memcmp); 47227d27e2fcb0 Daniel Axtens 2020-06-03 279 extern void *__underlying_memcpy(void *p, const void *q, __kernel_size_t size) __RENAME(memcpy); 47227d27e2fcb0 Daniel Axtens 2020-06-03 280 extern void *__underlying_memmove(void *p, const void *q, __kernel_size_t size) __RENAME(memmove); 47227d27e2fcb0 Daniel Axtens 2020-06-03 281 extern void *__underlying_memset(void *p, int c, __kernel_size_t size) __RENAME(memset); 47227d27e2fcb0 Daniel Axtens 2020-06-03 282 extern char *__underlying_strcat(char *p, const char *q) __RENAME(strcat); 47227d27e2fcb0 Daniel Axtens 2020-06-03 283 extern char *__underlying_strcpy(char *p, const char *q) __RENAME(strcpy); 47227d27e2fcb0 Daniel Axtens 2020-06-03 284 extern __kernel_size_t __underlying_strlen(const char *p) __RENAME(strlen); 47227d27e2fcb0 Daniel Axtens 2020-06-03 285 extern char *__underlying_strncat(char *p, const char *q, __kernel_size_t count) __RENAME(strncat); 47227d27e2fcb0 Daniel Axtens 2020-06-03 286 extern char *__underlying_strncpy(char *p, const char *q, __kernel_size_t size) __RENAME(strncpy); 47227d27e2fcb0 Daniel Axtens 2020-06-03 287 #else 47227d27e2fcb0 Daniel Axtens 2020-06-03 288 #define __underlying_memchr __builtin_memchr 47227d27e2fcb0 Daniel Axtens 2020-06-03 289 #define __underlying_memcmp __builtin_memcmp 47227d27e2fcb0 Daniel Axtens 2020-06-03 290 #define __underlying_memcpy __builtin_memcpy 47227d27e2fcb0 Daniel Axtens 2020-06-03 291 #define __underlying_memmove __builtin_memmove 47227d27e2fcb0 Daniel Axtens 2020-06-03 292 #define __underlying_memset __builtin_memset 47227d27e2fcb0 Daniel Axtens 2020-06-03 293 #define __underlying_strcat __builtin_strcat 47227d27e2fcb0 Daniel Axtens 2020-06-03 294 #define __underlying_strcpy __builtin_strcpy 47227d27e2fcb0 Daniel Axtens 2020-06-03 295 #define __underlying_strlen __builtin_strlen 47227d27e2fcb0 Daniel Axtens 2020-06-03 296 #define __underlying_strncat __builtin_strncat 47227d27e2fcb0 Daniel Axtens 2020-06-03 @297 #define __underlying_strncpy __builtin_strncpy 47227d27e2fcb0 Daniel Axtens 2020-06-03 298 #endif 47227d27e2fcb0 Daniel Axtens 2020-06-03 299 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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Re: [PATCH 2/2] ASoC: qcom: add apq8039 sound card support
by kernel test robot 19 Jun '20

19 Jun '20

Hi Pantelis, I love your patch! Perhaps something to improve: [auto build test WARNING on asoc/for-next] [also build test WARNING on sound/for-next v5.8-rc1 next-20200618] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Pantelis-Antoniou/ASoC-qcom-add-ap… base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next config: parisc-allyesconfig (attached as .config) compiler: hppa-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=parisc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp(a)intel.com> All warnings (new ones prefixed by >>, old ones prefixed by <<): sound/soc/qcom/apq8039.c: In function 'snd_soc_card_ctl_getset.constprop': >> sound/soc/qcom/apq8039.c:176:5: warning: 'strncpy' destination unchanged after copying no bytes [-Wstringop-truncation] 176 | strncpy(orig, uinfo->value.enumerated.name, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 177 | origsz); | ~~~~~~~ vim +/strncpy +176 sound/soc/qcom/apq8039.c 67 68 static int 69 snd_soc_card_ctl_getset(struct snd_soc_card *card, 70 const char *name, 71 char *orig, size_t origsz, const char *value) 72 { 73 struct snd_kcontrol *ctl; 74 struct snd_ctl_elem_info *uinfo = NULL; 75 struct snd_ctl_elem_value *uctl = NULL; 76 unsigned int i, count; 77 int ret; 78 79 /* get the control */ 80 ctl = snd_soc_card_ctl_find(card, name, NULL); 81 if (!ctl) 82 return -ENOENT; 83 84 /* allocate info and value */ 85 uinfo = kzalloc(sizeof(*uinfo), GFP_KERNEL); 86 uctl = kzalloc(sizeof(*uctl), GFP_KERNEL); 87 if (!uinfo || !uctl) { 88 ret = -ENOMEM; 89 goto out_free; 90 } 91 92 ret = ctl->info(ctl, uinfo); 93 if (ret) 94 goto out_free; 95 if (uinfo->count != 1) { 96 ret = -ENOTSUPP; 97 goto out_free; 98 } 99 100 ret = ctl->get(ctl, uctl); 101 if (ret) 102 goto out_free; 103 104 ret = 0; 105 106 switch (uinfo->type) { 107 108 case SNDRV_CTL_ELEM_TYPE_NONE: 109 break; 110 111 case SNDRV_CTL_ELEM_TYPE_BOOLEAN: 112 if (orig && origsz > 0) 113 snprintf(orig, origsz, "%s", 114 uctl->value.integer.value[0] ? 115 "true" : "false"); 116 117 if (value) { 118 bool bval; 119 120 ret = kstrtobool(value, &bval); 121 if (ret) 122 goto out_free; 123 uctl->value.integer.value[0] = !!bval; 124 125 } 126 break; 127 128 case SNDRV_CTL_ELEM_TYPE_INTEGER: 129 if (orig && origsz > 0) 130 snprintf(orig, origsz, "%ld", 131 uctl->value.integer.value[0]); 132 133 if (value) { 134 ret = kstrtol(value, 10, 135 &uctl->value.integer.value[0]); 136 if (ret) 137 goto out_free; 138 } 139 break; 140 141 case SNDRV_CTL_ELEM_TYPE_ENUMERATED: 142 count = uinfo->value.enumerated.items; 143 144 if (value) { /* set */ 145 for (i = 0; i < count; i++) { 146 uinfo->value.enumerated.item = i; 147 ret = ctl->info(ctl, uinfo); 148 if (ret) 149 goto out_free; 150 151 if (!strcmp(value, 152 uinfo->value.enumerated.name)) 153 break; 154 } 155 156 /* setting without finding the enum */ 157 if (i >= count) { 158 ret = -EINVAL; 159 goto out_free; 160 } 161 uctl->value.enumerated.item[0] = i; 162 } else { /* get */ 163 uinfo->value.enumerated.item = 164 uctl->value.enumerated.item[0]; 165 ret = ctl->info(ctl, uinfo); 166 if (ret) 167 goto out_free; 168 169 if (orig && origsz) { 170 if (origsz < 171 strlen(uinfo->value.enumerated.name) 172 + 1) { 173 ret = -ENOSPC; 174 goto out_free; 175 } > 176 strncpy(orig, uinfo->value.enumerated.name, 177 origsz); 178 } 179 } 180 break; 181 182 case SNDRV_CTL_ELEM_TYPE_INTEGER64: 183 if (orig && origsz > 0) 184 snprintf(orig, origsz, "%lld", 185 uctl->value.integer64.value[0]); 186 187 if (value) { 188 ret = kstrtoll(value, 10, 189 &uctl->value.integer64.value[0]); 190 if (ret) 191 goto out_free; 192 } 193 break; 194 195 case SNDRV_CTL_ELEM_TYPE_BYTES: 196 case SNDRV_CTL_ELEM_TYPE_IEC958: 197 ret = -ENOTSUPP; 198 goto out_free; 199 default: 200 ret = -EINVAL; 201 goto out_free; 202 } 203 204 if (value) { 205 ret = ctl->put(ctl, uctl); 206 if (ret < 0) 207 goto out_free; 208 209 /* if it changed, report change to user space */ 210 if (ret > 0) 211 snd_ctl_notify(card->snd_card, 212 SNDRV_CTL_EVENT_MASK_VALUE, 213 &uctl->id); 214 } 215 216 out_free: 217 kfree(uctl); 218 kfree(uinfo); 219 220 if (ret < 0) 221 dev_err(card->dev, "%s: %s operation failed for \"%s\"", 222 __func__, value ? "set" : "get", name); 223 224 return ret; 225 } 226 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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[PATCH] ASoC: Intel: haswell: Power transition refactor
by Cezary Rojewski 19 Jun '20

19 Jun '20

Update D0 <-> D3 sequence to correctly transition hardware and DSP core from and to D3. On top of that, set SHIM registers to their recommended defaults during D0 and D3 proceduces as HW does not reset registers for us. Connected to: [alsa-devel][BUG] bdw-rt5650 DSP boot timeout https://mailman.alsa-project.org/pipermail/alsa-devel/2019-July/153098.html Github issue ticket reference: https://github.com/thesofproject/linux/pull/1842 Tested on: - BDW-Y RVP with rt286 - SAMUS with rt5677 Proposed solution (both in July 2019 and on github): 'Revert "ASoC: Intel: Work around to fix HW d3 potential crash issue"' is NAKed as it only covers the problem up and actually brings back the undefined behavior: some registers (e.g.: APLLSE) are describing LPT offsets rather than WPT ones. In consequence, during power-transitions driver issues incorrect writes and leaves the regs of interest alone. Existing patch - the non-revert - does not resolve the HW D3 issue at all as it ignores the recommended sequence and does not initialize hardware registers as expected. And thus, leaving things as are is also unacceptable. Signed-off-by: Cezary Rojewski <cezary.rojewski(a)intel.com> --- sound/soc/intel/haswell/sst-haswell-dsp.c | 185 ++++++++++++---------- 1 file changed, 104 insertions(+), 81 deletions(-) diff --git a/sound/soc/intel/haswell/sst-haswell-dsp.c b/sound/soc/intel/haswell/sst-haswell-dsp.c index 88c3f63bded9..de80e19454c1 100644 --- a/sound/soc/intel/haswell/sst-haswell-dsp.c +++ b/sound/soc/intel/haswell/sst-haswell-dsp.c @@ -243,45 +243,92 @@ static irqreturn_t hsw_irq(int irq, void *context) return ret; } +#define CSR_DEFAULT_VALUE 0x8480040E +#define ISC_DEFAULT_VALUE 0x0 +#define ISD_DEFAULT_VALUE 0x0 +#define IMC_DEFAULT_VALUE 0x7FFF0003 +#define IMD_DEFAULT_VALUE 0x7FFF0003 +#define IPCC_DEFAULT_VALUE 0x0 +#define IPCD_DEFAULT_VALUE 0x0 +#define CLKCTL_DEFAULT_VALUE 0x7FF +#define CSR2_DEFAULT_VALUE 0x0 +#define LTR_CTRL_DEFAULT_VALUE 0x0 +#define HMD_CTRL_DEFAULT_VALUE 0x0 + +static void hsw_set_shim_defaults(struct sst_dsp *sst) +{ + sst_dsp_shim_write_unlocked(sst, SST_CSR, CSR_DEFAULT_VALUE); + sst_dsp_shim_write_unlocked(sst, SST_ISRX, ISC_DEFAULT_VALUE); + sst_dsp_shim_write_unlocked(sst, SST_ISRD, ISD_DEFAULT_VALUE); + sst_dsp_shim_write_unlocked(sst, SST_IMRX, IMC_DEFAULT_VALUE); + sst_dsp_shim_write_unlocked(sst, SST_IMRD, IMD_DEFAULT_VALUE); + sst_dsp_shim_write_unlocked(sst, SST_IPCX, IPCC_DEFAULT_VALUE); + sst_dsp_shim_write_unlocked(sst, SST_IPCD, IPCD_DEFAULT_VALUE); + sst_dsp_shim_write_unlocked(sst, SST_CLKCTL, CLKCTL_DEFAULT_VALUE); + sst_dsp_shim_write_unlocked(sst, SST_CSR2, CSR2_DEFAULT_VALUE); + sst_dsp_shim_write_unlocked(sst, SST_LTRC, LTR_CTRL_DEFAULT_VALUE); + sst_dsp_shim_write_unlocked(sst, SST_HMDC, HMD_CTRL_DEFAULT_VALUE); +} + +/* all clock-gating minus DCLCGE and DTCGE */ +#define SST_VDRTCL2_CG_OTHER 0xB7D + static void hsw_set_dsp_D3(struct sst_dsp *sst) { - u32 val; u32 reg; - /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ + /* disable clock core gating */ reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); - reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE); + reg &= ~(SST_VDRTCL2_DCLCGE); writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); - /* enable power gating and switch off DRAM & IRAM blocks */ - val = readl(sst->addr.pci_cfg + SST_VDRTCTL0); - val |= SST_VDRTCL0_DSRAMPGE_MASK | - SST_VDRTCL0_ISRAMPGE_MASK; - val &= ~(SST_VDRTCL0_D3PGD | SST_VDRTCL0_D3SRAMPGD); - writel(val, sst->addr.pci_cfg + SST_VDRTCTL0); + /* stall, reset and set 24MHz XOSC */ + sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, + SST_CSR_24MHZ_LPCS | SST_CSR_STALL | SST_CSR_RST, + SST_CSR_24MHZ_LPCS | SST_CSR_STALL | SST_CSR_RST); - /* switch off audio PLL */ - val = readl(sst->addr.pci_cfg + SST_VDRTCTL2); - val |= SST_VDRTCL2_APLLSE_MASK; - writel(val, sst->addr.pci_cfg + SST_VDRTCTL2); + /* DRAM power gating all */ + reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); + reg |= SST_VDRTCL0_ISRAMPGE_MASK | + SST_VDRTCL0_DSRAMPGE_MASK; + reg &= ~(SST_VDRTCL0_D3SRAMPGD); + reg |= SST_VDRTCL0_D3PGD; + writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0); + udelay(50); - /* disable MCLK(clkctl.smos = 0) */ - sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL, - SST_CLKCTL_MASK, 0); + /* PLL shutdown enable */ + reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); + reg |= SST_VDRTCL2_APLLSE_MASK; + writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); - /* Set D3 state, delay 50 us */ - val = readl(sst->addr.pci_cfg + SST_PMCS); - val |= SST_PMCS_PS_MASK; - writel(val, sst->addr.pci_cfg + SST_PMCS); - udelay(50); + /* disable MCLK */ + sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL, + SST_CLKCTL_MASK, 0); - /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */ + /* switch clock gating */ + reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); + reg |= SST_VDRTCL2_CG_OTHER; + reg &= ~(SST_VDRTCL2_DTCGE); + writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); + /* enable DTCGE separatelly */ reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); - reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE; + reg |= SST_VDRTCL2_DTCGE; writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); + /* set shim defaults */ + hsw_set_shim_defaults(sst); + + /* set D3 */ + reg = readl(sst->addr.pci_cfg + SST_PMCS); + reg |= SST_PMCS_PS_MASK; + writel(reg, sst->addr.pci_cfg + SST_PMCS); udelay(50); + /* enable clock core gating */ + reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); + reg |= SST_VDRTCL2_DCLCGE; + writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); + udelay(50); } static void hsw_reset(struct sst_dsp *sst) @@ -299,75 +346,62 @@ static void hsw_reset(struct sst_dsp *sst) SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL); } +/* recommended CSR state for power-up */ +#define SST_CSR_D0_MASK (0x18A09C0C | SST_CSR_DCS_MASK) + static int hsw_set_dsp_D0(struct sst_dsp *sst) { - int tries = 10; - u32 reg, fw_dump_bit; + u32 reg; - /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ + /* disable clock core gating */ reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); - reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE); + reg &= ~(SST_VDRTCL2_DCLCGE); writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); - /* Disable D3PG (VDRTCTL0.D3PGD = 1) */ - reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); - reg |= SST_VDRTCL0_D3PGD; - writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0); + /* switch clock gating */ + reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); + reg |= SST_VDRTCL2_CG_OTHER; + reg &= ~(SST_VDRTCL2_DTCGE); + writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); - /* Set D0 state */ + /* set D0 */ reg = readl(sst->addr.pci_cfg + SST_PMCS); - reg &= ~SST_PMCS_PS_MASK; + reg &= ~(SST_PMCS_PS_MASK); writel(reg, sst->addr.pci_cfg + SST_PMCS); - /* check that ADSP shim is enabled */ - while (tries--) { - reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK; - if (reg == 0) - goto finish; - - msleep(1); - } - - return -ENODEV; - -finish: - /* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */ - sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, - SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0); + /* DRAM power gating none */ + reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); + reg &= ~(SST_VDRTCL0_ISRAMPGE_MASK | + SST_VDRTCL0_DSRAMPGE_MASK); + reg |= SST_VDRTCL0_D3SRAMPGD; + reg |= SST_VDRTCL0_D3PGD; + writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0); + mdelay(10); - /* stall DSP core, set clk to 192/96Mhz */ - sst_dsp_shim_update_bits_unlocked(sst, - SST_CSR, SST_CSR_STALL | SST_CSR_DCS_MASK, - SST_CSR_STALL | SST_CSR_DCS(4)); + /* set shim defaults */ + hsw_set_shim_defaults(sst); - /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */ + /* restore MCLK */ sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL, - SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0, - SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0); + SST_CLKCTL_MASK, SST_CLKCTL_MASK); - /* Stall and reset core, set CSR */ - hsw_reset(sst); - - /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */ + /* PLL shutdown disable */ reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); - reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE; + reg &= ~(SST_VDRTCL2_APLLSE_MASK); writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); + sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, + SST_CSR_D0_MASK, SST_CSR_SBCS0 | SST_CSR_SBCS1 | + SST_CSR_STALL | SST_CSR_DCS(4)); udelay(50); - /* switch on audio PLL */ + /* enable clock core gating */ reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); - reg &= ~SST_VDRTCL2_APLLSE_MASK; + reg |= SST_VDRTCL2_DCLCGE; writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); - /* set default power gating control, enable power gating control for all blocks. that is, - can't be accessed, please enable each block before accessing. */ - reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); - reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK; - /* for D0, always enable the block(DSRAM[0]) used for FW dump */ - fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT; - writel(reg & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0); - + /* clear reset */ + sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_RST, 0); /* disable DMA finish function for SSP0 & SSP1 */ sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1, @@ -384,12 +418,6 @@ static int hsw_set_dsp_D0(struct sst_dsp *sst) sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY | SST_IMRD_SSP0 | SST_IMRD_DMAC), 0x0); - /* clear IPC registers */ - sst_dsp_shim_write(sst, SST_IPCX, 0x0); - sst_dsp_shim_write(sst, SST_IPCD, 0x0); - sst_dsp_shim_write(sst, 0x80, 0x6); - sst_dsp_shim_write(sst, 0xe0, 0x300a); - return 0; } @@ -415,11 +443,6 @@ static void hsw_sleep(struct sst_dsp *sst) { dev_dbg(sst->dev, "HSW_PM dsp runtime suspend\n"); - /* put DSP into reset and stall */ - sst_dsp_shim_update_bits(sst, SST_CSR, - SST_CSR_24MHZ_LPCS | SST_CSR_RST | SST_CSR_STALL, - SST_CSR_RST | SST_CSR_STALL | SST_CSR_24MHZ_LPCS); - hsw_set_dsp_D3(sst); dev_dbg(sst->dev, "HSW_PM dsp runtime suspend exit\n"); } -- 2.17.1

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[PATCH alsa-lib] conf: Add /usr/etc to the default search paths
by Takashi Iwai 19 Jun '20

19 Jun '20

There's been some recent action to move the distribution-default setup from /etc to /usr/etc, and we should follow that, too. This patch adds /usr/etc/alsa.conf.d and /usr/etc/alsa.conf to the default search paths. Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- src/conf/alsa.conf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/conf/alsa.conf b/src/conf/alsa.conf index 18427ec6c4c6..aea1fe24f73c 100644 --- a/src/conf/alsa.conf +++ b/src/conf/alsa.conf @@ -8,6 +8,8 @@ { func load files [ + "/usr/etc/alsa/conf.d" + "/usr/etc/asound.conf" "/etc/alsa/conf.d" "/etc/asound.conf" "~/.asoundrc" -- 2.16.4

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[PATCH AUTOSEL 4.19 047/172] ASoC: meson: add missing free_irq() in error path
by Sasha Levin 19 Jun '20

19 Jun '20

From: "Pavel Machek (CIP)" <pavel(a)denx.de> [ Upstream commit 3b8a299a58b2afce464ae11324b59dcf0f1d10a7 ] free_irq() is missing in case of error, fix that. Signed-off-by: Pavel Machek (CIP) <pavel(a)denx.de> Reviewed-by: Jerome Brunet <jbrunet(a)baylibre.com> Link: https://lore.kernel.org/r/20200606153103.GA17905@amd Signed-off-by: Mark Brown <broonie(a)kernel.org> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- sound/soc/meson/axg-fifo.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c index 0e4f65e654c4..b229c182b7c3 100644 --- a/sound/soc/meson/axg-fifo.c +++ b/sound/soc/meson/axg-fifo.c @@ -209,7 +209,7 @@ static int axg_fifo_pcm_open(struct snd_pcm_substream *ss) /* Enable pclk to access registers and clock the fifo ip */ ret = clk_prepare_enable(fifo->pclk); if (ret) - return ret; + goto free_irq; /* Setup status2 so it reports the memory pointer */ regmap_update_bits(fifo->map, FIFO_CTRL1, @@ -229,8 +229,14 @@ static int axg_fifo_pcm_open(struct snd_pcm_substream *ss) /* Take memory arbitror out of reset */ ret = reset_control_deassert(fifo->arb); if (ret) - clk_disable_unprepare(fifo->pclk); + goto free_clk; + + return 0; +free_clk: + clk_disable_unprepare(fifo->pclk); +free_irq: + free_irq(fifo->irq, ss); return ret; } -- 2.25.1

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