Alsa-devel May 2019

alsa-devel@alsa-project.org

136 participants
372 discussions

[alsa-devel] [PATCH v1 0/6] VAG power control improvement for sgtl5000 codec
by Oleksandr Suvorov 24 Jun '19

24 Jun '19

VAG power control is improved to fit the manual. This fixes as minimum one bug: if customer muxes Headphone to Line-In right after boot w/o playing any sound, the VAG power remains off that leads to poor sound quality from line-in. I.e. after boot: - Connect sound source to Line-In jack; - Connect headphone to HP jack; - Run following commands: $ amixer set 'Headphone' 80% $ amixer set 'Headphone Mux' LINE_IN Also this series includes fixes of non-important bugs in sgtl5000 codec driver. Oleksandr Suvorov (6): ASoC: sgtl5000: Fix definition of VAG Ramp Control ASoC: sgtl5000: add ADC mute control ASoC: sgtl5000: Fix of unmute outputs on probe ASoC: sgtl5000: Fix charge pump source assignment ASoC: Define a set of DAPM pre/post-up events ASoC: sgtl5000: Improve VAG power and mute control include/sound/soc-dapm.h | 2 + sound/soc/codecs/sgtl5000.c | 250 ++++++++++++++++++++++++++++++------ sound/soc/codecs/sgtl5000.h | 2 +- 3 files changed, 212 insertions(+), 42 deletions(-) -- 2.20.1 -- Ciklum refers to one or more of Ciklum Group Holdings LTD. and its subsidiaries and affiliates each of which is a legally separate entity. Ciklum LLC is a limited liability company registered in Ukraine under EDRPOU code 31902643, with its registered address at 12 Amosova St., 03680, Kyiv, Ukraine. The contents of this e-mail (including any attachments) are confidential and may be legally privileged. If you are not the intended recipient of this e-mail, please notify the sender immediately and then delete it (including any attachments) from all your systems. Any unauthorised use, reproduction, distribution, disclosure and/or modification of this message and/or its contents are strictly prohibited. We cannot guarantee that this e-mail is secure or error-free. Ciklum cannot be held liable for any loss or damage caused by software viruses or resulting from any use of or reliance on this email by anyone, other than the intended addressee to the extent agreed in a contract for the matter to which this email relates (if any). Messages sent to and from Ciklum may be monitored; by replying to this e-mail you give your consent to such monitoring. Notice: we do not accept service by e-mail of court proceedings, other processes or formal notices of any kind without specific prior written agreement. This email does not constitute a binding offer or acceptance for Ciklum unless so set forth in a separate document.

2 14

[alsa-devel] [RFC PATCH] ASoC: Intel: use common helpers to detect CPUs
by Pierre-Louis Bossart 19 Jun '19

19 Jun '19

We have duplicated code in multiple locations (atom, machine drivers, SOF) to detect Baytrail, Cherrytrail and other SOCs. This is not very elegant, and introduces dependencies on CONFIG_X86 that prevent COMPILE_TEST from working. Add common helpers to provide same functionality in a cleaner way. This will also help support the DMI-based quirks being introduced to handle SOF/SST autodetection. FIXME: 0. does this fix COMPILE_TEST issues reported by Randy? 1. should the include file moved to include/sound? this would be handy for the SOF/SST mutual exclusion? 2. is there a better way to do this for all Intel chips or do we keep this in sound/? Andy? Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart(a)linux.intel.com> --- sound/soc/intel/atom/sst/sst_acpi.c | 65 +--------- sound/soc/intel/boards/bxt_da7219_max98357a.c | 11 +- sound/soc/intel/boards/bytcht_es8316.c | 12 +- sound/soc/intel/boards/bytcr_rt5640.c | 16 +-- sound/soc/intel/boards/bytcr_rt5651.c | 17 +-- sound/soc/intel/boards/cht_bsw_rt5645.c | 16 +-- sound/soc/intel/boards/sof_rt5682.c | 11 +- sound/soc/intel/common/soc-intel-quirks.h | 115 ++++++++++++++++++ sound/soc/sof/sof-acpi-dev.c | 57 +-------- 9 files changed, 135 insertions(+), 185 deletions(-) create mode 100644 sound/soc/intel/common/soc-intel-quirks.h diff --git a/sound/soc/intel/atom/sst/sst_acpi.c b/sound/soc/intel/atom/sst/sst_acpi.c index ae17ce4677a5..06c4a2da900c 100644 --- a/sound/soc/intel/atom/sst/sst_acpi.c +++ b/sound/soc/intel/atom/sst/sst_acpi.c @@ -38,12 +38,11 @@ #include <acpi/platform/aclinux.h> #include <acpi/actypes.h> #include <acpi/acpi_bus.h> -#include <asm/cpu_device_id.h> -#include <asm/iosf_mbi.h> #include <sound/soc-acpi.h> #include <sound/soc-acpi-intel-match.h> #include "../sst-mfld-platform.h" #include "../../common/sst-dsp.h" +#include "../../common/soc-intel-quirks.h" #include "sst.h" /* LPE viewpoint addresses */ @@ -243,64 +242,6 @@ static int sst_platform_get_resources(struct intel_sst_drv *ctx) return 0; } -static int is_byt(void) -{ - bool status = false; - static const struct x86_cpu_id cpu_ids[] = { - { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */ - {} - }; - if (x86_match_cpu(cpu_ids)) - status = true; - return status; -} - -static bool is_byt_cr(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - int status = 0; - - if (!is_byt()) - return false; - - if (iosf_mbi_available()) { - u32 bios_status; - status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */ - MBI_REG_READ, /* 0x10 */ - 0x006, /* BIOS_CONFIG */ - &bios_status); - - if (status) { - dev_err(dev, "could not read PUNIT BIOS_CONFIG\n"); - } else { - /* bits 26:27 mirror PMIC options */ - bios_status = (bios_status >> 26) & 3; - - if (bios_status == 1 || bios_status == 3) { - dev_info(dev, "Detected Baytrail-CR platform\n"); - return true; - } - - dev_info(dev, "BYT-CR not detected\n"); - } - } else { - dev_info(dev, "IOSF_MBI not available, no BYT-CR detection\n"); - } - - if (platform_get_resource(pdev, IORESOURCE_IRQ, 5) == NULL) { - /* - * Some devices detected as BYT-T have only a single IRQ listed, - * causing platform_get_irq with index 5 to return -ENXIO. - * The correct IRQ in this case is at index 0, as on BYT-CR. - */ - dev_info(dev, "Falling back to Baytrail-CR platform\n"); - return true; - } - - return false; -} - - static int sst_acpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -325,7 +266,7 @@ static int sst_acpi_probe(struct platform_device *pdev) return -ENODEV; } - if (is_byt()) + if (soc_intel_is_byt()) mach->pdata = &byt_rvp_platform_data; else mach->pdata = &chv_platform_data; @@ -343,7 +284,7 @@ static int sst_acpi_probe(struct platform_device *pdev) if (ret < 0) return ret; - if (is_byt_cr(pdev)) { + if (soc_intel_is_byt_cr(pdev)) { /* override resource info */ byt_rvp_platform_data.res_info = &bytcr_res_info; } diff --git a/sound/soc/intel/boards/bxt_da7219_max98357a.c b/sound/soc/intel/boards/bxt_da7219_max98357a.c index d8c7d64bb1d7..d476c55f2efe 100644 --- a/sound/soc/intel/boards/bxt_da7219_max98357a.c +++ b/sound/soc/intel/boards/bxt_da7219_max98357a.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include <asm/cpu_device_id.h> #include <linux/input.h> #include <linux/module.h> #include <linux/platform_device.h> @@ -29,6 +28,7 @@ #include "../../codecs/hdac_hdmi.h" #include "../../codecs/da7219.h" #include "../../codecs/da7219-aad.h" +#include "../common/soc-intel-quirks.h" #define BXT_DIALOG_CODEC_DAI "da7219-hifi" #define BXT_MAXIM_CODEC_DAI "HiFi" @@ -579,11 +579,6 @@ static struct snd_soc_dai_link broxton_dais[] = { }, }; -static const struct x86_cpu_id glk_ids[] = { - { X86_VENDOR_INTEL, 6, 0x7A }, /* Geminilake CPU_ID */ - {} -}; - #define NAME_SIZE 32 static int bxt_card_late_probe(struct snd_soc_card *card) { @@ -593,7 +588,7 @@ static int bxt_card_late_probe(struct snd_soc_card *card) int err, i = 0; char jack_name[NAME_SIZE]; - if (x86_match_cpu(glk_ids)) + if (soc_intel_is_glk()) snd_soc_dapm_add_routes(&card->dapm, gemini_map, ARRAY_SIZE(gemini_map)); else @@ -656,7 +651,7 @@ static int broxton_audio_probe(struct platform_device *pdev) broxton_audio_card.dev = &pdev->dev; snd_soc_card_set_drvdata(&broxton_audio_card, ctx); - if (x86_match_cpu(glk_ids)) { + if (soc_intel_is_glk()) { unsigned int i; broxton_audio_card.name = "glkda7219max"; diff --git a/sound/soc/intel/boards/bytcht_es8316.c b/sound/soc/intel/boards/bytcht_es8316.c index e8c585ffd04d..d08715ac3945 100644 --- a/sound/soc/intel/boards/bytcht_es8316.c +++ b/sound/soc/intel/boards/bytcht_es8316.c @@ -30,8 +30,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> -#include <asm/cpu_device_id.h> -#include <asm/intel-family.h> #include <asm/platform_sst_audio.h> #include <sound/jack.h> #include <sound/pcm.h> @@ -40,6 +38,7 @@ #include <sound/soc-acpi.h> #include "../atom/sst-atom-controls.h" #include "../common/sst-dsp.h" +#include "../common/soc-intel-quirks.h" /* jd-inv + terminating entry */ #define MAX_NO_PROPS 2 @@ -430,11 +429,6 @@ static struct snd_soc_card byt_cht_es8316_card = { .resume_post = byt_cht_es8316_resume, }; -static const struct x86_cpu_id baytrail_cpu_ids[] = { - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT }, /* Valleyview */ - {} -}; - static const struct acpi_gpio_params first_gpio = { 0, 0, false }; static const struct acpi_gpio_mapping byt_cht_es8316_gpios[] = { @@ -506,8 +500,8 @@ static int snd_byt_cht_es8316_mc_probe(struct platform_device *pdev) dmi_id = dmi_first_match(byt_cht_es8316_quirk_table); if (dmi_id) { quirk = (unsigned long)dmi_id->driver_data; - } else if (x86_match_cpu(baytrail_cpu_ids) && - mach->mach_params.acpi_ipc_irq_index == 0) { + } else if (soc_intel_is_byt() && + mach->mach_params.acpi_ipc_irq_index == 0) { /* On BYTCR default to SSP0, internal-mic-in2-map, mono-spk */ quirk = BYT_CHT_ES8316_SSP0 | BYT_CHT_ES8316_INTMIC_IN2_MAP | BYT_CHT_ES8316_MONO_SPEAKER; diff --git a/sound/soc/intel/boards/bytcr_rt5640.c b/sound/soc/intel/boards/bytcr_rt5640.c index dc22df9a99fb..7aae7b78efba 100644 --- a/sound/soc/intel/boards/bytcr_rt5640.c +++ b/sound/soc/intel/boards/bytcr_rt5640.c @@ -28,7 +28,6 @@ #include <linux/dmi.h> #include <linux/input.h> #include <linux/slab.h> -#include <asm/cpu_device_id.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/soc.h> @@ -38,6 +37,7 @@ #include "../../codecs/rt5640.h" #include "../atom/sst-atom-controls.h" #include "../common/sst-dsp.h" +#include "../common/soc-intel-quirks.h" enum { BYT_RT5640_DMIC1_MAP, @@ -1130,18 +1130,6 @@ static struct snd_soc_card byt_rt5640_card = { .resume_post = byt_rt5640_resume, }; -static bool is_valleyview(void) -{ - static const struct x86_cpu_id cpu_ids[] = { - { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */ - {} - }; - - if (!x86_match_cpu(cpu_ids)) - return false; - return true; -} - struct acpi_chan_package { /* ACPICA seems to require 64 bit integers */ u64 aif_value; /* 1: AIF1, 2: AIF2 */ u64 mclock_value; /* usually 25MHz (0x17d7940), ignored */ @@ -1190,7 +1178,7 @@ static int snd_byt_rt5640_mc_probe(struct platform_device *pdev) * swap SSP0 if bytcr is detected * (will be overridden if DMI quirk is detected) */ - if (is_valleyview()) { + if (soc_intel_is_byt()) { if (mach->mach_params.acpi_ipc_irq_index == 0) is_bytcr = true; } diff --git a/sound/soc/intel/boards/bytcr_rt5651.c b/sound/soc/intel/boards/bytcr_rt5651.c index ca657c3e5726..6df6435ea394 100644 --- a/sound/soc/intel/boards/bytcr_rt5651.c +++ b/sound/soc/intel/boards/bytcr_rt5651.c @@ -30,8 +30,6 @@ #include <linux/gpio/consumer.h> #include <linux/gpio/machine.h> #include <linux/slab.h> -#include <asm/cpu_device_id.h> -#include <asm/intel-family.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/soc.h> @@ -39,6 +37,7 @@ #include <sound/soc-acpi.h> #include "../../codecs/rt5651.h" #include "../atom/sst-atom-controls.h" +#include "../common/soc-intel-quirks.h" enum { BYT_RT5651_DMIC_MAP, @@ -852,16 +851,6 @@ static struct snd_soc_card byt_rt5651_card = { .resume_post = byt_rt5651_resume, }; -static const struct x86_cpu_id baytrail_cpu_ids[] = { - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT }, /* Valleyview */ - {} -}; - -static const struct x86_cpu_id cherrytrail_cpu_ids[] = { - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, /* Braswell */ - {} -}; - static const struct acpi_gpio_params ext_amp_enable_gpios = { 0, 0, false }; static const struct acpi_gpio_mapping cht_rt5651_gpios[] = { @@ -932,7 +921,7 @@ static int snd_byt_rt5651_mc_probe(struct platform_device *pdev) * swap SSP0 if bytcr is detected * (will be overridden if DMI quirk is detected) */ - if (x86_match_cpu(baytrail_cpu_ids)) { + if (soc_intel_is_byt()) { if (mach->mach_params.acpi_ipc_irq_index == 0) is_bytcr = true; } @@ -1001,7 +990,7 @@ static int snd_byt_rt5651_mc_probe(struct platform_device *pdev) } /* Cherry Trail devices use an external amplifier enable gpio */ - if (x86_match_cpu(cherrytrail_cpu_ids) && !byt_rt5651_gpios) + if (soc_intel_is_cht() && !byt_rt5651_gpios) byt_rt5651_gpios = cht_rt5651_gpios; if (byt_rt5651_gpios) { diff --git a/sound/soc/intel/boards/cht_bsw_rt5645.c b/sound/soc/intel/boards/cht_bsw_rt5645.c index 32dbeaf1ab94..de5fe58ae3b4 100644 --- a/sound/soc/intel/boards/cht_bsw_rt5645.c +++ b/sound/soc/intel/boards/cht_bsw_rt5645.c @@ -26,7 +26,6 @@ #include <linux/clk.h> #include <linux/dmi.h> #include <linux/slab.h> -#include <asm/cpu_device_id.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/soc.h> @@ -34,6 +33,7 @@ #include <sound/soc-acpi.h> #include "../../codecs/rt5645.h" #include "../atom/sst-atom-controls.h" +#include "../common/soc-intel-quirks.h" #define CHT_PLAT_CLK_3_HZ 19200000 #define CHT_CODEC_DAI1 "rt5645-aif1" @@ -509,18 +509,6 @@ static char cht_rt5645_codec_name[SND_ACPI_I2C_ID_LEN]; static char cht_rt5645_codec_aif_name[12]; /* = "rt5645-aif[1|2]" */ static char cht_rt5645_cpu_dai_name[10]; /* = "ssp[0|2]-port" */ -static bool is_valleyview(void) -{ - static const struct x86_cpu_id cpu_ids[] = { - { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */ - {} - }; - - if (!x86_match_cpu(cpu_ids)) - return false; - return true; -} - struct acpi_chan_package { /* ACPICA seems to require 64 bit integers */ u64 aif_value; /* 1: AIF1, 2: AIF2 */ u64 mclock_value; /* usually 25MHz (0x17d7940), ignored */ @@ -585,7 +573,7 @@ static int snd_cht_mc_probe(struct platform_device *pdev) * swap SSP0 if bytcr is detected * (will be overridden if DMI quirk is detected) */ - if (is_valleyview()) { + if (soc_intel_is_byt()) { if (mach->mach_params.acpi_ipc_irq_index == 0) is_bytcr = true; } diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c index e441dc979966..355fd9730a44 100644 --- a/sound/soc/intel/boards/sof_rt5682.c +++ b/sound/soc/intel/boards/sof_rt5682.c @@ -10,8 +10,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/dmi.h> -#include <asm/cpu_device_id.h> -#include <asm/intel-family.h> #include <sound/core.h> #include <sound/jack.h> #include <sound/pcm.h> @@ -21,6 +19,7 @@ #include <sound/soc-acpi.h> #include "../../codecs/rt5682.h" #include "../../codecs/hdac_hdmi.h" +#include "../common/soc-intel-quirks.h" #define NAME_SIZE 32 @@ -304,12 +303,6 @@ static struct snd_soc_card sof_audio_card_rt5682 = { .late_probe = sof_card_late_probe, }; -static const struct x86_cpu_id legacy_cpi_ids[] = { - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT }, /* Baytrail */ - { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, /* Cherrytrail */ - {} -}; - static struct snd_soc_dai_link_component rt5682_component[] = { { .name = "i2c-10EC5682:00", @@ -498,7 +491,7 @@ static int sof_audio_probe(struct platform_device *pdev) if (!ctx) return -ENOMEM; - if (x86_match_cpu(legacy_cpi_ids)) { + if (soc_intel_is_byt() || soc_intel_is_cht()) { is_legacy_cpu = 1; dmic_num = 0; hdmi_num = 0; diff --git a/sound/soc/intel/common/soc-intel-quirks.h b/sound/soc/intel/common/soc-intel-quirks.h new file mode 100644 index 000000000000..4718fd3cf636 --- /dev/null +++ b/sound/soc/intel/common/soc-intel-quirks.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * soc-intel-quirks.h - prototypes for quirk autodetection + * + * Copyright (c) 2019, Intel Corporation. + * + */ + +#ifndef _SND_SOC_INTEL_QUIRKS_H +#define _SND_SOC_INTEL_QUIRKS_H + +#if IS_ENABLED(CONFIG_X86) + +#include <asm/cpu_device_id.h> +#include <asm/intel-family.h> +#include <asm/iosf_mbi.h> + +#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } + +#define SOC_INTEL_IS_CPU(soc, type) \ +static inline bool soc_intel_is_##soc(void) \ +{ \ + static const struct x86_cpu_id soc##_cpu_ids[] = { \ + ICPU(type), \ + {} \ + }; \ + const struct x86_cpu_id *id; \ + \ + id = x86_match_cpu(soc##_cpu_ids); \ + if (id) \ + return true; \ + return false; \ +} + +SOC_INTEL_IS_CPU(byt, INTEL_FAM6_ATOM_SILVERMONT); +SOC_INTEL_IS_CPU(cht, INTEL_FAM6_ATOM_AIRMONT); +SOC_INTEL_IS_CPU(apl, INTEL_FAM6_ATOM_GOLDMONT); +SOC_INTEL_IS_CPU(glk, INTEL_FAM6_ATOM_GOLDMONT_PLUS); + +static inline bool soc_intel_is_byt_cr(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int status = 0; + + if (!soc_intel_is_byt()) + return false; + + if (iosf_mbi_available()) { + u32 bios_status; + + status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */ + MBI_REG_READ, /* 0x10 */ + 0x006, /* BIOS_CONFIG */ + &bios_status); + + if (status) { + dev_err(dev, "could not read PUNIT BIOS_CONFIG\n"); + } else { + /* bits 26:27 mirror PMIC options */ + bios_status = (bios_status >> 26) & 3; + + if (bios_status == 1 || bios_status == 3) { + dev_info(dev, "Detected Baytrail-CR platform\n"); + return true; + } + + dev_info(dev, "BYT-CR not detected\n"); + } + } else { + dev_info(dev, "IOSF_MBI not available, no BYT-CR detection\n"); + } + + if (!platform_get_resource(pdev, IORESOURCE_IRQ, 5)) { + /* + * Some devices detected as BYT-T have only a single IRQ listed, + * causing platform_get_irq with index 5 to return -ENXIO. + * The correct IRQ in this case is at index 0, as on BYT-CR. + */ + dev_info(dev, "Falling back to Baytrail-CR platform\n"); + return true; + } + + return false; +} + +#else + +static inline bool soc_intel_is_byt_cr(struct platform_device *pdev) +{ + return false; +} + +static inline bool soc_intel_is_byt(void) +{ + return false; +} + +static inline bool soc_intel_is_cht(void) +{ + return false; +} + +static inline bool soc_intel_is_apl(void) +{ + return false; +} + +static inline bool soc_intel_is_glk(void) +{ + return false; +} + +#endif + + #endif /* _SND_SOC_INTEL_QUIRKS_H */ diff --git a/sound/soc/sof/sof-acpi-dev.c b/sound/soc/sof/sof-acpi-dev.c index 38062dd00dd2..93a8e15bbd2c 100644 --- a/sound/soc/sof/sof-acpi-dev.c +++ b/sound/soc/sof/sof-acpi-dev.c @@ -15,10 +15,7 @@ #include <sound/soc-acpi.h> #include <sound/soc-acpi-intel-match.h> #include <sound/sof.h> -#ifdef CONFIG_X86 -#include <asm/iosf_mbi.h> -#endif - +#include "../intel/common/soc-intel-quirks.h" #include "ops.h" /* platform specific devices */ @@ -105,56 +102,6 @@ static const struct sof_dev_desc sof_acpi_baytrail_desc = { .arch_ops = &sof_xtensa_arch_ops }; -#ifdef CONFIG_X86 /* TODO: move this to common helper */ - -static bool is_byt_cr(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - int status; - - if (iosf_mbi_available()) { - u32 bios_status; - status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */ - MBI_REG_READ, /* 0x10 */ - 0x006, /* BIOS_CONFIG */ - &bios_status); - - if (status) { - dev_err(dev, "could not read PUNIT BIOS_CONFIG\n"); - } else { - /* bits 26:27 mirror PMIC options */ - bios_status = (bios_status >> 26) & 3; - - if (bios_status == 1 || bios_status == 3) { - dev_info(dev, "Detected Baytrail-CR platform\n"); - return true; - } - - dev_info(dev, "BYT-CR not detected\n"); - } - } else { - dev_info(dev, "IOSF_MBI not available, no BYT-CR detection\n"); - } - - if (platform_get_resource(pdev, IORESOURCE_IRQ, 5) == NULL) { - /* - * Some devices detected as BYT-T have only a single IRQ listed, - * causing platform_get_irq with index 5 to return -ENXIO. - * The correct IRQ in this case is at index 0, as on BYT-CR. - */ - dev_info(dev, "Falling back to Baytrail-CR platform\n"); - return true; - } - - return false; -} -#else -static int is_byt_cr(struct platform_device *pdev) -{ - return 0; -} -#endif - static const struct sof_dev_desc sof_acpi_cherrytrail_desc = { .machines = snd_soc_acpi_intel_cherrytrail_machines, .resindex_lpe_base = 0, @@ -209,7 +156,7 @@ static int sof_acpi_probe(struct platform_device *pdev) return -ENODEV; #if IS_ENABLED(CONFIG_SND_SOC_SOF_BAYTRAIL) - if (desc == &sof_acpi_baytrail_desc && is_byt_cr(pdev)) + if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev)) desc = &sof_acpi_baytrailcr_desc; #endif -- 2.20.1

6 9

[alsa-devel] [RFC PATCH 0/6] ALSA/HDA: abort probe when DMICs are detected
by Pierre-Louis Bossart 18 Jun '19

18 Jun '19

This is the second take on same problem of detecting when the HDaudio legacy driver can be used and when the SST or SOF drivers are required. The previous attempt based on a the PCI Class information was a resounding failure and broke audio on Linus' laptop, so we need additional information to avoid enabling a DSP-based driver without a good reason to do so. This patchset suggests the use of the NHLT information which *in theory* exposes DMIC endpoints. The legacy HDaudio driver cannot handle DMICs and will not provide any capture capabilities. Since it's typically the first one to probe due to the Makefile order, aborting the probe will let the PCI subsystem look for the next driver which hopefully will support this capability. I tested this patch on 5 devices (SKL, KBL, APL, GLK, WHL), three without DMICs and two with, and the detection seems to work as planned. I would appreciate it if HDaudio integrators and folks at Google/Canonical/Endless can give this a try. As usual I expect that we will have to use quirks and work-arounds, but it'd be a better idea than a build-time mutual exclusion. We could also make this optional (Kconfig and/or module parameters) if people prefer to muck with blacklists. Feedback and comments welcome! Pierre-Louis Bossart (6): ASoC: Intel: boards: remove unnecessary inclusion of skl.h ASoC: Intel: Skylake: move NHLT header to common directory ASoC: Intel: common: move parts of NHLT code to new module ASoC: Intel: Skylake: use common NHLT module ALSA / hda: stop probe if DMICS are detected on Skylake+ platforms [HACK] ASoC: Intel: NHLT: handle VENDOR_DEFINED DMIC geometry sound/pci/hda/Kconfig | 1 + sound/pci/hda/hda_intel.c | 30 ++++++ sound/soc/intel/Kconfig | 3 + sound/soc/intel/boards/glk_rt5682_max98357a.c | 1 - sound/soc/intel/boards/kbl_da7219_max98357a.c | 1 - sound/soc/intel/boards/kbl_da7219_max98927.c | 1 - sound/soc/intel/boards/skl_hda_dsp_common.c | 1 - sound/soc/intel/common/Makefile | 3 + sound/soc/intel/common/intel-nhlt.c | 101 ++++++++++++++++++ .../skl-nhlt.h => common/intel-nhlt.h} | 28 +++++ sound/soc/intel/skylake/skl-nhlt.c | 91 +--------------- sound/soc/intel/skylake/skl-ssp-clk.c | 1 + sound/soc/intel/skylake/skl-topology.c | 1 + sound/soc/intel/skylake/skl.c | 11 +- sound/soc/intel/skylake/skl.h | 4 - 15 files changed, 176 insertions(+), 102 deletions(-) create mode 100644 sound/soc/intel/common/intel-nhlt.c rename sound/soc/intel/{skylake/skl-nhlt.h => common/intel-nhlt.h} (83%) -- 2.20.1

4 26

[alsa-devel] [PATCH v2 00/12] ASoC: SOF: stability fixes
by Pierre-Louis Bossart 17 Jun '19

17 Jun '19

No new functionality here but fixes to the IPC, memory allocation, workqueues, control, runtime_pm and HDaudio support. These issues were identified during the integration/productization of new platforms. I added a 'Fixes' tag to make sure backports/stable can pick up these patches, in case it's too late for them to land in 5.2 The next batch for SOF will be a set of new capabilities for trace, IPC test, Hdaudio support, they will be submitted after additional tests and once these fixes are reviewed/merged. Thanks! Changes since v1: Feedback from Takashi: use spin_lock_irq instead of spin_lock_irq_save Added Takashi's Reviewed-by tag Amadeusz Sławiński (1): ALSA: hdac: fix memory release for SST and SOF drivers Guennadi Liakhovetski (1): ASoC: SOF: ipc: fix a race, leading to IPC timeouts Keyon Jie (1): ASoC: SOF: control: correct the copy size for bytes kcontrol put Libin Yang (2): ASoC: SOF: pcm: clear hw_params_upon_resume flag correctly ASoC: SOF: Intel: hda-codec: fix memory allocation Pierre-Louis Bossart (2): ASoC: SOF: core: fix error handling with the probe workqueue ASoC: SOF: pcm: remove warning - initialize workqueue on open Ranjani Sridharan (3): ASoC: SOF: core: remove DSP after unregistering machine driver ASoC: SOF: core: remove snd_soc_unregister_component in case of error ASoC: SOF: pcm: remove runtime PM calls during pcm open/close Zhu Yingjiang (2): ASoC: SOF: Intel: hda: fix the hda init chip ASoC: SOF: Intel: hda: use the defined ppcap functions sound/hda/ext/hdac_ext_bus.c | 1 - sound/soc/sof/control.c | 9 +-- sound/soc/sof/core.c | 29 +++++++-- sound/soc/sof/intel/bdw.c | 10 +-- sound/soc/sof/intel/byt.c | 11 ++-- sound/soc/sof/intel/cnl.c | 5 ++ sound/soc/sof/intel/hda-codec.c | 6 +- sound/soc/sof/intel/hda-ctrl.c | 102 +++++++++++++++++++++++++++--- sound/soc/sof/intel/hda-ipc.c | 18 +++++- sound/soc/sof/intel/hda.c | 109 +++++++------------------------- sound/soc/sof/ipc.c | 13 ---- sound/soc/sof/pcm.c | 37 ++--------- 12 files changed, 184 insertions(+), 166 deletions(-) -- 2.20.1

5 29

[alsa-devel] [PATCH 0/3] Add mclk0 clock source for SAI
by Daniel Baluta 14 Jun '19

14 Jun '19

This patch series brings together patches [1] and [2] which introduce mclk0 clock source via DT. mclk0..3 are the four clock sources options of SAI's clock MUX. mclk0 option selects: - Bus Clock on i.MX8 - MCLK1 on i.MX6/7 Finally we also update the DT binding information for SAI clocks. In [1] and [2] Nicolin had a very good point on the fact that mclk0 might not be needed in the DT. Anyhow, there are two reasons for which I think mlck0 should be added to DT: 1) SAI clock source select MUX is really part of the hardware 2) flexibility! We let DT tell us which is the option for MUX option 0. [1] lkml.org/lkml/2019/4/20/141 [2] lkml.org/lkml/2019/4/20/56 Daniel Baluta (2): dt-bindings: sound: Clarify the usage of clocks in SAI ASoC: fsl_sai: Read SAI clock source 0 from DT Shengjiu Wang (1): ARM: dts: imx: Add mclk0 clock for SAI Documentation/devicetree/bindings/sound/fsl-sai.txt | 5 +++-- arch/arm/boot/dts/imx6sx.dtsi | 6 ++++-- arch/arm/boot/dts/imx6ul.dtsi | 9 ++++++--- arch/arm/boot/dts/imx7s.dtsi | 9 ++++++--- sound/soc/fsl/fsl_sai.c | 3 +-- 5 files changed, 20 insertions(+), 12 deletions(-) -- 2.17.1

3 7

[alsa-devel] next/master boot bisection: next-20190528 on sun8i-h3-libretech-all-h3-cc
by kernelci.org bot 07 Jun '19

07 Jun '19

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This automated bisection report was sent to you on the basis * * that you may be involved with the breaking commit it has * * found. No manual investigation has been done to verify it, * * and the root cause of the problem may be somewhere else. * * Hope this helps! * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * next/master boot bisection: next-20190528 on sun8i-h3-libretech-all-h3-cc Summary: Start: 531b0a360899 Add linux-next specific files for 20190528 Details: https://kernelci.org/boot/id/5cece0fd59b5144bc47a362b Plain log: https://storage.kernelci.org//next/master/next-20190528/arm/sunxi_defconfig… HTML log: https://storage.kernelci.org//next/master/next-20190528/arm/sunxi_defconfig… Result: 34ac3c3eb8f0 ASoC: core: lock client_mutex while removing link components Checks: revert: PASS verify: PASS Parameters: Tree: next URL: git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git Branch: master Target: sun8i-h3-libretech-all-h3-cc CPU arch: arm Lab: lab-baylibre Compiler: gcc-8 Config: sunxi_defconfig Test suite: boot Breaking commit found: ------------------------------------------------------------------------------- commit 34ac3c3eb8f0c07252ceddf0a22dd240e5c91ccb Author: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> Date: Thu May 23 10:12:01 2019 -0700 ASoC: core: lock client_mutex while removing link components Removing link components results in topology unloading. So, acquire the client_mutex before removing components in soc_remove_link_components. This will prevent the lockdep warning seen when dai links are removed during topology removal. Signed-off-by: Ranjani Sridharan <ranjani.sridharan(a)linux.intel.com> Signed-off-by: Mark Brown <broonie(a)kernel.org> diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index 2403bec2fccf..7c9415987ac7 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -1005,12 +1005,14 @@ static void soc_remove_link_components(struct snd_soc_card *card, struct snd_soc_component *component; struct snd_soc_rtdcom_list *rtdcom; + mutex_lock(&client_mutex); for_each_rtdcom(rtd, rtdcom) { component = rtdcom->component; if (component->driver->remove_order == order) soc_remove_component(component); } + mutex_unlock(&client_mutex); } static void soc_remove_dai_links(struct snd_soc_card *card) ------------------------------------------------------------------------------- Git bisection log: ------------------------------------------------------------------------------- git bisect start # good: [cd6c84d8f0cdc911df435bb075ba22ce3c605b07] Linux 5.2-rc2 git bisect good cd6c84d8f0cdc911df435bb075ba22ce3c605b07 # bad: [531b0a360899269bd99a38ba9852a8ba46852bcd] Add linux-next specific files for 20190528 git bisect bad 531b0a360899269bd99a38ba9852a8ba46852bcd # bad: [0b61d4c3b7d7938ef0014778c328e3f65c0d6d57] Merge remote-tracking branch 'crypto/master' git bisect bad 0b61d4c3b7d7938ef0014778c328e3f65c0d6d57 # bad: [6179e21b065dc0f592cd3d9d3676bd64d4278025] Merge remote-tracking branch 'xtensa/xtensa-for-next' git bisect bad 6179e21b065dc0f592cd3d9d3676bd64d4278025 # bad: [3e085f66fe7e93575f2a583a3d434415cef2d860] Merge remote-tracking branch 'amlogic/for-next' git bisect bad 3e085f66fe7e93575f2a583a3d434415cef2d860 # bad: [b9afa223a3420432bc483d2b43429c88c6a5d0e0] Merge remote-tracking branch 'staging.current/staging-linus' git bisect bad b9afa223a3420432bc483d2b43429c88c6a5d0e0 # good: [fc6557648e19dbd207dc815c6e09fc6452f01e63] Merge remote-tracking branch 'bpf/master' git bisect good fc6557648e19dbd207dc815c6e09fc6452f01e63 # bad: [6c3f2a0e0f236f31b47d63ab7d3f4ec889821d0d] Merge remote-tracking branch 'spi-fixes/for-linus' git bisect bad 6c3f2a0e0f236f31b47d63ab7d3f4ec889821d0d # bad: [20a5f9c8649d74407aa657ce5b76cf8b0bbb17e3] Merge branch 'asoc-5.2' into asoc-linus git bisect bad 20a5f9c8649d74407aa657ce5b76cf8b0bbb17e3 # good: [ad6eecbfc01c987e0253371f274c3872042e4350] ASoC: cs42xx8: Add regcache mask dirty git bisect good ad6eecbfc01c987e0253371f274c3872042e4350 # good: [069d037aea98ffa64c26d4b1dc958fb8f39f5c2b] ASoC: simple-card: Fix configuration of DAI format git bisect good 069d037aea98ffa64c26d4b1dc958fb8f39f5c2b # good: [df9366131a452296d040a7a496d93108f1fc240c] ASoC: Intel: sof-rt5682: fix AMP quirk support git bisect good df9366131a452296d040a7a496d93108f1fc240c # bad: [34ac3c3eb8f0c07252ceddf0a22dd240e5c91ccb] ASoC: core: lock client_mutex while removing link components git bisect bad 34ac3c3eb8f0c07252ceddf0a22dd240e5c91ccb # good: [4819d06292c9b57eabdd6d1603e49a27baf183be] ASoC: simple-card: Restore original configuration of DAI format git bisect good 4819d06292c9b57eabdd6d1603e49a27baf183be # first bad commit: [34ac3c3eb8f0c07252ceddf0a22dd240e5c91ccb] ASoC: core: lock client_mutex while removing link components -------------------------------------------------------------------------------

3 2

[alsa-devel] [PATCH v5 0/3] Fix jack detection for Chromebook Pixel
by Fletcher Woodruff 05 Jun '19

05 Jun '19

Headphone/mic jack detection doesn't work on the Chromebook Pixel 2015. This patch changes the irq implementation to support polarity flipping and fixes the configuration code so that correct GPIO pins are read from ACPI. With this series, plugging and unplugging the headphone jack switches between headphones and speakers automatically, and headset microphones are also detected. v5: - Fix void* parameter to devm_request_threaded_irq - Correct authorship for patch 2/3 v4: - Fix incorrect void* cast in rt5677_irq() v3: - Update commit message for patch 1/3 to clarify why we implement our own irq_chip. v2: - Split IRQ change into two patches: adding and fixing potential race - Change config reading code to try both DT and ACPI style names Ben Zhang (2): ASoC: rt5677: allow multiple interrupt sources ASoC: rt5677: handle concurrent interrupts Fletcher Woodruff (1): ASoC: rt5677: fall back to DT prop names on error sound/soc/codecs/rt5677.c | 346 ++++++++++++++++++++++++++------------ sound/soc/codecs/rt5677.h | 14 +- 2 files changed, 256 insertions(+), 104 deletions(-) -- 2.21.0.1020.gf2820cf01a-goog

3 13

[alsa-devel] [PATCH 1/6] device property: Add new array helper
by Charles Keepax 05 Jun '19

05 Jun '19

It is fairly common to want to read an integer array property that is composed of an unknown number of fixed size integer groups. For example, say each group consists of three values which correspond to the settings for one input on the device and the driver supports several chips with different numbers of inputs. Add a new helper function to provide this functionality, it differs for the existing helpers in that it allows reading a smaller number of values than the full array size and checks that the number of values read is a multiple of the group size. Signed-off-by: Charles Keepax <ckeepax(a)opensource.cirrus.com> --- drivers/base/property.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/property.h | 2 ++ 2 files changed, 50 insertions(+) diff --git a/drivers/base/property.c b/drivers/base/property.c index 348b37e64944c..656d21e01a648 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -133,6 +133,54 @@ int device_property_read_u32_array(struct device *dev, const char *propname, EXPORT_SYMBOL_GPL(device_property_read_u32_array); /** + * device_property_read_u32_2darray - return a 2d u32 array property of a device + * @dev: Device to get the property of + * @propname: Name of the property + * @val: The values are stored here or %NULL to return the number of values + * @nval: Size of the @val array + * @multiple: Number of entries in each block of data + * + * Function reads an array of u32 properties split up into fixed size + * sub-groups, with @propname from the device firmware description and + * stores them to @val if found. + * + * Return: Number of values read + * %0 if the property was not found, + * %-EINVAL if given arguments are not valid, + * %-ENODATA if the property does not have a value, + * %-EPROTO if the property is not an array of numbers, + * %-EOVERFLOW if the size of the property is not as expected. + * %-ENXIO if no suitable firmware interface is present. + */ +int device_property_read_u32_2darray(struct device *dev, const char *propname, + u32 *val, size_t nval, int multiple) +{ + int n, ret; + + n = device_property_read_u32_array(dev, propname, NULL, 0); + if (n == -EINVAL) { + return 0; /* missing, ignore */ + } else if (n < 0) { + dev_warn(dev, "%s malformed (%d)\n", propname, n); + return n; + } else if ((n % multiple) != 0) { + dev_warn(dev, "%s not a multiple of %d entries\n", + propname, multiple); + return -EOVERFLOW; + } + + if (n > nval) + n = nval; + + ret = device_property_read_u32_array(dev, propname, val, n); + if (ret < 0) + return ret; + else + return n; +} +EXPORT_SYMBOL_GPL(device_property_read_u32_2darray); + +/** * device_property_read_u64_array - return a u64 array property of a device * @dev: Device to get the property of * @propname: Name of the property diff --git a/include/linux/property.h b/include/linux/property.h index a29369c89e6ef..854867f0d139f 100644 --- a/include/linux/property.h +++ b/include/linux/property.h @@ -43,6 +43,8 @@ int device_property_read_u16_array(struct device *dev, const char *propname, u16 *val, size_t nval); int device_property_read_u32_array(struct device *dev, const char *propname, u32 *val, size_t nval); +int device_property_read_u32_2darray(struct device *dev, const char *propname, + u32 *val, size_t nval, int multiple); int device_property_read_u64_array(struct device *dev, const char *propname, u64 *val, size_t nval); int device_property_read_string_array(struct device *dev, const char *propname, -- 2.11.0

2 8

[alsa-devel] [PATCH] wcd9335: fix a incorrect use of kstrndup()
by Gen Zhang 05 Jun '19

05 Jun '19

In wcd9335_codec_enable_dec(), 'widget_name' is allocated by kstrndup(). However, according to doc: "Note: Use kmemdup_nul() instead if the size is known exactly." So we should use kmemdup_nul() here instead of kstrndup(). Signed-off-by: Gen Zhang <blackgod016574(a)gmail.com> --- diff --git a/sound/soc/codecs/wcd9335.c b/sound/soc/codecs/wcd9335.c index a04a7ce..85737fe 100644 --- a/sound/soc/codecs/wcd9335.c +++ b/sound/soc/codecs/wcd9335.c @@ -2734,7 +2734,7 @@ static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, char *dec; u8 hpf_coff_freq; - widget_name = kstrndup(w->name, 15, GFP_KERNEL); + widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL); if (!widget_name) return -ENOMEM; ---

3 2

[alsa-devel] [PATCH] ASoC: rt1011: Add RT1011 amplifier driver
by shumingf＠realtek.com 04 Jun '19

04 Jun '19

From: Shuming Fan <shumingf(a)realtek.com> This is the initial amplifier driver for rt1011. Signed-off-by: Shuming Fan <shumingf(a)realtek.com> --- .../devicetree/bindings/sound/rt1011.txt | 32 + sound/soc/codecs/Kconfig | 6 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rt1011.c | 2241 +++++++++++++++++ sound/soc/codecs/rt1011.h | 672 +++++ 5 files changed, 2953 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/rt1011.txt create mode 100644 sound/soc/codecs/rt1011.c create mode 100644 sound/soc/codecs/rt1011.h diff --git a/Documentation/devicetree/bindings/sound/rt1011.txt b/Documentation/devicetree/bindings/sound/rt1011.txt new file mode 100644 index 000000000000..35a23e60d679 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rt1011.txt @@ -0,0 +1,32 @@ +RT1011 Mono Class D Audio Amplifier + +This device supports I2C only. + +Required properties: + +- compatible : "realtek,rt1011". + +- reg : The I2C address of the device. This I2C address decide by + two input pins (ASEL1 and ASEL2). + ------------------------------------- + | ASEL2 | ASEL1 | Address | + ------------------------------------- + | 0 | 0 | 0x38 | + ------------------------------------- + | 0 | 1 | 0x39 | + ------------------------------------- + | 1 | 0 | 0x3a | + ------------------------------------- + | 1 | 1 | 0x3b | + ------------------------------------- + +Pins on the device (for linking into audio routes) for RT1011: + + * SPO + +Example: + +rt1011: codec@38 { + compatible = "realtek,rt1011"; + reg = <0x38>; +}; diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 8f577258080b..5264bd0c6227 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -139,6 +139,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_RT274 if I2C select SND_SOC_RT286 if I2C select SND_SOC_RT298 if I2C + select SND_SOC_RT1011 if I2C select SND_SOC_RT1305 if I2C select SND_SOC_RT5514 if I2C select SND_SOC_RT5616 if I2C @@ -869,6 +870,7 @@ config SND_SOC_RL6231 default y if SND_SOC_RT5670=y default y if SND_SOC_RT5677=y default y if SND_SOC_RT5682=y + default y if SND_SOC_RT1011=y default y if SND_SOC_RT1305=y default m if SND_SOC_RT5514=m default m if SND_SOC_RT5616=m @@ -883,6 +885,7 @@ config SND_SOC_RL6231 default m if SND_SOC_RT5670=m default m if SND_SOC_RT5677=m default m if SND_SOC_RT5682=m + default m if SND_SOC_RT1011=m default m if SND_SOC_RT1305=m config SND_SOC_RL6347A @@ -906,6 +909,9 @@ config SND_SOC_RT298 tristate depends on I2C +config SND_SOC_RT1011 + tristate + config SND_SOC_RT1305 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index aa7720a7a0aa..5d895933b116 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -141,6 +141,7 @@ snd-soc-pcm512x-spi-objs := pcm512x-spi.o snd-soc-rk3328-objs := rk3328_codec.o snd-soc-rl6231-objs := rl6231.o snd-soc-rl6347a-objs := rl6347a.o +snd-soc-rt1011-objs := rt1011.o snd-soc-rt1305-objs := rt1305.o snd-soc-rt274-objs := rt274.o snd-soc-rt286-objs := rt286.o @@ -415,6 +416,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o obj-$(CONFIG_SND_SOC_RK3328) += snd-soc-rk3328.o obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o +obj-$(CONFIG_SND_SOC_RT1011) += snd-soc-rt1011.o obj-$(CONFIG_SND_SOC_RT1305) += snd-soc-rt1305.o obj-$(CONFIG_SND_SOC_RT274) += snd-soc-rt274.o obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o diff --git a/sound/soc/codecs/rt1011.c b/sound/soc/codecs/rt1011.c new file mode 100644 index 000000000000..349d6db7ecd4 --- /dev/null +++ b/sound/soc/codecs/rt1011.c @@ -0,0 +1,2241 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rt1011.c -- rt1011 ALSA SoC amplifier component driver + * + * Copyright(c) 2019 Realtek Semiconductor Corp. + * + * Author: Shuming Fan <shumingf(a)realtek.com> + * + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/acpi.h> +#include <linux/regmap.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/firmware.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> + +#include "rl6231.h" +#include "rt1011.h" + +static int rt1011_calibrate(struct rt1011_priv *rt1011, + unsigned char cali_flag); + +static const struct reg_sequence init_list[] = { + + { RT1011_POWER_9, 0xa840 }, + + { RT1011_ADC_SET_5, 0x0a20 }, + { RT1011_DAC_SET_2, 0xa232 }, + { RT1011_ADC_SET_1, 0x2925 }, + + { RT1011_SPK_PRO_DC_DET_1, 0xb00c }, + { RT1011_SPK_PRO_DC_DET_2, 0xcccc }, + + { RT1011_A_TIMING_1, 0x6054 }, + + { RT1011_POWER_7, 0x3e55 }, + { RT1011_POWER_8, 0x0520 }, + { RT1011_BOOST_CON_1, 0xe188 }, + { RT1011_POWER_4, 0x16f2 }, + + { RT1011_CROSS_BQ_SET_1, 0x0004 }, + { RT1011_SIL_DET, 0xc313 }, + { RT1011_SINE_GEN_REG_1, 0x0707 }, + + { RT1011_DC_CALIB_CLASSD_3, 0xcb00 }, + + { RT1011_DAC_SET_1, 0xe702 }, + { RT1011_DAC_SET_3, 0x2004 }, +}; +#define RT1011_INIT_REG_LEN ARRAY_SIZE(init_list) + +static const struct reg_default rt1011_reg[] = { + {0x0000, 0x0000}, + {0x0002, 0x0000}, + {0x0004, 0xa000}, + {0x0006, 0x0000}, + {0x0008, 0x0003}, + {0x000a, 0x087e}, + {0x000c, 0x0020}, + {0x000e, 0x9002}, + {0x0010, 0x0000}, + {0x0012, 0x0000}, + {0x0020, 0x0c40}, + {0x0022, 0x4313}, + {0x0076, 0x0000}, + {0x0078, 0x0000}, + {0x007a, 0x0000}, + {0x007c, 0x10ec}, + {0x007d, 0x1011}, + {0x00f0, 0x5000}, + {0x00f2, 0x0374}, + {0x00f3, 0x0000}, + {0x00f4, 0x0000}, + {0x0100, 0x0038}, + {0x0102, 0xff02}, + {0x0104, 0x0232}, + {0x0106, 0x200c}, + {0x0107, 0x0000}, + {0x0108, 0x2f2f}, + {0x010a, 0x2f2f}, + {0x010c, 0x002f}, + {0x010e, 0xe000}, + {0x0110, 0x0820}, + {0x0111, 0x4010}, + {0x0112, 0x0000}, + {0x0114, 0x0000}, + {0x0116, 0x0000}, + {0x0118, 0x0000}, + {0x011a, 0x0101}, + {0x011c, 0x4567}, + {0x011e, 0x0000}, + {0x0120, 0x0000}, + {0x0122, 0x0000}, + {0x0124, 0x0123}, + {0x0126, 0x4567}, + {0x0200, 0x0000}, + {0x0300, 0xffdd}, + {0x0302, 0x001e}, + {0x0311, 0x0000}, + {0x0313, 0x5254}, + {0x0314, 0x0062}, + {0x0316, 0x7f40}, + {0x0319, 0x000f}, + {0x031a, 0xffff}, + {0x031b, 0x0000}, + {0x031c, 0x009f}, + {0x031d, 0xffff}, + {0x031e, 0x0000}, + {0x031f, 0x0000}, + {0x0320, 0xe31c}, + {0x0321, 0x0000}, + {0x0322, 0x0000}, + {0x0324, 0x0000}, + {0x0326, 0x0002}, + {0x0328, 0x20b2}, + {0x0329, 0x0175}, + {0x032a, 0x32ad}, + {0x032b, 0x3455}, + {0x032c, 0x0528}, + {0x032d, 0xa800}, + {0x032e, 0x030e}, + {0x0330, 0x2080}, + {0x0332, 0x0034}, + {0x0334, 0x0000}, + {0x0508, 0x0010}, + {0x050a, 0x0018}, + {0x050c, 0x0000}, + {0x050d, 0xffff}, + {0x050e, 0x1f1f}, + {0x050f, 0x04ff}, + {0x0510, 0x4020}, + {0x0511, 0x01f0}, + {0x0512, 0x0702}, + {0x0516, 0xbb80}, + {0x0517, 0xffff}, + {0x0518, 0xffff}, + {0x0519, 0x307f}, + {0x051a, 0xffff}, + {0x051b, 0x0000}, + {0x051c, 0x0000}, + {0x051d, 0x2000}, + {0x051e, 0x0000}, + {0x051f, 0x0000}, + {0x0520, 0x0000}, + {0x0521, 0x1001}, + {0x0522, 0x7fff}, + {0x0524, 0x7fff}, + {0x0526, 0x0000}, + {0x0528, 0x0000}, + {0x052a, 0x0000}, + {0x0530, 0x0401}, + {0x0532, 0x3000}, + {0x0534, 0x0000}, + {0x0535, 0xffff}, + {0x0536, 0x101c}, + {0x0538, 0x1814}, + {0x053a, 0x100c}, + {0x053c, 0x0804}, + {0x053d, 0x0000}, + {0x053e, 0x0000}, + {0x053f, 0x0000}, + {0x0540, 0x0000}, + {0x0541, 0x0000}, + {0x0542, 0x0000}, + {0x0543, 0x0000}, + {0x0544, 0x001c}, + {0x0545, 0x1814}, + {0x0546, 0x100c}, + {0x0547, 0x0804}, + {0x0548, 0x0000}, + {0x0549, 0x0000}, + {0x054a, 0x0000}, + {0x054b, 0x0000}, + {0x054c, 0x0000}, + {0x054d, 0x0000}, + {0x054e, 0x0000}, + {0x054f, 0x0000}, + {0x0566, 0x0000}, + {0x0568, 0x20f1}, + {0x056a, 0x0007}, + {0x0600, 0x9d00}, + {0x0611, 0x2000}, + {0x0612, 0x505f}, + {0x0613, 0x0444}, + {0x0614, 0x4000}, + {0x0615, 0x4004}, + {0x0616, 0x0606}, + {0x0617, 0x8904}, + {0x0618, 0xe021}, + {0x0621, 0x2000}, + {0x0622, 0x505f}, + {0x0623, 0x0444}, + {0x0624, 0x4000}, + {0x0625, 0x4004}, + {0x0626, 0x0606}, + {0x0627, 0x8704}, + {0x0628, 0xe021}, + {0x0631, 0x2000}, + {0x0632, 0x517f}, + {0x0633, 0x0440}, + {0x0634, 0x4000}, + {0x0635, 0x4104}, + {0x0636, 0x0306}, + {0x0637, 0x8904}, + {0x0638, 0xe021}, + {0x0702, 0x0014}, + {0x0704, 0x0000}, + {0x0706, 0x0014}, + {0x0708, 0x0000}, + {0x070a, 0x0000}, + {0x0710, 0x0200}, + {0x0711, 0x0000}, + {0x0712, 0x0200}, + {0x0713, 0x0000}, + {0x0720, 0x0200}, + {0x0721, 0x0000}, + {0x0722, 0x0000}, + {0x0723, 0x0000}, + {0x0724, 0x0000}, + {0x0725, 0x0000}, + {0x0726, 0x0000}, + {0x0727, 0x0000}, + {0x0728, 0x0000}, + {0x0729, 0x0000}, + {0x0730, 0x0200}, + {0x0731, 0x0000}, + {0x0732, 0x0000}, + {0x0733, 0x0000}, + {0x0734, 0x0000}, + {0x0735, 0x0000}, + {0x0736, 0x0000}, + {0x0737, 0x0000}, + {0x0738, 0x0000}, + {0x0739, 0x0000}, + {0x0740, 0x0200}, + {0x0741, 0x0000}, + {0x0742, 0x0000}, + {0x0743, 0x0000}, + {0x0744, 0x0000}, + {0x0745, 0x0000}, + {0x0746, 0x0000}, + {0x0747, 0x0000}, + {0x0748, 0x0000}, + {0x0749, 0x0000}, + {0x0750, 0x0200}, + {0x0751, 0x0000}, + {0x0752, 0x0000}, + {0x0753, 0x0000}, + {0x0754, 0x0000}, + {0x0755, 0x0000}, + {0x0756, 0x0000}, + {0x0757, 0x0000}, + {0x0758, 0x0000}, + {0x0759, 0x0000}, + {0x0760, 0x0200}, + {0x0761, 0x0000}, + {0x0762, 0x0000}, + {0x0763, 0x0000}, + {0x0764, 0x0000}, + {0x0765, 0x0000}, + {0x0766, 0x0000}, + {0x0767, 0x0000}, + {0x0768, 0x0000}, + {0x0769, 0x0000}, + {0x0770, 0x0200}, + {0x0771, 0x0000}, + {0x0772, 0x0000}, + {0x0773, 0x0000}, + {0x0774, 0x0000}, + {0x0775, 0x0000}, + {0x0776, 0x0000}, + {0x0777, 0x0000}, + {0x0778, 0x0000}, + {0x0779, 0x0000}, + {0x0780, 0x0200}, + {0x0781, 0x0000}, + {0x0782, 0x0000}, + {0x0783, 0x0000}, + {0x0784, 0x0000}, + {0x0785, 0x0000}, + {0x0786, 0x0000}, + {0x0787, 0x0000}, + {0x0788, 0x0000}, + {0x0789, 0x0000}, + {0x0790, 0x0200}, + {0x0791, 0x0000}, + {0x0792, 0x0000}, + {0x0793, 0x0000}, + {0x0794, 0x0000}, + {0x0795, 0x0000}, + {0x0796, 0x0000}, + {0x0797, 0x0000}, + {0x0798, 0x0000}, + {0x0799, 0x0000}, + {0x07a0, 0x0200}, + {0x07a1, 0x0000}, + {0x07a2, 0x0000}, + {0x07a3, 0x0000}, + {0x07a4, 0x0000}, + {0x07a5, 0x0000}, + {0x07a6, 0x0000}, + {0x07a7, 0x0000}, + {0x07a8, 0x0000}, + {0x07a9, 0x0000}, + {0x07b0, 0x0200}, + {0x07b1, 0x0000}, + {0x07b2, 0x0000}, + {0x07b3, 0x0000}, + {0x07b4, 0x0000}, + {0x07b5, 0x0000}, + {0x07b6, 0x0000}, + {0x07b7, 0x0000}, + {0x07b8, 0x0000}, + {0x07b9, 0x0000}, + {0x07c0, 0x0200}, + {0x07c1, 0x0000}, + {0x07c2, 0x0000}, + {0x07c3, 0x0000}, + {0x07c4, 0x0000}, + {0x07c5, 0x0000}, + {0x07c6, 0x0000}, + {0x07c7, 0x0000}, + {0x07c8, 0x0000}, + {0x07c9, 0x0000}, + {0x1000, 0x4040}, + {0x1002, 0x6505}, + {0x1004, 0x5405}, + {0x1006, 0x5555}, + {0x1007, 0x003f}, + {0x1008, 0x7fd7}, + {0x1009, 0x770f}, + {0x100a, 0xfffe}, + {0x100b, 0xe000}, + {0x100c, 0x0000}, + {0x100d, 0x0007}, + {0x1010, 0xa433}, + {0x1020, 0x0000}, + {0x1022, 0x0000}, + {0x1024, 0x0000}, + {0x1200, 0x5a01}, + {0x1202, 0x6324}, + {0x1204, 0x0b00}, + {0x1206, 0x0000}, + {0x1208, 0x0000}, + {0x120a, 0x0024}, + {0x120c, 0x0000}, + {0x120e, 0x000e}, + {0x1210, 0x0000}, + {0x1212, 0x0000}, + {0x1300, 0x0701}, + {0x1302, 0x12f9}, + {0x1304, 0x3405}, + {0x1305, 0x0844}, + {0x1306, 0x5611}, + {0x1308, 0x555e}, + {0x130a, 0xa605}, + {0x130c, 0x2000}, + {0x130e, 0x0000}, + {0x130f, 0x0001}, + {0x1310, 0xaa48}, + {0x1312, 0x0285}, + {0x1314, 0xaaaa}, + {0x1316, 0xaaa0}, + {0x1318, 0x2aaa}, + {0x131a, 0xaa07}, + {0x1322, 0x0029}, + {0x1323, 0x4a52}, + {0x1324, 0x002c}, + {0x1325, 0x0b02}, + {0x1326, 0x002d}, + {0x1327, 0x6b5a}, + {0x1328, 0x002e}, + {0x1329, 0xcbb2}, + {0x132a, 0x0030}, + {0x132b, 0x2c0b}, + {0x1330, 0x0031}, + {0x1331, 0x8c63}, + {0x1332, 0x0032}, + {0x1333, 0xecbb}, + {0x1334, 0x0034}, + {0x1335, 0x4d13}, + {0x1336, 0x0037}, + {0x1337, 0x0dc3}, + {0x1338, 0x003d}, + {0x1339, 0xef7b}, + {0x133a, 0x0044}, + {0x133b, 0xd134}, + {0x133c, 0x0047}, + {0x133d, 0x91e4}, + {0x133e, 0x004d}, + {0x133f, 0xc370}, + {0x1340, 0x0053}, + {0x1341, 0xf4fd}, + {0x1342, 0x0060}, + {0x1343, 0x5816}, + {0x1344, 0x006c}, + {0x1345, 0xbb2e}, + {0x1346, 0x0072}, + {0x1347, 0xecbb}, + {0x1348, 0x0076}, + {0x1349, 0x5d97}, + {0x1500, 0x0702}, + {0x1502, 0x002f}, + {0x1504, 0x0000}, + {0x1510, 0x0064}, + {0x1512, 0x0000}, + {0x1514, 0xdf47}, + {0x1516, 0x079c}, + {0x1518, 0xfbf5}, + {0x151a, 0x00bc}, + {0x151c, 0x3b85}, + {0x151e, 0x02b3}, + {0x1520, 0x3333}, + {0x1522, 0x0000}, + {0x1524, 0x4000}, + {0x1528, 0x0064}, + {0x152a, 0x0000}, + {0x152c, 0x0000}, + {0x152e, 0x0000}, + {0x1530, 0x0000}, + {0x1532, 0x0000}, + {0x1534, 0x0000}, + {0x1536, 0x0000}, + {0x1538, 0x0040}, + {0x1539, 0x0000}, + {0x153a, 0x0040}, + {0x153b, 0x0000}, + {0x153c, 0x0064}, + {0x153e, 0x0bf9}, + {0x1540, 0xb2a9}, + {0x1544, 0x0200}, + {0x1546, 0x0000}, + {0x1548, 0x00ca}, + {0x1552, 0x03ff}, + {0x1554, 0x017f}, + {0x1556, 0x017f}, + {0x155a, 0x0000}, + {0x155c, 0x0000}, + {0x1560, 0x0040}, + {0x1562, 0x0000}, + {0x1570, 0x03ff}, + {0x1571, 0xdcff}, + {0x1572, 0x1e00}, + {0x1573, 0x224f}, + {0x1574, 0x0000}, + {0x1575, 0x0000}, + {0x1576, 0x1e00}, + {0x1577, 0x0000}, + {0x1578, 0x0000}, + {0x1579, 0x1128}, + {0x157a, 0x03ff}, + {0x157b, 0xdcff}, + {0x157c, 0x1e00}, + {0x157d, 0x224f}, + {0x157e, 0x0000}, + {0x157f, 0x0000}, + {0x1580, 0x1e00}, + {0x1581, 0x0000}, + {0x1582, 0x0000}, + {0x1583, 0x1128}, + {0x1590, 0x03ff}, + {0x1591, 0xdcff}, + {0x1592, 0x1e00}, + {0x1593, 0x224f}, + {0x1594, 0x0000}, + {0x1595, 0x0000}, + {0x1596, 0x1e00}, + {0x1597, 0x0000}, + {0x1598, 0x0000}, + {0x1599, 0x1128}, + {0x159a, 0x03ff}, + {0x159b, 0xdcff}, + {0x159c, 0x1e00}, + {0x159d, 0x224f}, + {0x159e, 0x0000}, + {0x159f, 0x0000}, + {0x15a0, 0x1e00}, + {0x15a1, 0x0000}, + {0x15a2, 0x0000}, + {0x15a3, 0x1128}, + {0x15b0, 0x007f}, + {0x15b1, 0xffff}, + {0x15b2, 0x007f}, + {0x15b3, 0xffff}, + {0x15b4, 0x007f}, + {0x15b5, 0xffff}, + {0x15b8, 0x007f}, + {0x15b9, 0xffff}, + {0x15bc, 0x0000}, + {0x15bd, 0x0000}, + {0x15be, 0xff00}, + {0x15bf, 0x0000}, + {0x15c0, 0xff00}, + {0x15c1, 0x0000}, + {0x15c3, 0xfc00}, + {0x15c4, 0xbb80}, + {0x15d0, 0x0000}, + {0x15d1, 0x0000}, + {0x15d2, 0x0000}, + {0x15d3, 0x0000}, + {0x15d4, 0x0000}, + {0x15d5, 0x0000}, + {0x15d6, 0x0000}, + {0x15d7, 0x0000}, + {0x15d8, 0x0200}, + {0x15d9, 0x0000}, + {0x15da, 0x0000}, + {0x15db, 0x0000}, + {0x15dc, 0x0000}, + {0x15dd, 0x0000}, + {0x15de, 0x0000}, + {0x15df, 0x0000}, + {0x15e0, 0x0000}, + {0x15e1, 0x0000}, + {0x15e2, 0x0200}, + {0x15e3, 0x0000}, + {0x15e4, 0x0000}, + {0x15e5, 0x0000}, + {0x15e6, 0x0000}, + {0x15e7, 0x0000}, + {0x15e8, 0x0000}, + {0x15e9, 0x0000}, + {0x15ea, 0x0000}, + {0x15eb, 0x0000}, + {0x15ec, 0x0200}, + {0x15ed, 0x0000}, + {0x15ee, 0x0000}, + {0x15ef, 0x0000}, + {0x15f0, 0x0000}, + {0x15f1, 0x0000}, + {0x15f2, 0x0000}, + {0x15f3, 0x0000}, + {0x15f4, 0x0000}, + {0x15f5, 0x0000}, + {0x15f6, 0x0200}, + {0x15f7, 0x0200}, + {0x15f8, 0x8200}, + {0x15f9, 0x0000}, + {0x1600, 0x007d}, + {0x1601, 0xa178}, + {0x1602, 0x00c2}, + {0x1603, 0x5383}, + {0x1604, 0x0000}, + {0x1605, 0x02c1}, + {0x1606, 0x007d}, + {0x1607, 0xa178}, + {0x1608, 0x00c2}, + {0x1609, 0x5383}, + {0x160a, 0x003e}, + {0x160b, 0xd37d}, + {0x1611, 0x3210}, + {0x1612, 0x7418}, + {0x1613, 0xc0ff}, + {0x1614, 0x0000}, + {0x1615, 0x00ff}, + {0x1616, 0x0000}, + {0x1617, 0x0000}, + {0x1621, 0x6210}, + {0x1622, 0x7418}, + {0x1623, 0xc0ff}, + {0x1624, 0x0000}, + {0x1625, 0x00ff}, + {0x1626, 0x0000}, + {0x1627, 0x0000}, + {0x1631, 0x3a14}, + {0x1632, 0x7418}, + {0x1633, 0xc3ff}, + {0x1634, 0x0000}, + {0x1635, 0x00ff}, + {0x1636, 0x0000}, + {0x1637, 0x0000}, + {0x1638, 0x0000}, + {0x163a, 0x0000}, + {0x163c, 0x0000}, + {0x163e, 0x0000}, + {0x1640, 0x0000}, + {0x1642, 0x0000}, + {0x1644, 0x0000}, + {0x1646, 0x0000}, + {0x1648, 0x0000}, + {0x1650, 0x0000}, + {0x1652, 0x0000}, + {0x1654, 0x0000}, + {0x1656, 0x0000}, + {0x1658, 0x0000}, + {0x1660, 0x0000}, + {0x1662, 0x0000}, + {0x1664, 0x0000}, + {0x1666, 0x0000}, + {0x1668, 0x0000}, + {0x1670, 0x0000}, + {0x1672, 0x0000}, + {0x1674, 0x0000}, + {0x1676, 0x0000}, + {0x1678, 0x0000}, + {0x1680, 0x0000}, + {0x1682, 0x0000}, + {0x1684, 0x0000}, + {0x1686, 0x0000}, + {0x1688, 0x0000}, + {0x1690, 0x0000}, + {0x1692, 0x0000}, + {0x1694, 0x0000}, + {0x1696, 0x0000}, + {0x1698, 0x0000}, + {0x1700, 0x0000}, + {0x1702, 0x0000}, + {0x1704, 0x0000}, + {0x1706, 0x0000}, + {0x1708, 0x0000}, + {0x1710, 0x0000}, + {0x1712, 0x0000}, + {0x1714, 0x0000}, + {0x1716, 0x0000}, + {0x1718, 0x0000}, + {0x1720, 0x0000}, + {0x1722, 0x0000}, + {0x1724, 0x0000}, + {0x1726, 0x0000}, + {0x1728, 0x0000}, + {0x1730, 0x0000}, + {0x1732, 0x0000}, + {0x1734, 0x0000}, + {0x1736, 0x0000}, + {0x1738, 0x0000}, + {0x173a, 0x0000}, + {0x173c, 0x0000}, + {0x173e, 0x0000}, + {0x17bb, 0x0500}, + {0x17bd, 0x0004}, + {0x17bf, 0x0004}, + {0x17c1, 0x0004}, + {0x17c2, 0x7fff}, + {0x17c3, 0x0000}, + {0x17c5, 0x0000}, + {0x17c7, 0x0000}, + {0x17c9, 0x0000}, + {0x17cb, 0x2010}, + {0x17cd, 0x0000}, + {0x17cf, 0x0000}, + {0x17d1, 0x0000}, + {0x17d3, 0x0000}, + {0x17d5, 0x0000}, + {0x17d7, 0x0000}, + {0x17d9, 0x0000}, + {0x17db, 0x0000}, + {0x17dd, 0x0000}, + {0x17df, 0x0000}, + {0x17e1, 0x0000}, + {0x17e3, 0x0000}, + {0x17e5, 0x0000}, + {0x17e7, 0x0000}, + {0x17e9, 0x0000}, + {0x17eb, 0x0000}, + {0x17ed, 0x0000}, + {0x17ef, 0x0000}, + {0x17f1, 0x0000}, + {0x17f3, 0x0000}, + {0x17f5, 0x0000}, + {0x17f7, 0x0000}, + {0x17f9, 0x0000}, + {0x17fb, 0x0000}, + {0x17fd, 0x0000}, + {0x17ff, 0x0000}, + {0x1801, 0x0000}, + {0x1803, 0x0000}, +}; + +static int rt1011_reg_init(struct snd_soc_component *component) +{ + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + + regmap_multi_reg_write(rt1011->regmap, init_list, RT1011_INIT_REG_LEN); + return 0; +} + +static bool rt1011_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RT1011_RESET: + case RT1011_SRC_2: + case RT1011_CLK_DET: + case RT1011_SIL_DET: + case RT1011_VERSION_ID: + case RT1011_VENDOR_ID: + case RT1011_DEVICE_ID: + case RT1011_DUM_RO: + case RT1011_DAC_SET_3: + case RT1011_PWM_CAL: + case RT1011_SPK_VOL_TEST_OUT: + case RT1011_VBAT_VOL_DET_1: + case RT1011_VBAT_TEST_OUT_1: + case RT1011_VBAT_TEST_OUT_2: + case RT1011_VBAT_PROTECTION: + case RT1011_VBAT_DET: + case RT1011_BOOST_CON_1: + case RT1011_SHORT_CIRCUIT_DET_1: + case RT1011_SPK_TEMP_PROTECT_3: + case RT1011_SPK_TEMP_PROTECT_6: + case RT1011_SPK_PRO_DC_DET_3: + case RT1011_SPK_PRO_DC_DET_7: + case RT1011_SPK_PRO_DC_DET_8: + case RT1011_SPL_1: + case RT1011_SPL_4: + case RT1011_EXCUR_PROTECT_1: + case RT1011_CROSS_BQ_SET_1: + case RT1011_CROSS_BQ_SET_2: + case RT1011_BQ_SET_0: + case RT1011_BQ_SET_1: + case RT1011_BQ_SET_2: + case RT1011_TEST_PAD_STATUS: + case RT1011_DC_CALIB_CLASSD_1: + case RT1011_DC_CALIB_CLASSD_5: + case RT1011_DC_CALIB_CLASSD_6: + case RT1011_DC_CALIB_CLASSD_7: + case RT1011_DC_CALIB_CLASSD_8: + case RT1011_SINE_GEN_REG_2: + case RT1011_STP_CALIB_RS_TEMP: + case RT1011_SPK_RESISTANCE_1: + case RT1011_SPK_RESISTANCE_2: + case RT1011_SPK_THERMAL: + case RT1011_ALC_BK_GAIN_O: + case RT1011_ALC_BK_GAIN_O_PRE: + case RT1011_SPK_DC_O_23_16: + case RT1011_SPK_DC_O_15_0: + case RT1011_INIT_RECIPROCAL_SYN_24_16: + case RT1011_INIT_RECIPROCAL_SYN_15_0: + case RT1011_SPK_EXCURSION_23_16: + case RT1011_SPK_EXCURSION_15_0: + case RT1011_SEP_MAIN_OUT_23_16: + case RT1011_SEP_MAIN_OUT_15_0: + case RT1011_ALC_DRC_HB_INTERNAL_5: + case RT1011_ALC_DRC_HB_INTERNAL_6: + case RT1011_ALC_DRC_HB_INTERNAL_7: + case RT1011_ALC_DRC_BB_INTERNAL_5: + case RT1011_ALC_DRC_BB_INTERNAL_6: + case RT1011_ALC_DRC_BB_INTERNAL_7: + case RT1011_ALC_DRC_POS_INTERNAL_5: + case RT1011_ALC_DRC_POS_INTERNAL_6: + case RT1011_ALC_DRC_POS_INTERNAL_7: + case RT1011_ALC_DRC_POS_INTERNAL_8: + case RT1011_ALC_DRC_POS_INTERNAL_9: + case RT1011_ALC_DRC_POS_INTERNAL_10: + case RT1011_ALC_DRC_POS_INTERNAL_11: + case RT1011_IRQ_1: + case RT1011_EFUSE_CONTROL_1: + case RT1011_EFUSE_CONTROL_2: + case RT1011_EFUSE_MATCH_DONE ... RT1011_EFUSE_READ_R0_3_15_0: + return true; + + default: + return false; + } +} + +static bool rt1011_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RT1011_RESET: + case RT1011_CLK_1: + case RT1011_CLK_2: + case RT1011_CLK_3: + case RT1011_CLK_4: + case RT1011_PLL_1: + case RT1011_PLL_2: + case RT1011_SRC_1: + case RT1011_SRC_2: + case RT1011_SRC_3: + case RT1011_CLK_DET: + case RT1011_SIL_DET: + case RT1011_PRIV_INDEX: + case RT1011_PRIV_DATA: + case RT1011_CUSTOMER_ID: + case RT1011_FM_VER: + case RT1011_VERSION_ID: + case RT1011_VENDOR_ID: + case RT1011_DEVICE_ID: + case RT1011_DUM_RW_0: + case RT1011_DUM_YUN: + case RT1011_DUM_RW_1: + case RT1011_DUM_RO: + case RT1011_MAN_I2C_DEV: + case RT1011_DAC_SET_1: + case RT1011_DAC_SET_2: + case RT1011_DAC_SET_3: + case RT1011_ADC_SET: + case RT1011_ADC_SET_1: + case RT1011_ADC_SET_2: + case RT1011_ADC_SET_3: + case RT1011_ADC_SET_4: + case RT1011_ADC_SET_5: + case RT1011_TDM_TOTAL_SET: + case RT1011_TDM1_SET_TCON: + case RT1011_TDM1_SET_1: + case RT1011_TDM1_SET_2: + case RT1011_TDM1_SET_3: + case RT1011_TDM1_SET_4: + case RT1011_TDM1_SET_5: + case RT1011_TDM2_SET_1: + case RT1011_TDM2_SET_2: + case RT1011_TDM2_SET_3: + case RT1011_TDM2_SET_4: + case RT1011_TDM2_SET_5: + case RT1011_PWM_CAL: + case RT1011_MIXER_1: + case RT1011_MIXER_2: + case RT1011_ADRC_LIMIT: + case RT1011_A_PRO: + case RT1011_A_TIMING_1: + case RT1011_A_TIMING_2: + case RT1011_A_TEMP_SEN: + case RT1011_SPK_VOL_DET_1: + case RT1011_SPK_VOL_DET_2: + case RT1011_SPK_VOL_TEST_OUT: + case RT1011_VBAT_VOL_DET_1: + case RT1011_VBAT_VOL_DET_2: + case RT1011_VBAT_TEST_OUT_1: + case RT1011_VBAT_TEST_OUT_2: + case RT1011_VBAT_PROTECTION: + case RT1011_VBAT_DET: + case RT1011_POWER_1: + case RT1011_POWER_2: + case RT1011_POWER_3: + case RT1011_POWER_4: + case RT1011_POWER_5: + case RT1011_POWER_6: + case RT1011_POWER_7: + case RT1011_POWER_8: + case RT1011_POWER_9: + case RT1011_CLASS_D_POS: + case RT1011_BOOST_CON_1: + case RT1011_BOOST_CON_2: + case RT1011_ANALOG_CTRL: + case RT1011_POWER_SEQ: + case RT1011_SHORT_CIRCUIT_DET_1: + case RT1011_SHORT_CIRCUIT_DET_2: + case RT1011_SPK_TEMP_PROTECT_0: + case RT1011_SPK_TEMP_PROTECT_1: + case RT1011_SPK_TEMP_PROTECT_2: + case RT1011_SPK_TEMP_PROTECT_3: + case RT1011_SPK_TEMP_PROTECT_4: + case RT1011_SPK_TEMP_PROTECT_5: + case RT1011_SPK_TEMP_PROTECT_6: + case RT1011_SPK_TEMP_PROTECT_7: + case RT1011_SPK_TEMP_PROTECT_8: + case RT1011_SPK_TEMP_PROTECT_9: + case RT1011_SPK_PRO_DC_DET_1: + case RT1011_SPK_PRO_DC_DET_2: + case RT1011_SPK_PRO_DC_DET_3: + case RT1011_SPK_PRO_DC_DET_4: + case RT1011_SPK_PRO_DC_DET_5: + case RT1011_SPK_PRO_DC_DET_6: + case RT1011_SPK_PRO_DC_DET_7: + case RT1011_SPK_PRO_DC_DET_8: + case RT1011_SPL_1: + case RT1011_SPL_2: + case RT1011_SPL_3: + case RT1011_SPL_4: + case RT1011_THER_FOLD_BACK_1: + case RT1011_THER_FOLD_BACK_2: + case RT1011_EXCUR_PROTECT_1: + case RT1011_EXCUR_PROTECT_2: + case RT1011_EXCUR_PROTECT_3: + case RT1011_EXCUR_PROTECT_4: + case RT1011_BAT_GAIN_1: + case RT1011_BAT_GAIN_2: + case RT1011_BAT_GAIN_3: + case RT1011_BAT_GAIN_4: + case RT1011_BAT_GAIN_5: + case RT1011_BAT_GAIN_6: + case RT1011_BAT_GAIN_7: + case RT1011_BAT_GAIN_8: + case RT1011_BAT_GAIN_9: + case RT1011_BAT_GAIN_10: + case RT1011_BAT_GAIN_11: + case RT1011_BAT_RT_THMAX_1: + case RT1011_BAT_RT_THMAX_2: + case RT1011_BAT_RT_THMAX_3: + case RT1011_BAT_RT_THMAX_4: + case RT1011_BAT_RT_THMAX_5: + case RT1011_BAT_RT_THMAX_6: + case RT1011_BAT_RT_THMAX_7: + case RT1011_BAT_RT_THMAX_8: + case RT1011_BAT_RT_THMAX_9: + case RT1011_BAT_RT_THMAX_10: + case RT1011_BAT_RT_THMAX_11: + case RT1011_BAT_RT_THMAX_12: + case RT1011_SPREAD_SPECTURM: + case RT1011_PRO_GAIN_MODE: + case RT1011_RT_DRC_CROSS: + case RT1011_RT_DRC_HB_1: + case RT1011_RT_DRC_HB_2: + case RT1011_RT_DRC_HB_3: + case RT1011_RT_DRC_HB_4: + case RT1011_RT_DRC_HB_5: + case RT1011_RT_DRC_HB_6: + case RT1011_RT_DRC_HB_7: + case RT1011_RT_DRC_HB_8: + case RT1011_RT_DRC_BB_1: + case RT1011_RT_DRC_BB_2: + case RT1011_RT_DRC_BB_3: + case RT1011_RT_DRC_BB_4: + case RT1011_RT_DRC_BB_5: + case RT1011_RT_DRC_BB_6: + case RT1011_RT_DRC_BB_7: + case RT1011_RT_DRC_BB_8: + case RT1011_RT_DRC_POS_1: + case RT1011_RT_DRC_POS_2: + case RT1011_RT_DRC_POS_3: + case RT1011_RT_DRC_POS_4: + case RT1011_RT_DRC_POS_5: + case RT1011_RT_DRC_POS_6: + case RT1011_RT_DRC_POS_7: + case RT1011_RT_DRC_POS_8: + case RT1011_CROSS_BQ_SET_1: + case RT1011_CROSS_BQ_SET_2: + case RT1011_BQ_SET_0: + case RT1011_BQ_SET_1: + case RT1011_BQ_SET_2: + case RT1011_BQ_PRE_GAIN_28_16: + case RT1011_BQ_PRE_GAIN_15_0: + case RT1011_BQ_POST_GAIN_28_16: + case RT1011_BQ_POST_GAIN_15_0: + case RT1011_BQ_H0_28_16 ... RT1011_BQ_A2_15_0: + case RT1011_BQ_1_H0_28_16 ... RT1011_BQ_1_A2_15_0: + case RT1011_BQ_2_H0_28_16 ... RT1011_BQ_2_A2_15_0: + case RT1011_BQ_3_H0_28_16 ... RT1011_BQ_3_A2_15_0: + case RT1011_BQ_4_H0_28_16 ... RT1011_BQ_4_A2_15_0: + case RT1011_BQ_5_H0_28_16 ... RT1011_BQ_5_A2_15_0: + case RT1011_BQ_6_H0_28_16 ... RT1011_BQ_6_A2_15_0: + case RT1011_BQ_7_H0_28_16 ... RT1011_BQ_7_A2_15_0: + case RT1011_BQ_8_H0_28_16 ... RT1011_BQ_8_A2_15_0: + case RT1011_BQ_9_H0_28_16 ... RT1011_BQ_9_A2_15_0: + case RT1011_BQ_10_H0_28_16 ... RT1011_BQ_10_A2_15_0: + case RT1011_TEST_PAD_STATUS ... RT1011_PLL_INTERNAL_SET: + case RT1011_TEST_OUT_1 ... RT1011_TEST_OUT_3: + case RT1011_DC_CALIB_CLASSD_1 ... RT1011_DC_CALIB_CLASSD_10: + case RT1011_CLASSD_INTERNAL_SET_1 ... RT1011_VREF_LV_1: + case RT1011_SMART_BOOST_TIMING_1 ... RT1011_SMART_BOOST_TIMING_36: + case RT1011_SINE_GEN_REG_1 ... RT1011_SINE_GEN_REG_3: + case RT1011_STP_INITIAL_RS_TEMP ... RT1011_SPK_THERMAL: + case RT1011_STP_OTP_TH ... RT1011_INIT_RECIPROCAL_SYN_15_0: + case RT1011_STP_BQ_1_A1_L_28_16 ... RT1011_STP_BQ_1_H0_R_15_0: + case RT1011_STP_BQ_2_A1_L_28_16 ... RT1011_SEP_RE_REG_15_0: + case RT1011_DRC_CF_PARAMS_1 ... RT1011_DRC_CF_PARAMS_12: + case RT1011_ALC_DRC_HB_INTERNAL_1 ... RT1011_ALC_DRC_HB_INTERNAL_7: + case RT1011_ALC_DRC_BB_INTERNAL_1 ... RT1011_ALC_DRC_BB_INTERNAL_7: + case RT1011_ALC_DRC_POS_INTERNAL_1 ... RT1011_ALC_DRC_POS_INTERNAL_8: + case RT1011_ALC_DRC_POS_INTERNAL_9 ... RT1011_BQ_1_PARAMS_CHECK_5: + case RT1011_BQ_2_PARAMS_CHECK_1 ... RT1011_BQ_2_PARAMS_CHECK_5: + case RT1011_BQ_3_PARAMS_CHECK_1 ... RT1011_BQ_3_PARAMS_CHECK_5: + case RT1011_BQ_4_PARAMS_CHECK_1 ... RT1011_BQ_4_PARAMS_CHECK_5: + case RT1011_BQ_5_PARAMS_CHECK_1 ... RT1011_BQ_5_PARAMS_CHECK_5: + case RT1011_BQ_6_PARAMS_CHECK_1 ... RT1011_BQ_6_PARAMS_CHECK_5: + case RT1011_BQ_7_PARAMS_CHECK_1 ... RT1011_BQ_7_PARAMS_CHECK_5: + case RT1011_BQ_8_PARAMS_CHECK_1 ... RT1011_BQ_8_PARAMS_CHECK_5: + case RT1011_BQ_9_PARAMS_CHECK_1 ... RT1011_BQ_9_PARAMS_CHECK_5: + case RT1011_BQ_10_PARAMS_CHECK_1 ... RT1011_BQ_10_PARAMS_CHECK_5: + case RT1011_IRQ_1 ... RT1011_PART_NUMBER_EFUSE: + case RT1011_EFUSE_CONTROL_1 ... RT1011_EFUSE_READ_R0_3_15_0: + return true; + default: + return false; + } +} + +static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0); +static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1739, 37, 0); + +static const char * const rt1011_din_source_select[] = { + "Left", + "Right", + "Left + Right average", +}; + +static SOC_ENUM_SINGLE_DECL(rt1011_din_source_enum, RT1011_CROSS_BQ_SET_1, 5, + rt1011_din_source_select); + +static const char * const rt1011_tdm_data_out_select[] = { + "TDM_O_LR", "BQ1", "DVOL", "BQ10", "ALC", "DMIX", "ADC_SRC_LR", + "ADC_O_LR", "ADC_MONO", "RSPK_BPF_LR", "DMIX_ADD", "ENVELOPE_FS", + "SEP_O_GAIN", "ALC_BK_GAIN", "STP_V_C", "DMIX_ABST" +}; + +static const char * const rt1011_tdm_l_ch_data_select[] = { + "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" +}; +static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_l_dac1_enum, RT1011_TDM1_SET_4, 12, + rt1011_tdm_l_ch_data_select); +static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_l_dac1_enum, RT1011_TDM2_SET_4, 12, + rt1011_tdm_l_ch_data_select); + +static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_dat_enum, + RT1011_ADCDAT_OUT_SOURCE, 0, rt1011_tdm_data_out_select); +static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_loc_enum, RT1011_TDM1_SET_2, 0, + rt1011_tdm_l_ch_data_select); + +static const char * const rt1011_adc_data_mode_select[] = { + "Stereo", "Mono" +}; +static SOC_ENUM_SINGLE_DECL(rt1011_adc_dout_mode_enum, RT1011_TDM1_SET_1, 12, + rt1011_adc_data_mode_select); + +static const char * const rt1011_tdm_adc_data_len_control[] = { + "1CH", "2CH", "3CH", "4CH", "5CH", "6CH", "7CH", "8CH" +}; +static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_dout_len_enum, RT1011_TDM1_SET_2, 13, + rt1011_tdm_adc_data_len_control); +static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_dout_len_enum, RT1011_TDM2_SET_2, 13, + rt1011_tdm_adc_data_len_control); + +static const char * const rt1011_tdm_adc_swap_select[] = { + "L/R", "R/L", "L/L", "R/R" +}; + +static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc1_1_enum, RT1011_TDM1_SET_3, 6, + rt1011_tdm_adc_swap_select); + +static void rt1011_reset(struct regmap *regmap) +{ + regmap_write(regmap, RT1011_RESET, 0); +} + +static int rt1011_recv_spk_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct rt1011_priv *rt1011 = + snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rt1011->recv_spk_mode; + + return 0; +} + +static int rt1011_recv_spk_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct rt1011_priv *rt1011 = + snd_soc_component_get_drvdata(component); + + if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode) + return 0; + + if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { + rt1011->recv_spk_mode = ucontrol->value.integer.value[0]; + + if (rt1011->recv_spk_mode) { + + /* 1: recevier mode on */ + snd_soc_component_update_bits(component, + RT1011_CLASSD_INTERNAL_SET_3, + RT1011_REG_GAIN_CLASSD_RI_SPK_MASK, + RT1011_REG_GAIN_CLASSD_RI_410K); + snd_soc_component_update_bits(component, + RT1011_CLASSD_INTERNAL_SET_1, + RT1011_RECV_MODE_SPK_MASK, + RT1011_RECV_MODE); + } else { + /* 0: speaker mode on */ + snd_soc_component_update_bits(component, + RT1011_CLASSD_INTERNAL_SET_3, + RT1011_REG_GAIN_CLASSD_RI_SPK_MASK, + RT1011_REG_GAIN_CLASSD_RI_72P5K); + snd_soc_component_update_bits(component, + RT1011_CLASSD_INTERNAL_SET_1, + RT1011_RECV_MODE_SPK_MASK, + RT1011_SPK_MODE); + } + } + + return 0; +} + +static bool rt1011_validate_bq_drc_coeff(unsigned short reg) +{ + if ((reg == RT1011_DAC_SET_1) | + (reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) | + (reg == RT1011_ADC_SET_4) | (reg == RT1011_ADC_SET_5) | + (reg == RT1011_MIXER_1) | + (reg == RT1011_A_TIMING_1) | (reg >= RT1011_POWER_7 && + reg <= RT1011_POWER_8) | + (reg == RT1011_CLASS_D_POS) | (reg == RT1011_ANALOG_CTRL) | + (reg >= RT1011_SPK_TEMP_PROTECT_0 && + reg <= RT1011_SPK_TEMP_PROTECT_6) | + (reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) | + (reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) | + (reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) | + (reg >= RT1011_SMART_BOOST_TIMING_1 && + reg <= RT1011_SMART_BOOST_TIMING_36) | + (reg == RT1011_SINE_GEN_REG_1) | + (reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB && + reg <= RT1011_BQ_6_PARAMS_CHECK_5) | + (reg >= RT1011_BQ_7_PARAMS_CHECK_1 && + reg <= RT1011_BQ_10_PARAMS_CHECK_5)) + return true; + + return false; +} + +static int rt1011_bq_drc_coeff_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct rt1011_priv *rt1011 = + snd_soc_component_get_drvdata(component); + struct rt1011_bq_drc_params *bq_drc_info; + struct rt1011_bq_drc_params *params = + (struct rt1011_bq_drc_params *)ucontrol->value.integer.value; + unsigned int i, mode_idx = 0; + + if (strstr(ucontrol->id.name, "AdvanceMode Initial Set")) + mode_idx = RT1011_ADVMODE_INITIAL_SET; + else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff")) + mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF; + else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff")) + mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF; + else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff")) + mode_idx = RT1011_ADVMODE_BQ_UI_COEFF; + else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff")) + mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF; + else + return -EINVAL; + + pr_info("%s, id.name=%s, mode_idx=%d\n", __func__, + ucontrol->id.name, mode_idx); + bq_drc_info = rt1011->bq_drc_params[mode_idx]; + + for (i = 0; i < RT1011_BQ_DRC_NUM; i++) { + params[i].reg = cpu_to_le16(bq_drc_info[i].reg); + params[i].val = cpu_to_le16(bq_drc_info[i].val); + } + + return 0; +} + +static int rt1011_bq_drc_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct rt1011_priv *rt1011 = + snd_soc_component_get_drvdata(component); + struct rt1011_bq_drc_params *bq_drc_info; + struct rt1011_bq_drc_params *params = + (struct rt1011_bq_drc_params *)ucontrol->value.integer.value; + unsigned int i, mode_idx = 0; + + if (!component->card->instantiated) + return 0; + + if (strstr(ucontrol->id.name, "AdvanceMode Initial Set")) + mode_idx = RT1011_ADVMODE_INITIAL_SET; + else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff")) + mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF; + else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff")) + mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF; + else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff")) + mode_idx = RT1011_ADVMODE_BQ_UI_COEFF; + else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff")) + mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF; + else + return -EINVAL; + + bq_drc_info = rt1011->bq_drc_params[mode_idx]; + memset(bq_drc_info, 0, + sizeof(struct rt1011_bq_drc_params) * RT1011_BQ_DRC_NUM); + + pr_info("%s, id.name=%s, mode_idx=%d\n", __func__, + ucontrol->id.name, mode_idx); + for (i = 0; i < RT1011_BQ_DRC_NUM; i++) { + bq_drc_info[i].reg = le16_to_cpu(params[i].reg); + bq_drc_info[i].val = le16_to_cpu(params[i].val); + } + + for (i = 0; i < RT1011_BQ_DRC_NUM; i++) { + if (bq_drc_info[i].reg == 0) + break; + else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) { + snd_soc_component_write(component, bq_drc_info[i].reg, + bq_drc_info[i].val); + } + } + + return 0; +} + +static int rt1011_bq_drc_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 128; + uinfo->value.integer.max = 0x17ffffff; + + return 0; +} + +#define RT1011_BQ_DRC(xname) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = rt1011_bq_drc_info, \ + .get = rt1011_bq_drc_coeff_get, \ + .put = rt1011_bq_drc_coeff_put \ +} + +static int rt1011_r0_cali_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = 0; + + return 0; +} + +static int rt1011_r0_cali_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + + if (!component->card->instantiated) + return 0; + + if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF && + ucontrol->value.integer.value[0]) + rt1011_calibrate(rt1011, 1); + + return 0; +} + +static int rt1011_r0_load(struct rt1011_priv *rt1011) +{ + if (!rt1011->r0_reg) + return -EINVAL; + + /* write R0 to register */ + regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_24_16, + ((rt1011->r0_reg>>16) & 0x1ff)); + regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_15_0, + (rt1011->r0_reg & 0xffff)); + regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4080); + + return 0; +} + +static int rt1011_r0_load_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rt1011->r0_reg; + + return 0; +} + +static int rt1011_r0_load_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + struct device *dev; + unsigned int r0_integer, r0_factor, format; + + if (ucontrol->value.integer.value[0] == rt1011->r0_reg) + return 0; + + if (!component->card->instantiated) + return 0; + + dev = regmap_get_device(rt1011->regmap); + if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { + rt1011->r0_reg = ucontrol->value.integer.value[0]; + + format = 2147483648; /* 2^24 * 128 */ + r0_integer = format / rt1011->r0_reg / 128; + r0_factor = ((format / rt1011->r0_reg * 100) / 128) + - (r0_integer * 100); + dev_info(dev, "New r0 resistance about %d.%02d ohm, reg=0x%X\n", + r0_integer, r0_factor, rt1011->r0_reg); + + if (rt1011->r0_reg) + rt1011_r0_load(rt1011); + } + + return 0; +} + +static int rt1011_r0_load_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.max = 0x1ffffff; + + return 0; +} + +#define RT1011_R0_LOAD(xname) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = rt1011_r0_load_info, \ + .get = rt1011_r0_load_mode_get, \ + .put = rt1011_r0_load_mode_put \ +} + +static const struct snd_kcontrol_new rt1011_snd_controls[] = { + /* I2S Data In Selection */ + SOC_ENUM("DIN Source", rt1011_din_source_enum), + + /* TDM Data In Selection */ + SOC_ENUM("TDM1 DIN Source", rt1011_tdm1_l_dac1_enum), + SOC_ENUM("TDM2 DIN Source", rt1011_tdm2_l_dac1_enum), + + /* TDM1 Data Out Selection */ + SOC_ENUM("TDM1 DOUT Source", rt1011_tdm1_adc1_dat_enum), + SOC_ENUM("TDM1 DOUT Location", rt1011_tdm1_adc1_loc_enum), + SOC_ENUM("TDM1 ADCDAT Swap Select", rt1011_tdm_adc1_1_enum), + + /* Data Out Mode */ + SOC_ENUM("I2S ADC DOUT Mode", rt1011_adc_dout_mode_enum), + SOC_ENUM("TDM1 DOUT Length", rt1011_tdm1_dout_len_enum), + SOC_ENUM("TDM2 DOUT Length", rt1011_tdm2_dout_len_enum), + + /* Speaker/Receiver Mode */ + SOC_SINGLE_EXT("RECV SPK Mode", SND_SOC_NOPM, 0, 1, 0, + rt1011_recv_spk_mode_get, rt1011_recv_spk_mode_put), + + /* BiQuad/DRC/SmartBoost Settings */ + RT1011_BQ_DRC("AdvanceMode Initial Set"), + RT1011_BQ_DRC("AdvanceMode SEP BQ Coeff"), + RT1011_BQ_DRC("AdvanceMode EQ BQ Coeff"), + RT1011_BQ_DRC("AdvanceMode BQ UI Coeff"), + RT1011_BQ_DRC("AdvanceMode SmartBoost Coeff"), + + /* R0 */ + SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0, + rt1011_r0_cali_get, rt1011_r0_cali_put), + RT1011_R0_LOAD("R0 Load Mode"), +}; + +static int rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(source->dapm); + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + + if (rt1011->sysclk_src == RT1011_FS_SYS_PRE_S_PLL1) + return 1; + else + return 0; +} + +static int rt1011_dac_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + snd_soc_component_update_bits(component, + RT1011_SPK_TEMP_PROTECT_0, + RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, + RT1011_STP_EN | RT1011_STP_RS_CLB_EN); + snd_soc_component_update_bits(component, RT1011_POWER_9, + RT1011_POW_MNL_SDB_MASK, RT1011_POW_MNL_SDB); + msleep(50); + snd_soc_component_update_bits(component, + RT1011_CLASSD_INTERNAL_SET_1, + RT1011_DRIVER_READY_SPK, RT1011_DRIVER_READY_SPK); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_component_update_bits(component, RT1011_POWER_9, + RT1011_POW_MNL_SDB_MASK, 0); + snd_soc_component_update_bits(component, + RT1011_SPK_TEMP_PROTECT_0, + RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 0); + msleep(200); + snd_soc_component_update_bits(component, + RT1011_CLASSD_INTERNAL_SET_1, + RT1011_DRIVER_READY_SPK, 0); + break; + + default: + return 0; + } + + return 0; +} + + +static const struct snd_soc_dapm_widget rt1011_dapm_widgets[] = { + SND_SOC_DAPM_SUPPLY("LDO2", RT1011_POWER_1, + RT1011_POW_LDO2_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ISENSE SPK", RT1011_POWER_1, + RT1011_POW_ISENSE_SPK_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VSENSE SPK", RT1011_POWER_1, + RT1011_POW_VSENSE_SPK_BIT, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("PLL", RT1011_POWER_2, + RT1011_PLLEN_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BG", RT1011_POWER_2, + RT1011_POW_BG_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1011_POWER_2, + RT1011_POW_BG_MBIAS_LV_BIT, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("DET VBAT", RT1011_POWER_3, + RT1011_POW_DET_VBAT_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MBIAS", RT1011_POWER_3, + RT1011_POW_MBIAS_LV_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC I", RT1011_POWER_3, + RT1011_POW_ADC_I_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC V", RT1011_POWER_3, + RT1011_POW_ADC_V_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC T", RT1011_POWER_3, + RT1011_POW_ADC_T_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DITHER ADC T", RT1011_POWER_3, + RT1011_POWD_ADC_T_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MIX I", RT1011_POWER_3, + RT1011_POW_MIX_I_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MIX V", RT1011_POWER_3, + RT1011_POW_MIX_V_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("SUM I", RT1011_POWER_3, + RT1011_POW_SUM_I_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("SUM V", RT1011_POWER_3, + RT1011_POW_SUM_V_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MIX T", RT1011_POWER_3, + RT1011_POW_MIX_T_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VREF", RT1011_POWER_3, + RT1011_POW_VREF_LV_BIT, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("BOOST SWR", RT1011_POWER_4, + RT1011_POW_EN_SWR_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("BGOK SWR", RT1011_POWER_4, + RT1011_POW_EN_PASS_BGOK_SWR_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("VPOK SWR", RT1011_POWER_4, + RT1011_POW_EN_PASS_VPOK_SWR_BIT, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("TEMP REG", RT1011_A_TEMP_SEN, + RT1011_POW_TEMP_REG_BIT, 0, NULL, 0), + + /* Audio Interface */ + SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + /* Digital Interface */ + SND_SOC_DAPM_SUPPLY("DAC Power", RT1011_POWER_1, + RT1011_POW_DAC_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLK12M", RT1011_POWER_1, + RT1011_POW_CLK12M_BIT, 0, NULL, 0), + SND_SOC_DAPM_DAC_E("DAC", NULL, RT1011_DAC_SET_3, + RT1011_DA_MUTE_EN_SFT, 1, rt1011_dac_event, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + + /* Output Lines */ + SND_SOC_DAPM_OUTPUT("SPO"), +}; + +static const struct snd_soc_dapm_route rt1011_dapm_routes[] = { + + { "DAC", NULL, "AIF1RX" }, + { "DAC", NULL, "DAC Power" }, + { "DAC", NULL, "LDO2" }, + { "DAC", NULL, "ISENSE SPK" }, + { "DAC", NULL, "VSENSE SPK" }, + { "DAC", NULL, "CLK12M" }, + + { "DAC", NULL, "PLL", rt1011_is_sys_clk_from_pll }, + { "DAC", NULL, "BG" }, + { "DAC", NULL, "BG MBIAS" }, + + { "DAC", NULL, "BOOST SWR" }, + { "DAC", NULL, "BGOK SWR" }, + { "DAC", NULL, "VPOK SWR" }, + + { "DAC", NULL, "DET VBAT" }, + { "DAC", NULL, "MBIAS" }, + { "DAC", NULL, "VREF" }, + { "DAC", NULL, "ADC I" }, + { "DAC", NULL, "ADC V" }, + { "DAC", NULL, "ADC T" }, + { "DAC", NULL, "DITHER ADC T" }, + { "DAC", NULL, "MIX I" }, + { "DAC", NULL, "MIX V" }, + { "DAC", NULL, "SUM I" }, + { "DAC", NULL, "SUM V" }, + { "DAC", NULL, "MIX T" }, + + { "DAC", NULL, "TEMP REG" }, + + { "SPO", NULL, "DAC" }, +}; + +static int rt1011_get_clk_info(int sclk, int rate) +{ + int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16}; + + if (sclk <= 0 || rate <= 0) + return -EINVAL; + + rate = rate << 8; + for (i = 0; i < ARRAY_SIZE(pd); i++) + if (sclk == rate * pd[i]) + return i; + + return -EINVAL; +} + +static int rt1011_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + unsigned int val_len = 0, ch_len = 0, val_clk, mask_clk; + int pre_div, bclk_ms, frame_size; + + rt1011->lrck = params_rate(params); + pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck); + if (pre_div < 0) { + dev_warn(component->dev, "Force using PLL "); + snd_soc_dai_set_pll(dai, 0, RT1011_PLL1_S_BCLK, + rt1011->lrck * 64, rt1011->lrck * 256); + snd_soc_dai_set_sysclk(dai, RT1011_FS_SYS_PRE_S_PLL1, + rt1011->lrck * 256, SND_SOC_CLOCK_IN); + pre_div = 0; + } + frame_size = snd_soc_params_to_frame_size(params); + if (frame_size < 0) { + dev_err(component->dev, "Unsupported frame size: %d\n", + frame_size); + return -EINVAL; + } + + bclk_ms = frame_size > 32; + rt1011->bclk = rt1011->lrck * (32 << bclk_ms); + + dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", + bclk_ms, pre_div, dai->id); + + dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", + rt1011->lrck, pre_div, dai->id); + + switch (params_width(params)) { + case 16: + val_len |= RT1011_I2S_TX_DL_16B; + val_len |= RT1011_I2S_RX_DL_16B; + ch_len |= RT1011_I2S_CH_TX_LEN_16B; + ch_len |= RT1011_I2S_CH_RX_LEN_16B; + break; + case 20: + val_len |= RT1011_I2S_TX_DL_20B; + val_len |= RT1011_I2S_RX_DL_20B; + ch_len |= RT1011_I2S_CH_TX_LEN_20B; + ch_len |= RT1011_I2S_CH_RX_LEN_20B; + break; + case 24: + val_len |= RT1011_I2S_TX_DL_24B; + val_len |= RT1011_I2S_RX_DL_24B; + ch_len |= RT1011_I2S_CH_TX_LEN_24B; + ch_len |= RT1011_I2S_CH_RX_LEN_24B; + break; + case 32: + val_len |= RT1011_I2S_TX_DL_32B; + val_len |= RT1011_I2S_RX_DL_32B; + ch_len |= RT1011_I2S_CH_TX_LEN_32B; + ch_len |= RT1011_I2S_CH_RX_LEN_32B; + break; + case 8: + val_len |= RT1011_I2S_TX_DL_8B; + val_len |= RT1011_I2S_RX_DL_8B; + ch_len |= RT1011_I2S_CH_TX_LEN_8B; + ch_len |= RT1011_I2S_CH_RX_LEN_8B; + break; + default: + return -EINVAL; + } + + switch (dai->id) { + case RT1011_AIF1: + mask_clk = RT1011_FS_SYS_DIV_MASK; + val_clk = pre_div << RT1011_FS_SYS_DIV_SFT; + snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET, + RT1011_I2S_TX_DL_MASK | RT1011_I2S_RX_DL_MASK, + val_len); + snd_soc_component_update_bits(component, RT1011_TDM1_SET_1, + RT1011_I2S_CH_TX_LEN_MASK | + RT1011_I2S_CH_RX_LEN_MASK, + ch_len); + break; + default: + dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); + return -EINVAL; + } + + snd_soc_component_update_bits(component, + RT1011_CLK_2, mask_clk, val_clk); + + return 0; +} + +static int rt1011_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + unsigned int reg_val = 0, reg_bclk_inv = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + reg_val |= RT1011_I2S_TDM_MS_S; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + reg_bclk_inv |= RT1011_TDM_INV_BCLK; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + break; + case SND_SOC_DAIFMT_LEFT_J: + reg_val |= RT1011_I2S_TDM_DF_LEFT; + break; + case SND_SOC_DAIFMT_DSP_A: + reg_val |= RT1011_I2S_TDM_DF_PCM_A; + break; + case SND_SOC_DAIFMT_DSP_B: + reg_val |= RT1011_I2S_TDM_DF_PCM_B; + break; + default: + return -EINVAL; + } + + switch (dai->id) { + case RT1011_AIF1: + snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET, + RT1011_I2S_TDM_MS_MASK | RT1011_I2S_TDM_DF_MASK, + reg_val); + snd_soc_component_update_bits(component, RT1011_TDM1_SET_1, + RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv); + snd_soc_component_update_bits(component, RT1011_TDM2_SET_1, + RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv); + break; + default: + dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); + return -EINVAL; + } + return 0; +} + +static int rt1011_set_component_sysclk(struct snd_soc_component *component, + int clk_id, int source, unsigned int freq, int dir) +{ + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + unsigned int reg_val = 0; + + if (freq == rt1011->sysclk && clk_id == rt1011->sysclk_src) + return 0; + + /* disable MCLK detect in default */ + snd_soc_component_update_bits(component, RT1011_CLK_DET, + RT1011_EN_MCLK_DET_MASK, 0); + + switch (clk_id) { + case RT1011_FS_SYS_PRE_S_MCLK: + reg_val |= RT1011_FS_SYS_PRE_MCLK; + snd_soc_component_update_bits(component, RT1011_CLK_DET, + RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET); + break; + case RT1011_FS_SYS_PRE_S_BCLK: + reg_val |= RT1011_FS_SYS_PRE_BCLK; + break; + case RT1011_FS_SYS_PRE_S_PLL1: + reg_val |= RT1011_FS_SYS_PRE_PLL1; + break; + case RT1011_FS_SYS_PRE_S_RCCLK: + reg_val |= RT1011_FS_SYS_PRE_RCCLK; + break; + default: + dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); + return -EINVAL; + } + snd_soc_component_update_bits(component, RT1011_CLK_2, + RT1011_FS_SYS_PRE_MASK, reg_val); + rt1011->sysclk = freq; + rt1011->sysclk_src = clk_id; + + dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", + freq, clk_id); + + return 0; +} + +static int rt1011_set_component_pll(struct snd_soc_component *component, + int pll_id, int source, unsigned int freq_in, + unsigned int freq_out) +{ + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + struct rl6231_pll_code pll_code; + int ret; + + if (source == rt1011->pll_src && freq_in == rt1011->pll_in && + freq_out == rt1011->pll_out) + return 0; + + if (!freq_in || !freq_out) { + dev_dbg(component->dev, "PLL disabled\n"); + + rt1011->pll_in = 0; + rt1011->pll_out = 0; + snd_soc_component_update_bits(component, RT1011_CLK_2, + RT1011_FS_SYS_PRE_MASK, RT1011_FS_SYS_PRE_BCLK); + return 0; + } + + switch (source) { + case RT1011_PLL2_S_MCLK: + snd_soc_component_update_bits(component, RT1011_CLK_2, + RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_MCLK); + snd_soc_component_update_bits(component, RT1011_CLK_2, + RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2); + snd_soc_component_update_bits(component, RT1011_CLK_DET, + RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET); + break; + case RT1011_PLL1_S_BCLK: + snd_soc_component_update_bits(component, RT1011_CLK_2, + RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_BCLK); + break; + case RT1011_PLL2_S_RCCLK: + snd_soc_component_update_bits(component, RT1011_CLK_2, + RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_RCCLK); + snd_soc_component_update_bits(component, RT1011_CLK_2, + RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2); + break; + default: + dev_err(component->dev, "Unknown PLL Source %d\n", source); + return -EINVAL; + } + + ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); + if (ret < 0) { + dev_err(component->dev, "Unsupport input clock %d\n", freq_in); + return ret; + } + + dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", + pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), + pll_code.n_code, pll_code.k_code); + + snd_soc_component_write(component, RT1011_PLL_1, + (pll_code.m_bp ? 0 : pll_code.m_code) << RT1011_PLL1_QM_SFT | + pll_code.m_bp << RT1011_PLL1_BPM_SFT | pll_code.n_code); + snd_soc_component_write(component, RT1011_PLL_2, + pll_code.k_code); + + rt1011->pll_in = freq_in; + rt1011->pll_out = freq_out; + rt1011->pll_src = source; + + return 0; +} + +static int rt1011_set_tdm_slot(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) +{ + struct snd_soc_component *component = dai->component; + unsigned int val = 0, tdm_en = 0; + + if (rx_mask || tx_mask) + tdm_en = RT1011_TDM_I2S_DOCK_EN_1; + + switch (slots) { + case 4: + val |= RT1011_I2S_TX_4CH; + val |= RT1011_I2S_RX_4CH; + break; + case 6: + val |= RT1011_I2S_TX_6CH; + val |= RT1011_I2S_RX_6CH; + break; + case 8: + val |= RT1011_I2S_TX_8CH; + val |= RT1011_I2S_RX_8CH; + break; + case 2: + break; + default: + return -EINVAL; + } + + switch (slot_width) { + case 20: + val |= RT1011_I2S_CH_TX_LEN_20B; + val |= RT1011_I2S_CH_RX_LEN_20B; + break; + case 24: + val |= RT1011_I2S_CH_TX_LEN_24B; + val |= RT1011_I2S_CH_RX_LEN_24B; + break; + case 32: + val |= RT1011_I2S_CH_TX_LEN_32B; + val |= RT1011_I2S_CH_RX_LEN_32B; + break; + case 16: + break; + default: + return -EINVAL; + } + + snd_soc_component_update_bits(component, RT1011_TDM1_SET_1, + RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK | + RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val); + snd_soc_component_update_bits(component, RT1011_TDM2_SET_1, + RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK | + RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val); + snd_soc_component_update_bits(component, RT1011_TDM1_SET_2, + RT1011_TDM_I2S_DOCK_EN_1_MASK, tdm_en); + snd_soc_component_update_bits(component, RT1011_TDM2_SET_2, + RT1011_TDM_I2S_DOCK_EN_2_MASK, tdm_en); + snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET, + RT1011_ADCDAT1_PIN_CONFIG | RT1011_ADCDAT2_PIN_CONFIG, + RT1011_ADCDAT1_OUTPUT | RT1011_ADCDAT2_OUTPUT); + + return 0; +} + +static int rt1011_probe(struct snd_soc_component *component) +{ + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + int i; + + rt1011->component = component; + + schedule_work(&rt1011->cali_work); + + rt1011->bq_drc_params = devm_kcalloc(component->dev, + RT1011_ADVMODE_NUM, sizeof(struct rt1011_bq_drc_params *), + GFP_KERNEL); + if (!rt1011->bq_drc_params) + return -ENOMEM; + + for (i = 0; i < RT1011_ADVMODE_NUM; i++) { + rt1011->bq_drc_params[i] = devm_kcalloc(component->dev, + RT1011_BQ_DRC_NUM, sizeof(struct rt1011_bq_drc_params), + GFP_KERNEL); + if (!rt1011->bq_drc_params[i]) + return -ENOMEM; + } + + return 0; +} + +static void rt1011_remove(struct snd_soc_component *component) +{ + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + + cancel_work_sync(&rt1011->cali_work); + rt1011_reset(rt1011->regmap); +} + +#ifdef CONFIG_PM +static int rt1011_suspend(struct snd_soc_component *component) +{ + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + + regcache_cache_only(rt1011->regmap, true); + regcache_mark_dirty(rt1011->regmap); + + return 0; +} + +static int rt1011_resume(struct snd_soc_component *component) +{ + struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component); + + regcache_cache_only(rt1011->regmap, false); + regcache_sync(rt1011->regmap); + + return 0; +} +#else +#define rt1011_suspend NULL +#define rt1011_resume NULL +#endif + +static int rt1011_set_bias_level(struct snd_soc_component *component, + enum snd_soc_bias_level level) +{ + switch (level) { + case SND_SOC_BIAS_OFF: + snd_soc_component_write(component, + RT1011_SYSTEM_RESET_1, 0x0000); + snd_soc_component_write(component, + RT1011_SYSTEM_RESET_2, 0x0000); + snd_soc_component_write(component, + RT1011_SYSTEM_RESET_3, 0x0000); + snd_soc_component_write(component, + RT1011_SYSTEM_RESET_1, 0x003f); + snd_soc_component_write(component, + RT1011_SYSTEM_RESET_2, 0x7fd7); + snd_soc_component_write(component, + RT1011_SYSTEM_RESET_3, 0x770f); + break; + default: + break; + } + + return 0; +} + +#define RT1011_STEREO_RATES SNDRV_PCM_RATE_8000_192000 +#define RT1011_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ + SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static const struct snd_soc_dai_ops rt1011_aif_dai_ops = { + .hw_params = rt1011_hw_params, + .set_fmt = rt1011_set_dai_fmt, + .set_tdm_slot = rt1011_set_tdm_slot, +}; + +static struct snd_soc_dai_driver rt1011_dai[] = { + { + .name = "rt1011-aif", + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT1011_STEREO_RATES, + .formats = RT1011_FORMATS, + }, + .ops = &rt1011_aif_dai_ops, + }, +}; + +static const struct snd_soc_component_driver soc_component_dev_rt1011 = { + .probe = rt1011_probe, + .remove = rt1011_remove, + .suspend = rt1011_suspend, + .resume = rt1011_resume, + .set_bias_level = rt1011_set_bias_level, + .controls = rt1011_snd_controls, + .num_controls = ARRAY_SIZE(rt1011_snd_controls), + .dapm_widgets = rt1011_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt1011_dapm_widgets), + .dapm_routes = rt1011_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt1011_dapm_routes), + .set_sysclk = rt1011_set_component_sysclk, + .set_pll = rt1011_set_component_pll, + .use_pmdown_time = 1, + .endianness = 1, + .non_legacy_dai_naming = 1, +}; + +static const struct regmap_config rt1011_regmap = { + .reg_bits = 16, + .val_bits = 16, + .max_register = RT1011_MAX_REG + 1, + .volatile_reg = rt1011_volatile_register, + .readable_reg = rt1011_readable_register, + .cache_type = REGCACHE_RBTREE, + .reg_defaults = rt1011_reg, + .num_reg_defaults = ARRAY_SIZE(rt1011_reg), + .use_single_read = true, + .use_single_write = true, +}; + +#if defined(CONFIG_OF) +static const struct of_device_id rt1011_of_match[] = { + { .compatible = "realtek,rt1011", }, + {}, +}; +MODULE_DEVICE_TABLE(of, rt1011_of_match); +#endif + +#ifdef CONFIG_ACPI +static struct acpi_device_id rt1011_acpi_match[] = { + {"10EC1011", 0,}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, rt1011_acpi_match); +#endif + +static const struct i2c_device_id rt1011_i2c_id[] = { + { "rt1011", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, rt1011_i2c_id); + +static int rt1011_calibrate(struct rt1011_priv *rt1011, unsigned char cali_flag) +{ + unsigned int value, count = 0, r0[3]; + unsigned int chk_cnt = 50; /* DONT change this */ + unsigned int dc_offset; + unsigned int r0_integer, r0_factor, format; + struct device *dev = regmap_get_device(rt1011->regmap); + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(rt1011->component); + int ret = 0; + + snd_soc_dapm_mutex_lock(dapm); + regcache_cache_bypass(rt1011->regmap, true); + + regmap_write(rt1011->regmap, RT1011_RESET, 0x0000); + regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x740f); + regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x770f); + + /* RC clock */ + regmap_write(rt1011->regmap, RT1011_CLK_2, 0x9400); + regmap_write(rt1011->regmap, RT1011_PLL_1, 0x0800); + regmap_write(rt1011->regmap, RT1011_PLL_2, 0x0020); + regmap_write(rt1011->regmap, RT1011_CLK_DET, 0x0800); + + /* ADC/DAC setting */ + regmap_write(rt1011->regmap, RT1011_ADC_SET_5, 0x0a20); + regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xe232); + regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x2925); + regmap_write(rt1011->regmap, RT1011_ADC_SET_4, 0xc000); + + /* DC detection */ + regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_1, 0xb00c); + regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_2, 0xcccc); + + /* Power */ + regmap_write(rt1011->regmap, RT1011_POWER_1, 0xe0e0); + regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5003); + regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa860); + regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xa032); + + /* POW_PLL / POW_BG / POW_BG_MBIAS_LV / POW_V/I */ + regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0007); + regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5ff7); + regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f44); + regmap_write(rt1011->regmap, RT1011_A_TIMING_1, 0x4054); + regmap_write(rt1011->regmap, RT1011_BAT_GAIN_1, 0x309c); + + /* DC offset from EFUSE */ + regmap_write(rt1011->regmap, RT1011_DC_CALIB_CLASSD_3, 0xcb00); + regmap_write(rt1011->regmap, RT1011_BOOST_CON_1, 0xe080); + regmap_write(rt1011->regmap, RT1011_POWER_4, 0x16f2); + regmap_write(rt1011->regmap, RT1011_POWER_6, 0x36ad); + + /* mixer */ + regmap_write(rt1011->regmap, RT1011_MIXER_1, 0x3f1d); + + /* EFUSE read */ + regmap_write(rt1011->regmap, RT1011_EFUSE_CONTROL_1, 0x0d0a); + msleep(30); + + regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_18_16, &value); + dc_offset = value << 16; + regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_15_0, &value); + dc_offset |= (value & 0xffff); + dev_info(dev, "ADC offset=0x%x\n", dc_offset); + regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_20_16, &value); + dc_offset = value << 16; + regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_15_0, &value); + dc_offset |= (value & 0xffff); + dev_info(dev, "Gain0 offset=0x%x\n", dc_offset); + regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_20_16, &value); + dc_offset = value << 16; + regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_15_0, &value); + dc_offset |= (value & 0xffff); + dev_info(dev, "Gain1 offset=0x%x\n", dc_offset); + + + if (cali_flag) { + /* Class D on */ + regmap_write(rt1011->regmap, RT1011_CLASS_D_POS, 0x010e); + regmap_write(rt1011->regmap, + RT1011_CLASSD_INTERNAL_SET_1, 0x1701); + + /* STP enable */ + regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x8000); + regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_7, 0xf000); + regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4040); + regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0xc000); + regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x07c2); + + r0[0] = r0[1] = r0[2] = count = 0; + while (count < chk_cnt) { + msleep(100); + regmap_read(rt1011->regmap, + RT1011_INIT_RECIPROCAL_SYN_24_16, &value); + r0[count%3] = value << 16; + regmap_read(rt1011->regmap, + RT1011_INIT_RECIPROCAL_SYN_15_0, &value); + r0[count%3] |= value; + + if (r0[count%3] == 0) + continue; + + count++; + + if (r0[0] == r0[1] && r0[1] == r0[2]) + break; + } + if (count > chk_cnt) { + dev_err(dev, "Calibrate R0 Failure\n"); + ret = -EAGAIN; + } else { + format = 2147483648; /* 2^24 * 128 */ + r0_integer = format / r0[0] / 128; + r0_factor = ((format / r0[0] * 100) / 128) + - (r0_integer * 100); + rt1011->r0_reg = r0[0]; + dev_info(dev, "r0 resistance about %d.%02d ohm, reg=0x%X\n", + r0_integer, r0_factor, r0[0]); + } + } + + /* depop */ + regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x0000); + msleep(400); + regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa840); + regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x0702); + regmap_write(rt1011->regmap, RT1011_MIXER_1, 0xffdd); + regmap_write(rt1011->regmap, RT1011_CLASSD_INTERNAL_SET_1, 0x0701); + regmap_write(rt1011->regmap, RT1011_DAC_SET_3, 0xe004); + regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f40); + regmap_write(rt1011->regmap, RT1011_POWER_1, 0x0000); + regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0000); + regmap_write(rt1011->regmap, RT1011_POWER_3, 0x0002); + regmap_write(rt1011->regmap, RT1011_POWER_4, 0x00f2); + + regmap_write(rt1011->regmap, RT1011_RESET, 0x0000); + + if (cali_flag) { + if (count <= chk_cnt) { + regmap_write(rt1011->regmap, + RT1011_INIT_RECIPROCAL_REG_24_16, + ((r0[0]>>16) & 0x1ff)); + regmap_write(rt1011->regmap, + RT1011_INIT_RECIPROCAL_REG_15_0, + (r0[0] & 0xffff)); + regmap_write(rt1011->regmap, + RT1011_SPK_TEMP_PROTECT_4, 0x4080); + } + } + + regcache_cache_bypass(rt1011->regmap, false); + regcache_mark_dirty(rt1011->regmap); + regcache_sync(rt1011->regmap); + snd_soc_dapm_mutex_unlock(dapm); + + return ret; +} + +static void rt1011_calibration_work(struct work_struct *work) +{ + struct rt1011_priv *rt1011 = + container_of(work, struct rt1011_priv, cali_work); + struct snd_soc_component *component = rt1011->component; + + rt1011_calibrate(rt1011, 1); + + /* initial */ + rt1011_reg_init(component); +} + +static int rt1011_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct rt1011_priv *rt1011; + int ret; + unsigned int val; + + rt1011 = devm_kzalloc(&i2c->dev, sizeof(struct rt1011_priv), + GFP_KERNEL); + if (rt1011 == NULL) + return -ENOMEM; + + i2c_set_clientdata(i2c, rt1011); + + rt1011->regmap = devm_regmap_init_i2c(i2c, &rt1011_regmap); + if (IS_ERR(rt1011->regmap)) { + ret = PTR_ERR(rt1011->regmap); + dev_err(&i2c->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val); + if (val != RT1011_DEVICE_ID_NUM) { + dev_err(&i2c->dev, + "Device with ID register %x is not rt1011\n", val); + return -ENODEV; + } + + INIT_WORK(&rt1011->cali_work, rt1011_calibration_work); + + return devm_snd_soc_register_component(&i2c->dev, + &soc_component_dev_rt1011, + rt1011_dai, ARRAY_SIZE(rt1011_dai)); + +} + +static void rt1011_i2c_shutdown(struct i2c_client *client) +{ + struct rt1011_priv *rt1011 = i2c_get_clientdata(client); + + rt1011_reset(rt1011->regmap); +} + + +static struct i2c_driver rt1011_i2c_driver = { + .driver = { + .name = "rt1011", + .of_match_table = of_match_ptr(rt1011_of_match), + .acpi_match_table = ACPI_PTR(rt1011_acpi_match) + }, + .probe = rt1011_i2c_probe, + .shutdown = rt1011_i2c_shutdown, + .id_table = rt1011_i2c_id, +}; +module_i2c_driver(rt1011_i2c_driver); + +MODULE_DESCRIPTION("ASoC RT1011 amplifier driver"); +MODULE_AUTHOR("Shuming Fan <shumingf(a)realtek.com>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/rt1011.h b/sound/soc/codecs/rt1011.h new file mode 100644 index 000000000000..98a38800c4df --- /dev/null +++ b/sound/soc/codecs/rt1011.h @@ -0,0 +1,672 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * rt1011.h -- RT1011 ALSA SoC amplifier component driver header + * + * Copyright(c) 2019 Realtek Semiconductor Corp. + */ + +#ifndef _RT1011_H_ +#define _RT1011_H_ + +#define RT1011_DEVICE_ID_NUM 0x1011 + +#define RT1011_RESET 0x0000 +#define RT1011_CLK_1 0x0002 +#define RT1011_CLK_2 0x0004 +#define RT1011_CLK_3 0x0006 +#define RT1011_CLK_4 0x0008 +#define RT1011_PLL_1 0x000a +#define RT1011_PLL_2 0x000c +#define RT1011_SRC_1 0x000e +#define RT1011_SRC_2 0x0010 +#define RT1011_SRC_3 0x0012 +#define RT1011_CLK_DET 0x0020 +#define RT1011_SIL_DET 0x0022 +#define RT1011_PRIV_INDEX 0x006a +#define RT1011_PRIV_DATA 0x006c +#define RT1011_CUSTOMER_ID 0x0076 +#define RT1011_FM_VER 0x0078 +#define RT1011_VERSION_ID 0x007a +#define RT1011_VENDOR_ID 0x007c +#define RT1011_DEVICE_ID 0x007d +#define RT1011_DUM_RW_0 0x00f0 +#define RT1011_DUM_YUN 0x00f2 +#define RT1011_DUM_RW_1 0x00f3 +#define RT1011_DUM_RO 0x00f4 +#define RT1011_MAN_I2C_DEV 0x0100 +#define RT1011_DAC_SET_1 0x0102 +#define RT1011_DAC_SET_2 0x0104 +#define RT1011_DAC_SET_3 0x0106 +#define RT1011_ADC_SET 0x0107 +#define RT1011_ADC_SET_1 0x0108 +#define RT1011_ADC_SET_2 0x010a +#define RT1011_ADC_SET_3 0x010c +#define RT1011_ADC_SET_4 0x010e +#define RT1011_ADC_SET_5 0x0110 +#define RT1011_TDM_TOTAL_SET 0x0111 +#define RT1011_TDM1_SET_TCON 0x0112 +#define RT1011_TDM1_SET_1 0x0114 +#define RT1011_TDM1_SET_2 0x0116 +#define RT1011_TDM1_SET_3 0x0118 +#define RT1011_TDM1_SET_4 0x011a +#define RT1011_TDM1_SET_5 0x011c +#define RT1011_TDM2_SET_1 0x011e +#define RT1011_TDM2_SET_2 0x0120 +#define RT1011_TDM2_SET_3 0x0122 +#define RT1011_TDM2_SET_4 0x0124 +#define RT1011_TDM2_SET_5 0x0126 +#define RT1011_PWM_CAL 0x0200 +#define RT1011_MIXER_1 0x0300 +#define RT1011_MIXER_2 0x0302 +#define RT1011_ADRC_LIMIT 0x0310 +#define RT1011_A_PRO 0x0311 +#define RT1011_A_TIMING_1 0x0313 +#define RT1011_A_TIMING_2 0x0314 +#define RT1011_A_TEMP_SEN 0x0316 +#define RT1011_SPK_VOL_DET_1 0x0319 +#define RT1011_SPK_VOL_DET_2 0x031a +#define RT1011_SPK_VOL_TEST_OUT 0x031b +#define RT1011_VBAT_VOL_DET_1 0x031c +#define RT1011_VBAT_VOL_DET_2 0x031d +#define RT1011_VBAT_TEST_OUT_1 0x031e +#define RT1011_VBAT_TEST_OUT_2 0x031f +#define RT1011_VBAT_PROTECTION 0x0320 +#define RT1011_VBAT_DET 0x0321 +#define RT1011_POWER_1 0x0322 +#define RT1011_POWER_2 0x0324 +#define RT1011_POWER_3 0x0326 +#define RT1011_POWER_4 0x0328 +#define RT1011_POWER_5 0x0329 +#define RT1011_POWER_6 0x032a +#define RT1011_POWER_7 0x032b +#define RT1011_POWER_8 0x032c +#define RT1011_POWER_9 0x032d +#define RT1011_CLASS_D_POS 0x032e +#define RT1011_BOOST_CON_1 0x0330 +#define RT1011_BOOST_CON_2 0x0332 +#define RT1011_ANALOG_CTRL 0x0334 +#define RT1011_POWER_SEQ 0x0340 +#define RT1011_SHORT_CIRCUIT_DET_1 0x0508 +#define RT1011_SHORT_CIRCUIT_DET_2 0x050a +#define RT1011_SPK_TEMP_PROTECT_0 0x050c +#define RT1011_SPK_TEMP_PROTECT_1 0x050d +#define RT1011_SPK_TEMP_PROTECT_2 0x050e +#define RT1011_SPK_TEMP_PROTECT_3 0x050f +#define RT1011_SPK_TEMP_PROTECT_4 0x0510 +#define RT1011_SPK_TEMP_PROTECT_5 0x0511 +#define RT1011_SPK_TEMP_PROTECT_6 0x0512 +#define RT1011_SPK_TEMP_PROTECT_7 0x0516 +#define RT1011_SPK_TEMP_PROTECT_8 0x0517 +#define RT1011_SPK_TEMP_PROTECT_9 0x0518 +#define RT1011_SPK_PRO_DC_DET_1 0x0519 +#define RT1011_SPK_PRO_DC_DET_2 0x051a +#define RT1011_SPK_PRO_DC_DET_3 0x051b +#define RT1011_SPK_PRO_DC_DET_4 0x051c +#define RT1011_SPK_PRO_DC_DET_5 0x051d +#define RT1011_SPK_PRO_DC_DET_6 0x051e +#define RT1011_SPK_PRO_DC_DET_7 0x051f +#define RT1011_SPK_PRO_DC_DET_8 0x0520 +#define RT1011_SPL_1 0x0521 +#define RT1011_SPL_2 0x0522 +#define RT1011_SPL_3 0x0524 +#define RT1011_SPL_4 0x0526 +#define RT1011_THER_FOLD_BACK_1 0x0528 +#define RT1011_THER_FOLD_BACK_2 0x052a +#define RT1011_EXCUR_PROTECT_1 0x0530 +#define RT1011_EXCUR_PROTECT_2 0x0532 +#define RT1011_EXCUR_PROTECT_3 0x0534 +#define RT1011_EXCUR_PROTECT_4 0x0535 +#define RT1011_BAT_GAIN_1 0x0536 +#define RT1011_BAT_GAIN_2 0x0538 +#define RT1011_BAT_GAIN_3 0x053a +#define RT1011_BAT_GAIN_4 0x053c +#define RT1011_BAT_GAIN_5 0x053d +#define RT1011_BAT_GAIN_6 0x053e +#define RT1011_BAT_GAIN_7 0x053f +#define RT1011_BAT_GAIN_8 0x0540 +#define RT1011_BAT_GAIN_9 0x0541 +#define RT1011_BAT_GAIN_10 0x0542 +#define RT1011_BAT_GAIN_11 0x0543 +#define RT1011_BAT_RT_THMAX_1 0x0544 +#define RT1011_BAT_RT_THMAX_2 0x0545 +#define RT1011_BAT_RT_THMAX_3 0x0546 +#define RT1011_BAT_RT_THMAX_4 0x0547 +#define RT1011_BAT_RT_THMAX_5 0x0548 +#define RT1011_BAT_RT_THMAX_6 0x0549 +#define RT1011_BAT_RT_THMAX_7 0x054a +#define RT1011_BAT_RT_THMAX_8 0x054b +#define RT1011_BAT_RT_THMAX_9 0x054c +#define RT1011_BAT_RT_THMAX_10 0x054d +#define RT1011_BAT_RT_THMAX_11 0x054e +#define RT1011_BAT_RT_THMAX_12 0x054f +#define RT1011_SPREAD_SPECTURM 0x0568 +#define RT1011_PRO_GAIN_MODE 0x056a +#define RT1011_RT_DRC_CROSS 0x0600 +#define RT1011_RT_DRC_HB_1 0x0611 +#define RT1011_RT_DRC_HB_2 0x0612 +#define RT1011_RT_DRC_HB_3 0x0613 +#define RT1011_RT_DRC_HB_4 0x0614 +#define RT1011_RT_DRC_HB_5 0x0615 +#define RT1011_RT_DRC_HB_6 0x0616 +#define RT1011_RT_DRC_HB_7 0x0617 +#define RT1011_RT_DRC_HB_8 0x0618 +#define RT1011_RT_DRC_BB_1 0x0621 +#define RT1011_RT_DRC_BB_2 0x0622 +#define RT1011_RT_DRC_BB_3 0x0623 +#define RT1011_RT_DRC_BB_4 0x0624 +#define RT1011_RT_DRC_BB_5 0x0625 +#define RT1011_RT_DRC_BB_6 0x0626 +#define RT1011_RT_DRC_BB_7 0x0627 +#define RT1011_RT_DRC_BB_8 0x0628 +#define RT1011_RT_DRC_POS_1 0x0631 +#define RT1011_RT_DRC_POS_2 0x0632 +#define RT1011_RT_DRC_POS_3 0x0633 +#define RT1011_RT_DRC_POS_4 0x0634 +#define RT1011_RT_DRC_POS_5 0x0635 +#define RT1011_RT_DRC_POS_6 0x0636 +#define RT1011_RT_DRC_POS_7 0x0637 +#define RT1011_RT_DRC_POS_8 0x0638 +#define RT1011_CROSS_BQ_SET_1 0x0702 +#define RT1011_CROSS_BQ_SET_2 0x0704 +#define RT1011_BQ_SET_0 0x0706 +#define RT1011_BQ_SET_1 0x0708 +#define RT1011_BQ_SET_2 0x070a +#define RT1011_BQ_PRE_GAIN_28_16 0x0710 +#define RT1011_BQ_PRE_GAIN_15_0 0x0711 +#define RT1011_BQ_POST_GAIN_28_16 0x0712 +#define RT1011_BQ_POST_GAIN_15_0 0x0713 + +#define RT1011_BQ_H0_28_16 0x0720 +#define RT1011_BQ_A2_15_0 0x0729 +#define RT1011_BQ_1_H0_28_16 0x0730 +#define RT1011_BQ_1_A2_15_0 0x0739 +#define RT1011_BQ_2_H0_28_16 0x0740 +#define RT1011_BQ_2_A2_15_0 0x0749 +#define RT1011_BQ_3_H0_28_16 0x0750 +#define RT1011_BQ_3_A2_15_0 0x0759 +#define RT1011_BQ_4_H0_28_16 0x0760 +#define RT1011_BQ_4_A2_15_0 0x0769 +#define RT1011_BQ_5_H0_28_16 0x0770 +#define RT1011_BQ_5_A2_15_0 0x0779 +#define RT1011_BQ_6_H0_28_16 0x0780 +#define RT1011_BQ_6_A2_15_0 0x0789 +#define RT1011_BQ_7_H0_28_16 0x0790 +#define RT1011_BQ_7_A2_15_0 0x0799 +#define RT1011_BQ_8_H0_28_16 0x07a0 +#define RT1011_BQ_8_A2_15_0 0x07a9 +#define RT1011_BQ_9_H0_28_16 0x07b0 +#define RT1011_BQ_9_A2_15_0 0x07b9 +#define RT1011_BQ_10_H0_28_16 0x07c0 +#define RT1011_BQ_10_A2_15_0 0x07c9 +#define RT1011_TEST_PAD_STATUS 0x1000 +#define RT1011_SYSTEM_RESET_1 0x1007 +#define RT1011_SYSTEM_RESET_2 0x1008 +#define RT1011_SYSTEM_RESET_3 0x1009 +#define RT1011_ADCDAT_OUT_SOURCE 0x100D +#define RT1011_PLL_INTERNAL_SET 0x1010 +#define RT1011_TEST_OUT_1 0x1020 +#define RT1011_TEST_OUT_3 0x1024 +#define RT1011_DC_CALIB_CLASSD_1 0x1200 +#define RT1011_DC_CALIB_CLASSD_2 0x1202 +#define RT1011_DC_CALIB_CLASSD_3 0x1204 +#define RT1011_DC_CALIB_CLASSD_5 0x1208 +#define RT1011_DC_CALIB_CLASSD_6 0x120a +#define RT1011_DC_CALIB_CLASSD_7 0x120c +#define RT1011_DC_CALIB_CLASSD_8 0x120e +#define RT1011_DC_CALIB_CLASSD_10 0x1212 +#define RT1011_CLASSD_INTERNAL_SET_1 0x1300 +#define RT1011_CLASSD_INTERNAL_SET_3 0x1304 +#define RT1011_CLASSD_INTERNAL_SET_8 0x130c +#define RT1011_VREF_LV_1 0x131a +#define RT1011_SMART_BOOST_TIMING_1 0x1322 +#define RT1011_SMART_BOOST_TIMING_36 0x1349 +#define RT1011_SINE_GEN_REG_1 0x1500 +#define RT1011_SINE_GEN_REG_2 0x1502 +#define RT1011_SINE_GEN_REG_3 0x1504 +#define RT1011_STP_INITIAL_RS_TEMP 0x1510 +#define RT1011_STP_CALIB_RS_TEMP 0x152a +#define RT1011_INIT_RECIPROCAL_REG_24_16 0x1538 +#define RT1011_INIT_RECIPROCAL_REG_15_0 0x1539 +#define RT1011_STP_ALPHA_RECIPROCAL_MSB 0x153e +#define RT1011_SPK_RESISTANCE_1 0x1544 +#define RT1011_SPK_RESISTANCE_2 0x1546 +#define RT1011_SPK_THERMAL 0x1548 +#define RT1011_STP_OTP_TH 0x1552 +#define RT1011_ALC_BK_GAIN_O 0x1554 +#define RT1011_ALC_BK_GAIN_O_PRE 0x1556 +#define RT1011_SPK_DC_O_23_16 0x155a +#define RT1011_SPK_DC_O_15_0 0x155c +#define RT1011_INIT_RECIPROCAL_SYN_24_16 0x1560 +#define RT1011_INIT_RECIPROCAL_SYN_15_0 0x1562 +#define RT1011_STP_BQ_1_A1_L_28_16 0x1570 +#define RT1011_STP_BQ_1_H0_R_15_0 0x1583 +#define RT1011_STP_BQ_2_A1_L_28_16 0x1590 +#define RT1011_SPK_EXCURSION_23_16 0x15be +#define RT1011_SPK_EXCURSION_15_0 0x15bf +#define RT1011_SEP_MAIN_OUT_23_16 0x15c0 +#define RT1011_SEP_MAIN_OUT_15_0 0x15c1 +#define RT1011_SEP_RE_REG_15_0 0x15f9 +#define RT1011_DRC_CF_PARAMS_1 0x1600 +#define RT1011_DRC_CF_PARAMS_12 0x160b +#define RT1011_ALC_DRC_HB_INTERNAL_1 0x1611 +#define RT1011_ALC_DRC_HB_INTERNAL_5 0x1615 +#define RT1011_ALC_DRC_HB_INTERNAL_6 0x1616 +#define RT1011_ALC_DRC_HB_INTERNAL_7 0x1617 +#define RT1011_ALC_DRC_BB_INTERNAL_1 0x1621 +#define RT1011_ALC_DRC_BB_INTERNAL_5 0x1625 +#define RT1011_ALC_DRC_BB_INTERNAL_6 0x1626 +#define RT1011_ALC_DRC_BB_INTERNAL_7 0x1627 +#define RT1011_ALC_DRC_POS_INTERNAL_1 0x1631 +#define RT1011_ALC_DRC_POS_INTERNAL_5 0x1635 +#define RT1011_ALC_DRC_POS_INTERNAL_6 0x1636 +#define RT1011_ALC_DRC_POS_INTERNAL_7 0x1637 +#define RT1011_ALC_DRC_POS_INTERNAL_8 0x1638 +#define RT1011_ALC_DRC_POS_INTERNAL_9 0x163a +#define RT1011_ALC_DRC_POS_INTERNAL_10 0x163c +#define RT1011_ALC_DRC_POS_INTERNAL_11 0x163e +#define RT1011_BQ_1_PARAMS_CHECK_5 0x1648 +#define RT1011_BQ_2_PARAMS_CHECK_1 0x1650 +#define RT1011_BQ_2_PARAMS_CHECK_5 0x1658 +#define RT1011_BQ_3_PARAMS_CHECK_1 0x1660 +#define RT1011_BQ_3_PARAMS_CHECK_5 0x1668 +#define RT1011_BQ_4_PARAMS_CHECK_1 0x1670 +#define RT1011_BQ_4_PARAMS_CHECK_5 0x1678 +#define RT1011_BQ_5_PARAMS_CHECK_1 0x1680 +#define RT1011_BQ_5_PARAMS_CHECK_5 0x1688 +#define RT1011_BQ_6_PARAMS_CHECK_1 0x1690 +#define RT1011_BQ_6_PARAMS_CHECK_5 0x1698 +#define RT1011_BQ_7_PARAMS_CHECK_1 0x1700 +#define RT1011_BQ_7_PARAMS_CHECK_5 0x1708 +#define RT1011_BQ_8_PARAMS_CHECK_1 0x1710 +#define RT1011_BQ_8_PARAMS_CHECK_5 0x1718 +#define RT1011_BQ_9_PARAMS_CHECK_1 0x1720 +#define RT1011_BQ_9_PARAMS_CHECK_5 0x1728 +#define RT1011_BQ_10_PARAMS_CHECK_1 0x1730 +#define RT1011_BQ_10_PARAMS_CHECK_5 0x1738 +#define RT1011_IRQ_1 0x173a +#define RT1011_PART_NUMBER_EFUSE 0x173e +#define RT1011_EFUSE_CONTROL_1 0x17bb +#define RT1011_EFUSE_CONTROL_2 0x17bd +#define RT1011_EFUSE_MATCH_DONE 0x17cb +#define RT1011_EFUSE_ADC_OFFSET_18_16 0x17e5 +#define RT1011_EFUSE_ADC_OFFSET_15_0 0x17e7 +#define RT1011_EFUSE_DAC_OFFSET_G0_20_16 0x17e9 +#define RT1011_EFUSE_DAC_OFFSET_G0_15_0 0x17eb +#define RT1011_EFUSE_DAC_OFFSET_G1_20_16 0x17ed +#define RT1011_EFUSE_DAC_OFFSET_G1_15_0 0x17ef +#define RT1011_EFUSE_READ_R0_3_15_0 0x1803 +#define RT1011_MAX_REG 0x1803 +#define RT1011_REG_DISP_LEN 23 + + +/* CLOCK-2 (0x0004) */ +#define RT1011_FS_SYS_PRE_MASK (0x3 << 14) +#define RT1011_FS_SYS_PRE_SFT 14 +#define RT1011_FS_SYS_PRE_MCLK (0x0 << 14) +#define RT1011_FS_SYS_PRE_BCLK (0x1 << 14) +#define RT1011_FS_SYS_PRE_PLL1 (0x2 << 14) +#define RT1011_FS_SYS_PRE_RCCLK (0x3 << 14) +#define RT1011_PLL1_SRC_MASK (0x1 << 13) +#define RT1011_PLL1_SRC_SFT 13 +#define RT1011_PLL1_SRC_PLL2 (0x0 << 13) +#define RT1011_PLL1_SRC_BCLK (0x1 << 13) +#define RT1011_PLL2_SRC_MASK (0x1 << 12) +#define RT1011_PLL2_SRC_SFT 12 +#define RT1011_PLL2_SRC_MCLK (0x0 << 12) +#define RT1011_PLL2_SRC_RCCLK (0x1 << 12) +#define RT1011_PLL2_SRC_DIV_MASK (0x3 << 10) +#define RT1011_PLL2_SRC_DIV_SFT 10 +#define RT1011_SRCIN_DIV_MASK (0x3 << 8) +#define RT1011_SRCIN_DIV_SFT 8 +#define RT1011_FS_SYS_DIV_MASK (0x7 << 4) +#define RT1011_FS_SYS_DIV_SFT 4 + +/* PLL-1 (0x000a) */ +#define RT1011_PLL1_QM_MASK (0xf << 12) +#define RT1011_PLL1_QM_SFT 12 +#define RT1011_PLL1_BPM_MASK (0x1 << 11) +#define RT1011_PLL1_BPM_SFT 11 +#define RT1011_PLL1_BPM (0x1 << 11) +#define RT1011_PLL1_QN_MASK (0x1ff << 0) +#define RT1011_PLL1_QN_SFT 0 + +/* PLL-2 (0x000c) */ +#define RT1011_PLL2_BPK_MASK (0x1 << 5) +#define RT1011_PLL2_BPK_SFT 5 +#define RT1011_PLL2_BPK (0x1 << 5) +#define RT1011_PLL2_QK_MASK (0x1f << 0) +#define RT1011_PLL2_QK_SFT 0 + +/* Clock Detect (0x0020) */ +#define RT1011_EN_MCLK_DET_MASK (0x1 << 15) +#define RT1011_EN_MCLK_DET_SFT 15 +#define RT1011_EN_MCLK_DET (0x1 << 15) + +/* DAC Setting-2 (0x0104) */ +#define RT1011_EN_CKGEN_DAC_MASK (0x1 << 13) +#define RT1011_EN_CKGEN_DAC_SFT 13 +#define RT1011_EN_CKGEN_DAC (0x1 << 13) + +/* DAC Setting-3 (0x0106) */ +#define RT1011_DA_MUTE_EN_MASK (0x1 << 15) +#define RT1011_DA_MUTE_EN_SFT 15 + +/* ADC Setting-5 (0x0110) */ +#define RT1011_AD_EN_CKGEN_ADC_MASK (0x1 << 9) +#define RT1011_AD_EN_CKGEN_ADC_SFT 9 +#define RT1011_AD_EN_CKGEN_ADC (0x1 << 9) + +/* TDM Total Setting (0x0111) */ +#define RT1011_I2S_TDM_MS_MASK (0x1 << 14) +#define RT1011_I2S_TDM_MS_SFT 14 +#define RT1011_I2S_TDM_MS_S (0x0 << 14) +#define RT1011_I2S_TDM_MS_M (0x1 << 14) +#define RT1011_I2S_TX_DL_MASK (0x7 << 8) +#define RT1011_I2S_TX_DL_SFT 8 +#define RT1011_I2S_TX_DL_16B (0x0 << 8) +#define RT1011_I2S_TX_DL_20B (0x1 << 8) +#define RT1011_I2S_TX_DL_24B (0x2 << 8) +#define RT1011_I2S_TX_DL_32B (0x3 << 8) +#define RT1011_I2S_TX_DL_8B (0x4 << 8) +#define RT1011_I2S_RX_DL_MASK (0x7 << 5) +#define RT1011_I2S_RX_DL_SFT 5 +#define RT1011_I2S_RX_DL_16B (0x0 << 5) +#define RT1011_I2S_RX_DL_20B (0x1 << 5) +#define RT1011_I2S_RX_DL_24B (0x2 << 5) +#define RT1011_I2S_RX_DL_32B (0x3 << 5) +#define RT1011_I2S_RX_DL_8B (0x4 << 5) +#define RT1011_ADCDAT1_PIN_CONFIG (0x1 << 4) +#define RT1011_ADCDAT1_OUTPUT (0x0 << 4) +#define RT1011_ADCDAT1_INPUT (0x1 << 4) +#define RT1011_ADCDAT2_PIN_CONFIG (0x1 << 3) +#define RT1011_ADCDAT2_OUTPUT (0x0 << 3) +#define RT1011_ADCDAT2_INPUT (0x1 << 3) +#define RT1011_I2S_TDM_DF_MASK (0x7 << 0) +#define RT1011_I2S_TDM_DF_SFT 0 +#define RT1011_I2S_TDM_DF_I2S (0x0) +#define RT1011_I2S_TDM_DF_LEFT (0x1) +#define RT1011_I2S_TDM_DF_PCM_A (0x2) +#define RT1011_I2S_TDM_DF_PCM_B (0x3) +#define RT1011_I2S_TDM_DF_PCM_A_N (0x6) +#define RT1011_I2S_TDM_DF_PCM_B_N (0x7) + +/* TDM_tcon Setting (0x0112) */ +#define RT1011_TCON_DF_MASK (0x7 << 13) +#define RT1011_TCON_DF_SFT 13 +#define RT1011_TCON_DF_I2S (0x0 << 13) +#define RT1011_TCON_DF_LEFT (0x1 << 13) +#define RT1011_TCON_DF_PCM_A (0x2 << 13) +#define RT1011_TCON_DF_PCM_B (0x3 << 13) +#define RT1011_TCON_DF_PCM_A_N (0x6 << 13) +#define RT1011_TCON_DF_PCM_B_N (0x7 << 13) +#define RT1011_TCON_BCLK_SEL_MASK (0x3 << 10) +#define RT1011_TCON_BCLK_SEL_SFT 10 +#define RT1011_TCON_BCLK_SEL_32FS (0x0 << 10) +#define RT1011_TCON_BCLK_SEL_64FS (0x1 << 10) +#define RT1011_TCON_BCLK_SEL_128FS (0x2 << 10) +#define RT1011_TCON_BCLK_SEL_256FS (0x3 << 10) +#define RT1011_TCON_CH_LEN_MASK (0x3 << 5) +#define RT1011_TCON_CH_LEN_SFT 5 +#define RT1011_TCON_CH_LEN_16B (0x0 << 5) +#define RT1011_TCON_CH_LEN_20B (0x1 << 5) +#define RT1011_TCON_CH_LEN_24B (0x2 << 5) +#define RT1011_TCON_CH_LEN_32B (0x3 << 5) +#define RT1011_TCON_BCLK_MST_MASK (0x1 << 4) +#define RT1011_TCON_BCLK_MST_SFT 4 +#define RT1011_TCON_BCLK_MST_INV (0x1 << 4) + +/* TDM1 Setting-1 (0x0114) */ +#define RT1011_TDM_INV_BCLK_MASK (0x1 << 15) +#define RT1011_TDM_INV_BCLK_SFT 15 +#define RT1011_TDM_INV_BCLK (0x1 << 15) +#define RT1011_I2S_CH_TX_MASK (0x3 << 10) +#define RT1011_I2S_CH_TX_SFT 10 +#define RT1011_I2S_TX_2CH (0x0 << 10) +#define RT1011_I2S_TX_4CH (0x1 << 10) +#define RT1011_I2S_TX_6CH (0x2 << 10) +#define RT1011_I2S_TX_8CH (0x3 << 10) +#define RT1011_I2S_CH_RX_MASK (0x3 << 8) +#define RT1011_I2S_CH_RX_SFT 8 +#define RT1011_I2S_RX_2CH (0x0 << 8) +#define RT1011_I2S_RX_4CH (0x1 << 8) +#define RT1011_I2S_RX_6CH (0x2 << 8) +#define RT1011_I2S_RX_8CH (0x3 << 8) +#define RT1011_I2S_LR_CH_SEL_MASK (0x1 << 7) +#define RT1011_I2S_LR_CH_SEL_SFT 7 +#define RT1011_I2S_LEFT_CH_SEL (0x0 << 7) +#define RT1011_I2S_RIGHT_CH_SEL (0x1 << 7) +#define RT1011_I2S_CH_TX_LEN_MASK (0x7 << 4) +#define RT1011_I2S_CH_TX_LEN_SFT 4 +#define RT1011_I2S_CH_TX_LEN_16B (0x0 << 4) +#define RT1011_I2S_CH_TX_LEN_20B (0x1 << 4) +#define RT1011_I2S_CH_TX_LEN_24B (0x2 << 4) +#define RT1011_I2S_CH_TX_LEN_32B (0x3 << 4) +#define RT1011_I2S_CH_TX_LEN_8B (0x4 << 4) +#define RT1011_I2S_CH_RX_LEN_MASK (0x7 << 0) +#define RT1011_I2S_CH_RX_LEN_SFT 0 +#define RT1011_I2S_CH_RX_LEN_16B (0x0 << 0) +#define RT1011_I2S_CH_RX_LEN_20B (0x1 << 0) +#define RT1011_I2S_CH_RX_LEN_24B (0x2 << 0) +#define RT1011_I2S_CH_RX_LEN_32B (0x3 << 0) +#define RT1011_I2S_CH_RX_LEN_8B (0x4 << 0) + +/* TDM1 Setting-2 (0x0116) */ +#define RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK (0x7 << 13) +#define RT1011_TDM_I2S_DOCK_ADCDAT_2CH (0x1 << 13) +#define RT1011_TDM_I2S_DOCK_ADCDAT_4CH (0x3 << 13) +#define RT1011_TDM_I2S_DOCK_ADCDAT_6CH (0x5 << 13) +#define RT1011_TDM_I2S_DOCK_ADCDAT_8CH (0x7 << 13) +#define RT1011_TDM_I2S_DOCK_EN_1_MASK (0x1 << 3) +#define RT1011_TDM_I2S_DOCK_EN_1_SFT 3 +#define RT1011_TDM_I2S_DOCK_EN_1 (0x1 << 3) + +/* TDM2 Setting-2 (0x0120) */ +#define RT1011_TDM_I2S_DOCK_ADCDAT_LEN_2_MASK (0x7 << 13) +#define RT1011_TDM_I2S_DOCK_EN_2_MASK (0x1 << 3) +#define RT1011_TDM_I2S_DOCK_EN_2_SFT 3 +#define RT1011_TDM_I2S_DOCK_EN_2 (0x1 << 3) + +/* MIXER 1 (0x0300) */ +#define RT1011_MIXER_MUTE_MIX_I_MASK (0x1 << 15) +#define RT1011_MIXER_MUTE_MIX_I_SFT 15 +#define RT1011_MIXER_MUTE_MIX_I (0x1 << 15) +#define RT1011_MIXER_MUTE_SUM_I_MASK (0x1 << 14) +#define RT1011_MIXER_MUTE_SUM_I_SFT 14 +#define RT1011_MIXER_MUTE_SUM_I (0x1 << 14) +#define RT1011_MIXER_MUTE_MIX_V_MASK (0x1 << 7) +#define RT1011_MIXER_MUTE_MIX_V_SFT 7 +#define RT1011_MIXER_MUTE_MIX_V (0x1 << 7) +#define RT1011_MIXER_MUTE_SUM_V_MASK (0x1 << 6) +#define RT1011_MIXER_MUTE_SUM_V_SFT 6 +#define RT1011_MIXER_MUTE_SUM_V (0x1 << 6) + +/* Analog Temperature Sensor (0x0316) */ +#define RT1011_POW_TEMP_REG (0x1 << 2) +#define RT1011_POW_TEMP_REG_BIT 2 + +/* POWER-1 (0x0322) */ +#define RT1011_POW_LDO2 (0x1 << 15) +#define RT1011_POW_LDO2_BIT 15 +#define RT1011_POW_DAC (0x1 << 14) +#define RT1011_POW_DAC_BIT 14 +#define RT1011_POW_CLK12M (0x1 << 13) +#define RT1011_POW_CLK12M_BIT 13 +#define RT1011_POW_TEMP (0x1 << 12) +#define RT1011_POW_TEMP_BIT 12 +#define RT1011_POW_ISENSE_SPK (0x1 << 7) +#define RT1011_POW_ISENSE_SPK_BIT 7 +#define RT1011_POW_LPF_SPK (0x1 << 6) +#define RT1011_POW_LPF_SPK_BIT 6 +#define RT1011_POW_VSENSE_SPK (0x1 << 5) +#define RT1011_POW_VSENSE_SPK_BIT 5 +#define RT1011_POW_TWO_BATTERY_SPK (0x1 << 4) +#define RT1011_POW_TWO_BATTERY_SPK_BIT 4 + +/* POWER-2 (0x0324) */ +#define RT1011_PLLEN (0x1 << 2) +#define RT1011_PLLEN_BIT 2 +#define RT1011_POW_BG (0x1 << 1) +#define RT1011_POW_BG_BIT 1 +#define RT1011_POW_BG_MBIAS_LV (0x1 << 0) +#define RT1011_POW_BG_MBIAS_LV_BIT 0 + +/* POWER-3 (0x0326) */ +#define RT1011_POW_DET_SPKVDD (0x1 << 15) +#define RT1011_POW_DET_SPKVDD_BIT 15 +#define RT1011_POW_DET_VBAT (0x1 << 14) +#define RT1011_POW_DET_VBAT_BIT 14 +#define RT1011_POW_FC (0x1 << 13) +#define RT1011_POW_FC_BIT 13 +#define RT1011_POW_MBIAS_LV (0x1 << 12) +#define RT1011_POW_MBIAS_LV_BIT 12 +#define RT1011_POW_ADC_I (0x1 << 11) +#define RT1011_POW_ADC_I_BIT 11 +#define RT1011_POW_ADC_V (0x1 << 10) +#define RT1011_POW_ADC_V_BIT 10 +#define RT1011_POW_ADC_T (0x1 << 9) +#define RT1011_POW_ADC_T_BIT 9 +#define RT1011_POWD_ADC_T (0x1 << 8) +#define RT1011_POWD_ADC_T_BIT 8 +#define RT1011_POW_MIX_I (0x1 << 7) +#define RT1011_POW_MIX_I_BIT 7 +#define RT1011_POW_MIX_V (0x1 << 6) +#define RT1011_POW_MIX_V_BIT 6 +#define RT1011_POW_SUM_I (0x1 << 5) +#define RT1011_POW_SUM_I_BIT 5 +#define RT1011_POW_SUM_V (0x1 << 4) +#define RT1011_POW_SUM_V_BIT 4 +#define RT1011_POW_MIX_T (0x1 << 2) +#define RT1011_POW_MIX_T_BIT 2 +#define RT1011_BYPASS_MIX_T (0x1 << 1) +#define RT1011_BYPASS_MIX_T_BIT 1 +#define RT1011_POW_VREF_LV (0x1 << 0) +#define RT1011_POW_VREF_LV_BIT 0 + +/* POWER-4 (0x0328) */ +#define RT1011_POW_EN_SWR (0x1 << 12) +#define RT1011_POW_EN_SWR_BIT 12 +#define RT1011_POW_EN_PASS_BGOK_SWR (0x1 << 10) +#define RT1011_POW_EN_PASS_BGOK_SWR_BIT 10 +#define RT1011_POW_EN_PASS_VPOK_SWR (0x1 << 9) +#define RT1011_POW_EN_PASS_VPOK_SWR_BIT 9 + +/* POWER-9 (0x032d) */ +#define RT1011_POW_SDB_REG_MASK (0x1 << 9) +#define RT1011_POW_SDB_REG_BIT 9 +#define RT1011_POW_SDB_REG (0x1 << 9) +#define RT1011_POW_SEL_SDB_MODE_MASK (0x1 << 6) +#define RT1011_POW_SEL_SDB_MODE_BIT 6 +#define RT1011_POW_SEL_SDB_MODE (0x1 << 6) +#define RT1011_POW_MNL_SDB_MASK (0x1 << 5) +#define RT1011_POW_MNL_SDB_BIT 5 +#define RT1011_POW_MNL_SDB (0x1 << 5) + +/* SPK Protection-Temperature Protection (0x050c) */ +#define RT1011_STP_EN_MASK (0x1 << 15) +#define RT1011_STP_EN_BIT 15 +#define RT1011_STP_EN (0x1 << 15) +#define RT1011_STP_RS_CLB_EN_MASK (0x1 << 14) +#define RT1011_STP_RS_CLB_EN_BIT 14 +#define RT1011_STP_RS_CLB_EN (0x1 << 14) + +/* SPK Protection-Temperature Protection-4 (0x0510) */ +#define RT1011_STP_R0_SELECT_MASK (0x3 << 6) +#define RT1011_STP_R0_SELECT_EFUSE (0x0 << 6) +#define RT1011_STP_R0_SELECT_START_VAL (0x1 << 6) +#define RT1011_STP_R0_SELECT_REG (0x2 << 6) +#define RT1011_STP_R0_SELECT_FORCE_ZERO (0x3 << 6) + +/* SPK Protection-Temperature Protection-6 (0x0512) */ +#define RT1011_STP_R0_EN_MASK (0x1 << 7) +#define RT1011_STP_R0_EN_BIT 7 +#define RT1011_STP_R0_EN (0x1 << 7) +#define RT1011_STP_T0_EN_MASK (0x1 << 6) +#define RT1011_STP_T0_EN_BIT 6 +#define RT1011_STP_T0_EN (0x1 << 6) + +/* ClassD Internal Setting-1 (0x1300) */ +#define RT1011_DRIVER_READY_SPK (0x1 << 12) +#define RT1011_DRIVER_READY_SPK_BIT 12 +#define RT1011_RECV_MODE_SPK_MASK (0x1 << 5) +#define RT1011_SPK_MODE (0x0 << 5) +#define RT1011_RECV_MODE (0x1 << 5) +#define RT1011_RECV_MODE_SPK_BIT 5 + +/* ClassD Internal Setting-3 (0x1304) */ +#define RT1011_REG_GAIN_CLASSD_RI_SPK_MASK (0x7 << 12) +#define RT1011_REG_GAIN_CLASSD_RI_410K (0x0 << 12) +#define RT1011_REG_GAIN_CLASSD_RI_95K (0x1 << 12) +#define RT1011_REG_GAIN_CLASSD_RI_82P5K (0x2 << 12) +#define RT1011_REG_GAIN_CLASSD_RI_72P5K (0x3 << 12) +#define RT1011_REG_GAIN_CLASSD_RI_62P5K (0x4 << 12) + +/* ClassD Internal Setting-8 (0x130c) */ +#define RT1011_TM_PORPVDD_SPK (0x1 << 1) +#define RT1011_TM_PORPVDD_SPK_BIT 1 + +/* SPK Protection-Temperature Protection-SINE_GEN_REG-1 (0x1500) */ +#define RT1011_STP_SIN_GEN_EN_MASK (0x1 << 13) +#define RT1011_STP_SIN_GEN_EN (0x1 << 13) +#define RT1011_STP_SIN_GEN_EN_BIT 13 + + +/* System Clock Source */ +enum { + RT1011_FS_SYS_PRE_S_MCLK, + RT1011_FS_SYS_PRE_S_BCLK, + RT1011_FS_SYS_PRE_S_PLL1, + RT1011_FS_SYS_PRE_S_RCCLK, /* 12M Hz */ +}; + +/* PLL Source 1/2 */ +enum { + RT1011_PLL1_S_BCLK, + RT1011_PLL2_S_MCLK, + RT1011_PLL2_S_RCCLK, /* 12M Hz */ +}; + +enum { + RT1011_AIF1, + RT1011_AIFS +}; + +/* BiQual & DRC related settings */ +#define RT1011_BQ_DRC_NUM 128 +struct rt1011_bq_drc_params { + unsigned short val; + unsigned short reg; +#ifdef CONFIG_64BIT + unsigned int reserved; +#endif +}; +enum { + RT1011_ADVMODE_INITIAL_SET, + RT1011_ADVMODE_SEP_BQ_COEFF, + RT1011_ADVMODE_EQ_BQ_COEFF, + RT1011_ADVMODE_BQ_UI_COEFF, + RT1011_ADVMODE_SMARTBOOST_COEFF, + RT1011_ADVMODE_NUM, +}; + +struct rt1011_priv { + struct snd_soc_component *component; + struct regmap *regmap; + struct work_struct cali_work; + struct rt1011_bq_drc_params **bq_drc_params; + + int sysclk; + int sysclk_src; + int lrck; + int bclk; + int id; + + int pll_src; + int pll_in; + int pll_out; + + int bq_drc_set; + unsigned int r0_reg; + int recv_spk_mode; +}; + +#endif /* end of _RT1011_H_ */ -- 2.21.0

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Alsa-devel May 2019