January 2017 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [PATCH v2 0/9] Allwinner H5 and Orange Pi PC2 support
by Icenowy Zheng 08 Feb '17

08 Feb '17

Allwinner H5 is a 64-bit SoC with a design like the 32-bit H3. This patch adds support for it, along with the first available board -- Orange Pi PC2. P.S. Some patches are sent wrongly, please ignore them. Sorry. Andre Przywara (3): arm: dts: sun8i: split Allwinner H3 .dtsi arm64: dts: allwinner: add Allwinner H5 .dtsi arm64: dts: sunxi: add support for the Orange Pi PC 2 board Icenowy Zheng (6): drivers: pinctrl: add driver for Allwinner H5 SoC arm64: allwinner: Kconfig: add essential pinctrl driver for H5 clk: sunxi-ng: add support for Allwinner H5 SoC clk: sunxi-ng: remove transitional headers for dt-bindings dmaengine: sun6i: allow build on ARM64 platforms (sun50i) ASoC: sunxi: allow the analog codec driver to be built on ARM64 .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + arch/arm/boot/dts/sun8i-h3.dtsi | 501 +----------------- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 557 ++++++++++++++++++++ arch/arm64/Kconfig.platforms | 5 +- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 164 ++++++ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 140 ++++++ arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi | 1 + drivers/clk/sunxi-ng/Kconfig | 6 +- drivers/clk/sunxi-ng/Makefile | 2 +- .../sunxi-ng/{ccu-sun8i-h3.c => ccu-sunxi-h3-h5.c} | 179 ++++++- .../sunxi-ng/{ccu-sun8i-h3.h => ccu-sunxi-h3-h5.h} | 15 +- drivers/dma/Kconfig | 2 +- drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 558 +++++++++++++++++++++ .../clock/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} | 11 +- .../reset/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} | 11 +- sound/soc/sunxi/Kconfig | 2 +- 20 files changed, 1628 insertions(+), 534 deletions(-) create mode 100644 arch/arm/boot/dts/sunxi-h3-h5.dtsi create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi create mode 120000 arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi rename drivers/clk/sunxi-ng/{ccu-sun8i-h3.c => ccu-sunxi-h3-h5.c} (80%) rename drivers/clk/sunxi-ng/{ccu-sun8i-h3.h => ccu-sunxi-h3-h5.h} (82%) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c rename include/dt-bindings/clock/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} (95%) rename include/dt-bindings/reset/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} (94%) -- 2.11.0

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Re: [alsa-devel] [linux-sunxi] Re: [PATCH v3 04/10] clk: sunxi-ng: add support for Allwinner H5 SoC
by Icenowy Zheng 07 Feb '17

07 Feb '17

2017年1月30日 17:04于 Maxime Ripard <maxime.ripard(a)free-electrons.com>写道： > > On Sun, Jan 29, 2017 at 10:33:25AM +0800, Icenowy Zheng wrote: > > Allwinner H5 is a SoC that features a CCU like H3, but with MMC phase > > clocks removed (for new MMC controller) and a new bus gate/reset > > imported. > > > > Add support for it. > > > > Signed-off-by: Icenowy Zheng <icenowy(a)aosc.xyz> > > --- > > See the comments of the previous patch. > > > > .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + > > drivers/clk/sunxi-ng/Kconfig | 2 +- > > drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c | 137 +++++++++++++++++++++ > > drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h | 5 +- > > include/dt-bindings/clock/sunxi-h3-h5-ccu.h | 3 + > > include/dt-bindings/reset/sunxi-h3-h5-ccu.h | 3 + > > 6 files changed, 149 insertions(+), 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > > index f6032cf63f12..a33a4a5ecffa 100644 > > --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > > +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt > > @@ -9,6 +9,7 @@ Required properties : > > - "allwinner,sun8i-h3-ccu" > > - "allwinner,sun8i-v3s-ccu" > > - "allwinner,sun50i-a64-ccu" > > + - "allwinner,sun50i-h5-ccu" > > > > - reg: Must contain the registers base address and length > > - clocks: phandle to the oscillators feeding the CCU. Two are needed: > > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig > > index 4be083ae717f..bdf18e846731 100644 > > --- a/drivers/clk/sunxi-ng/Kconfig > > +++ b/drivers/clk/sunxi-ng/Kconfig > > @@ -117,7 +117,7 @@ config SUNXI_H3_H5_CCU > > select SUNXI_CCU_NM > > select SUNXI_CCU_MP > > select SUNXI_CCU_PHASE > > - default MACH_SUN8I > > + default MACH_SUN8I || (ARM64 && ARCH_SUNXI) > > > > config SUN8I_V3S_CCU > > bool "Support for the Allwinner V3s CCU" > > diff --git a/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c > > index be63b56315f5..b7b9f85f5c9f 100644 > > --- a/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c > > +++ b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c > > @@ -302,6 +302,8 @@ static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", > > 0x06c, BIT(19), 0); > > static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", > > 0x06c, BIT(20), 0); > > +static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2", > > + 0x06c, BIT(21), 0); > > > > static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1", > > 0x070, BIT(0), 0); > > @@ -547,6 +549,7 @@ static struct ccu_common *sunxi_h3_h5_ccu_clks[] = { > > &bus_uart2_clk.common, > > &bus_uart3_clk.common, > > &bus_scr0_clk.common, > > + &bus_scr1_clk.common, > > &bus_ephy_clk.common, > > &bus_dbg_clk.common, > > &ths_clk.common, > > @@ -730,6 +733,122 @@ static struct clk_hw_onecell_data sun8i_h3_hw_clks = { > > .num = CLK_NUMBER, > > }; > > > > +static struct clk_hw_onecell_data sun50i_h5_hw_clks = { > > + .hws = { > > + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, > > + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, > > + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, > > + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, > > + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, > > + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, > > + [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, > > + [CLK_PLL_VE] = &pll_ve_clk.common.hw, > > + [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, > > + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, > > + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, > > + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, > > + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, > > + [CLK_PLL_DE] = &pll_de_clk.common.hw, > > + [CLK_CPUX] = &cpux_clk.common.hw, > > + [CLK_AXI] = &axi_clk.common.hw, > > + [CLK_AHB1] = &ahb1_clk.common.hw, > > + [CLK_APB1] = &apb1_clk.common.hw, > > + [CLK_APB2] = &apb2_clk.common.hw, > > + [CLK_AHB2] = &ahb2_clk.common.hw, > > + [CLK_BUS_CE] = &bus_ce_clk.common.hw, > > + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, > > + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, > > + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, > > + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, > > + [CLK_BUS_NAND] = &bus_nand_clk.common.hw, > > + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, > > + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, > > + [CLK_BUS_TS] = &bus_ts_clk.common.hw, > > + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, > > + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, > > + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, > > + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, > > + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, > > + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, > > + [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw, > > + [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw, > > + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, > > + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, > > + [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw, > > + [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw, > > + [CLK_BUS_VE] = &bus_ve_clk.common.hw, > > + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, > > + [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, > > + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, > > + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, > > + [CLK_BUS_TVE] = &bus_tve_clk.common.hw, > > + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, > > + [CLK_BUS_DE] = &bus_de_clk.common.hw, > > + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, > > + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, > > + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, > > + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, > > + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, > > + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, > > + [CLK_BUS_THS] = &bus_ths_clk.common.hw, > > + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, > > + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, > > + [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, > > + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, > > + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, > > + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, > > + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, > > + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, > > + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, > > + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, > > + [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw, > > + [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw, > > + [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw, > > + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, > > + [CLK_THS] = &ths_clk.common.hw, > > + [CLK_NAND] = &nand_clk.common.hw, > > + [CLK_MMC0] = &mmc0_clk.common.hw, > > + [CLK_MMC1] = &mmc1_clk.common.hw, > > + [CLK_MMC2] = &mmc2_clk.common.hw, > > + [CLK_TS] = &ts_clk.common.hw, > > + [CLK_CE] = &ce_clk.common.hw, > > + [CLK_SPI0] = &spi0_clk.common.hw, > > + [CLK_SPI1] = &spi1_clk.common.hw, > > + [CLK_I2S0] = &i2s0_clk.common.hw, > > + [CLK_I2S1] = &i2s1_clk.common.hw, > > + [CLK_I2S2] = &i2s2_clk.common.hw, > > + [CLK_SPDIF] = &spdif_clk.common.hw, > > + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, > > + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, > > + [CLK_USB_PHY2] = &usb_phy2_clk.common.hw, > > + [CLK_USB_PHY3] = &usb_phy3_clk.common.hw, > > + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, > > + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, > > + [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw, > > + [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw, > > + [CLK_DRAM] = &dram_clk.common.hw, > > + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, > > + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, > > + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, > > + [CLK_DRAM_TS] = &dram_ts_clk.common.hw, > > + [CLK_DE] = &de_clk.common.hw, > > + [CLK_TCON0] = &tcon_clk.common.hw, > > + [CLK_TVE] = &tve_clk.common.hw, > > + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, > > + [CLK_CSI_MISC] = &csi_misc_clk.common.hw, > > + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, > > + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, > > + [CLK_VE] = &ve_clk.common.hw, > > + [CLK_AC_DIG] = &ac_dig_clk.common.hw, > > + [CLK_AVS] = &avs_clk.common.hw, > > + [CLK_HDMI] = &hdmi_clk.common.hw, > > + [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, > > + [CLK_MBUS] = &mbus_clk.common.hw, > > + [CLK_GPU] = &gpu_clk.common.hw, > > + }, > > + .num = CLK_NUMBER, > > +}; > > + > > static struct ccu_reset_map sunxi_h3_h5_ccu_resets[] = { > > [RST_USB_PHY0] = { 0x0cc, BIT(0) }, > > [RST_USB_PHY1] = { 0x0cc, BIT(1) }, > > @@ -791,6 +910,7 @@ static struct ccu_reset_map sunxi_h3_h5_ccu_resets[] = { > > [RST_BUS_UART2] = { 0x2d8, BIT(18) }, > > [RST_BUS_UART3] = { 0x2d8, BIT(19) }, > > [RST_BUS_SCR0] = { 0x2d8, BIT(20) }, > > + [RST_BUS_SCR1] = { 0x2d8, BIT(21) }, > > That reset line is not valid on the H3. So I should split a H3 reset array and a H5 one? (I modelled after ccu-sun5i.c, which shares one reset array) > > Thanks, > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe(a)googlegroups.com. > For more options, visit https://groups.google.com/d/optout.

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[alsa-devel] sound: unable to handle kernel paging request snd_seq_prioq_cell_out
by Dmitry Vyukov 06 Feb '17

06 Feb '17

Hello, The following program triggers wild memory access in snd_seq_prioq_cell_out: https://gist.githubusercontent.com/dvyukov/e0bfb47caf577217b3b0550866cba00b… BUG: unable to handle kernel paging request at ffffc9000392ddb8 IP: snd_seq_prioq_cell_out+0x11d/0x260 sound/core/seq/seq_prioq.c:231 PGD 6cc6f067 PUD 6cc70067 PMD 5f94c067 PTE 0 Oops: 0000 [#1] SMP KASAN Modules linked in: CPU: 2 PID: 375 Comm: syz-executor Not tainted 4.10.0-rc5+ #201 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Bochs 01/01/2011 task: ffff880066f92500 task.stack: ffff88005f740000 RIP: 0010:snd_seq_prioq_cell_out+0x11d/0x260 sound/core/seq/seq_prioq.c:231 RSP: 0018:ffff88005f7470b8 EFLAGS: 00010046 RAX: dffffc0000000000 RBX: 1ffff1000bee8e18 RCX: ffffc90000c22000 RDX: 1ffff92000725bb7 RSI: ffffffff8348787e RDI: ffffc9000392ddb8 RBP: ffff88005f747208 R08: 0000000000000001 R09: 0000000000000001 R10: dffffc0000000000 R11: 0000000000000004 R12: ffff8800673cbe80 R13: ffff88005f7471e0 R14: ffffc9000392dd90 R15: ffff8800673cbe98 FS: 00007f5262fee700(0000) GS:ffff88006d100000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: ffffc9000392ddb8 CR3: 0000000066209000 CR4: 00000000001406e0 Call Trace: snd_seq_prioq_delete+0x8b/0xf0 sound/core/seq/seq_prioq.c:90 queue_delete+0x77/0xb0 sound/core/seq/seq_queue.c:152 snd_seq_queue_client_leave+0x34/0x130 sound/core/seq/seq_queue.c:595 seq_free_client1.part.5+0x10a/0x410 sound/core/seq/seq_clientmgr.c:258 seq_free_client1 sound/core/seq/seq_clientmgr.c:255 [inline] seq_free_client+0x6f/0x170 sound/core/seq/seq_clientmgr.c:284 snd_seq_release+0x51/0xe0 sound/core/seq/seq_clientmgr.c:366 __fput+0x332/0x7f0 fs/file_table.c:208 ____fput+0x15/0x20 fs/file_table.c:244 task_work_run+0x18a/0x260 kernel/task_work.c:116 get_signal+0x148f/0x1820 kernel/signal.c:2143 do_signal+0xd2/0x2190 arch/x86/kernel/signal.c:807 exit_to_usermode_loop+0x200/0x2a0 arch/x86/entry/common.c:156 prepare_exit_to_usermode arch/x86/entry/common.c:190 [inline] syscall_return_slowpath+0x4d3/0x570 arch/x86/entry/common.c:259 entry_SYSCALL_64_fastpath+0xc0/0xc2 RIP: 0033:0x4457d9 RSP: 002b:00007f5262fedb58 EFLAGS: 00000286 ORIG_RAX: 0000000000000010 RAX: 0000000000000000 RBX: 00000000007080a8 RCX: 00000000004457d9 RDX: 0000000020001000 RSI: 000000004058534c RDI: 0000000000000005 RBP: 0000000000002250 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000286 R12: 00000000006e0310 R13: 0000000000000005 R14: 000000004058534c R15: 0000000020001000 Code: f6 0f 84 90 00 00 00 e8 02 1e 2a fe 49 8d 7e 28 48 b8 00 00 00 00 00 fc ff df 48 89 fa 48 c1 ea 03 80 3c 02 00 0f 85 1f 01 00 00 <49> 8b 46 28 49 8d 7c 24 08 48 89 fa 49 89 04 24 48 c1 ea 03 48 RIP: snd_seq_prioq_cell_out+0x11d/0x260 sound/core/seq/seq_prioq.c:231 RSP: ffff88005f7470b8 CR2: ffffc9000392ddb8 ---[ end trace cbaec69c4a9fdbfc ]--- On commit fd694aaa46c7ed811b72eb47d5eb11ce7ab3f7f1 (Jan 26).

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[alsa-devel] [PATCH] ASoC: Intel: Skylake: Report Platform ID info from NHLT
by Subhransu S. Prusty 06 Feb '17

06 Feb '17

This patch create entry in sysfs file system to report the platform_id = "pci-id-oem_id-oem_table_id-oem_revision" for board identification. Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty(a)intel.com> Signed-off-by: Sodhi, VunnyX <vunnyx.sodhi(a)intel.com> --- sound/soc/intel/skylake/skl-nhlt.c | 42 +++++++++++++++++++++++++++++++++++--- sound/soc/intel/skylake/skl.c | 5 +++++ sound/soc/intel/skylake/skl.h | 2 ++ 3 files changed, 46 insertions(+), 3 deletions(-) diff --git a/sound/soc/intel/skylake/skl-nhlt.c b/sound/soc/intel/skylake/skl-nhlt.c index 3f8e6f0b7eb5..2710a3704a38 100644 --- a/sound/soc/intel/skylake/skl-nhlt.c +++ b/sound/soc/intel/skylake/skl-nhlt.c @@ -189,9 +189,9 @@ int skl_get_dmic_geo(struct skl *skl) return dmic_geo; } -static void skl_nhlt_trim_space(struct skl *skl) +static void skl_nhlt_trim_space(char *trim) { - char *s = skl->tplg_name; + char *s = trim; int cnt; int i; @@ -218,7 +218,43 @@ int skl_nhlt_update_topology_bin(struct skl *skl) skl->pci_id, nhlt->header.oem_id, nhlt->header.oem_table_id, nhlt->header.oem_revision, "-tplg.bin"); - skl_nhlt_trim_space(skl); + skl_nhlt_trim_space(skl->tplg_name); return 0; } + +static ssize_t skl_nhlt_platform_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci = to_pci_dev(dev); + struct hdac_ext_bus *ebus = pci_get_drvdata(pci); + struct skl *skl = ebus_to_skl(ebus); + struct nhlt_acpi_table *nhlt = (struct nhlt_acpi_table *)skl->nhlt; + char platform_id[32]; + + sprintf(platform_id, "%x-%.6s-%.8s-%d", skl->pci_id, + nhlt->header.oem_id, nhlt->header.oem_table_id, + nhlt->header.oem_revision); + + skl_nhlt_trim_space(platform_id); + return sprintf(buf, "%s\n", platform_id); +} + +static DEVICE_ATTR(platform_id, 0444, skl_nhlt_platform_id_show, NULL); + +int skl_nhlt_create_sysfs(struct skl *skl) +{ + struct device *dev = &skl->pci->dev; + + if (sysfs_create_file(&dev->kobj, &dev_attr_platform_id.attr)) + dev_warn(dev, "Error creating sysfs entry\n"); + + return 0; +} + +void skl_nhlt_remove_sysfs(struct skl *skl) +{ + struct device *dev = &skl->pci->dev; + + sysfs_remove_file(&dev->kobj, &dev_attr_platform_id.attr); +} diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c index da5db5098274..1152e46daede 100644 --- a/sound/soc/intel/skylake/skl.c +++ b/sound/soc/intel/skylake/skl.c @@ -732,6 +732,10 @@ static int skl_probe(struct pci_dev *pci, goto out_display_power_off; } + err = skl_nhlt_create_sysfs(skl); + if (err < 0) + goto out_nhlt_free; + skl_nhlt_update_topology_bin(skl); pci_set_drvdata(skl->pci, ebus); @@ -852,6 +856,7 @@ static void skl_remove(struct pci_dev *pci) skl_free_dsp(skl); skl_machine_device_unregister(skl); skl_dmic_device_unregister(skl); + skl_nhlt_remove_sysfs(skl); skl_nhlt_free(skl->nhlt); skl_free(ebus); dev_set_drvdata(&pci->dev, NULL); diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h index 4986e3929dd3..0a1b02e21277 100644 --- a/sound/soc/intel/skylake/skl.h +++ b/sound/soc/intel/skylake/skl.h @@ -130,5 +130,7 @@ struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance, void skl_cleanup_resources(struct skl *skl); const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id); void skl_update_d0i3c(struct device *dev, bool enable); +int skl_nhlt_create_sysfs(struct skl *skl); +void skl_nhlt_remove_sysfs(struct skl *skl); #endif /* __SOUND_SOC_SKL_H */ -- 1.9.1

2 1

[alsa-devel] [PATCH v3 00/10] Allwinner H5 and Orange Pi PC2 support
by Icenowy Zheng 05 Feb '17

05 Feb '17

Allwinner H5 is a 64-bit SoC with a design like the 32-bit H3. This patchset adds support for it, along with the first available board -- Orange Pi PC2. Some drivers are also enabled to be built on ARM64 ARCH_SUNXI platform, in order to make the internal audio codec work. Andre Przywara (3): arm: dts: sun8i: split Allwinner H3 .dtsi arm64: dts: allwinner: add Allwinner H5 .dtsi arm64: dts: sunxi: add support for the Orange Pi PC 2 board Icenowy Zheng (7): drivers: pinctrl: add driver for Allwinner H5 SoC arm64: allwinner: Kconfig: add essential pinctrl driver for H5 clk: sunxi-ng: rename sun8i-h3 driver to sunxi-h3-h5 clk: sunxi-ng: add support for Allwinner H5 SoC clk: sunxi-ng: remove transitional headers for dt-bindings dmaengine: sun6i: allow build on ARM64 platforms (sun50i) ASoC: sunxi: allow the analog codec driver to be built on ARM64 .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + arch/arm/boot/dts/sun8i-h3.dtsi | 571 ++------------------- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 557 ++++++++++++++++++++ arch/arm64/Kconfig.platforms | 5 +- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 164 ++++++ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 139 +++++ arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi | 1 + drivers/clk/sunxi-ng/Kconfig | 6 +- drivers/clk/sunxi-ng/Makefile | 2 +- .../sunxi-ng/{ccu-sun8i-h3.c => ccu-sunxi-h3-h5.c} | 179 ++++++- .../sunxi-ng/{ccu-sun8i-h3.h => ccu-sunxi-h3-h5.h} | 15 +- drivers/dma/Kconfig | 2 +- drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 558 ++++++++++++++++++++ .../clock/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} | 11 +- .../reset/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} | 11 +- sound/soc/sunxi/Kconfig | 2 +- 20 files changed, 1662 insertions(+), 569 deletions(-) create mode 100644 arch/arm/boot/dts/sunxi-h3-h5.dtsi create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi create mode 120000 arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi rename drivers/clk/sunxi-ng/{ccu-sun8i-h3.c => ccu-sunxi-h3-h5.c} (80%) rename drivers/clk/sunxi-ng/{ccu-sun8i-h3.h => ccu-sunxi-h3-h5.h} (82%) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c rename include/dt-bindings/clock/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} (95%) rename include/dt-bindings/reset/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} (94%) -- 2.11.0

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[alsa-devel] [PATCH v5 0/4] Add support for es8388 and hdmi audio on the rock2
by Romain Perier 04 Feb '17

04 Feb '17

This set of patches adds a machine driver for rk3288-based boards that have the built-in HDMI audio and a generic analog output. It also adds slave mode to the es8328 driver that currently only supported the master mode. Then, it adds the required DT definitions to link rockchip-i2s to the es8388 analog output and to hdmi audio. This work is based on the initial work that was done by Sjoerd Simons <sjoerd.simons(a)collabora.co.uk> with some improvements, changes and more commits. Changes in v5: - Fixed coding style issue in patch 2/4 (the switch case). - Moved the code for the master mode and the slave mode into the switch case for patch 2/4 - Fixed error handling for patch 3/4 Changes in v4: - Add support for multi codecs in the asoc machine driver, so the driver matches the hw architecture (analog and hdmi audio are connected on the same i2s line) - Renamed the driver to rk3288-hdmi-analog.c and changed its documentation - Add built-in support for hdmi audio in this driver - Add support for the property 'rockchip,routing' Changes in v3: - Cosmetic changes in rockchip_es8388.c - Added missing email to MODULE_AUTHOR in rockchip_es8388.c Changes in v2: - Fixed wrong use of the data structure i2c_device_id - Fixed wrong dependencies for SND_SOC_ROCKCHIP_ES8388 Romain Perier (4): ASoC: es8328-i2c: Add compatible for ES8388 ASoC: es8328: Add support for slave mode ASoC: rockchip: Add machine driver for RK3288 boards that use analog/HDMI arm: dts: Add support for ES8388 to the Radxa Rock 2 Documentation/devicetree/bindings/sound/es8328.txt | 2 +- .../bindings/sound/rockchip,rk3288-hdmi-analog.txt | 36 +++ arch/arm/boot/dts/rk3288-rock2-square.dts | 39 +++ sound/soc/codecs/es8328-i2c.c | 2 + sound/soc/codecs/es8328.c | 20 +- sound/soc/rockchip/Kconfig | 10 + sound/soc/rockchip/Makefile | 2 + sound/soc/rockchip/rk3288_hdmi_analog.c | 299 +++++++++++++++++++++ 8 files changed, 403 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt create mode 100644 sound/soc/rockchip/rk3288_hdmi_analog.c -- 2.9.3

2 6

[alsa-devel] [PATCH v7 0/4] Add support for es8388 and hdmi audio on the rock2
by Romain Perier 04 Feb '17

04 Feb '17

This set of patches adds a machine driver for rk3288-based boards that have the built-in HDMI audio and a generic analog output. It also adds slave mode to the es8328 driver that currently only supported the master mode. Then, it adds the required DT definitions to link rockchip-i2s to the es8388 analog output and to hdmi audio. This work is based on the initial work that was done by Sjoerd Simons <sjoerd.simons(a)collabora.co.uk> with some improvements, changes and more commits. Changes in v7: - Added patch 2/4 - No longer select ES8328_I2C for RK3288_HDMI_ANALOG - Fixed DT regulator names in the DT for the Rock2 - Splitted pins for the headphone in the DT for the Rock2 Changes in v6: - Fixed bad error handling for gpio in rk3288_analog_hdmi.c - Removed message duplication in rk_hw_params(), in rk3288_analog_hdmi.c - Removed patch 1/4 (from the previous series), as it has been merged Changes in v5: - Fixed coding style issue in patch 2/4 (the switch case). - Moved the code for the master mode and the slave mode into the switch case for patch 2/4 - Fixed error handling for patch 3/4 Changes in v4: - Add support for multi codecs in the asoc machine driver, so the driver matches the hw architecture (analog and hdmi audio are connected on the same i2s line) - Renamed the driver to rk3288-hdmi-analog.c and changed its documentation - Add built-in support for hdmi audio in this driver - Add support for the property 'rockchip,routing' Changes in v3: - Cosmetic changes in rockchip_es8388.c - Added missing email to MODULE_AUTHOR in rockchip_es8388.c Changes in v2: - Fixed wrong use of the data structure i2c_device_id - Fixed wrong dependencies for SND_SOC_ROCKCHIP_ES8388 Romain Perier (4): ASoC: es8328: Add support for slave mode ASoC: Allow to select ES8328_I2C and ES8328_SPI directly ASoC: rockchip: Add machine driver for RK3288 boards that use analog/HDMI arm: dts: Add support for ES8388 to the Radxa Rock 2 .../bindings/sound/rockchip,rk3288-hdmi-analog.txt | 36 +++ arch/arm/boot/dts/rk3288-rock2-som.dtsi | 2 +- arch/arm/boot/dts/rk3288-rock2-square.dts | 42 +++ sound/soc/codecs/Kconfig | 8 +- sound/soc/codecs/es8328.c | 20 +- sound/soc/rockchip/Kconfig | 9 + sound/soc/rockchip/Makefile | 2 + sound/soc/rockchip/rk3288_hdmi_analog.c | 299 +++++++++++++++++++++ 8 files changed, 407 insertions(+), 11 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt create mode 100644 sound/soc/rockchip/rk3288_hdmi_analog.c -- 2.9.3

3 6

[alsa-devel] [PATCH 0/7] Add STM32 DFSDM support
by Arnaud Pouliquen 04 Feb '17

04 Feb '17

This patch-set handles the Digital Filter for Sigma Delta modulators IP on STM32 platforms. DFSDM IP allows PDM microphone capture and sigma delta ADC conversion. Those two features are mixed into the registers of the same hardware block which lead to introduce a multifunction driver on the top of them to be able to share the registers. for This, MFD exports an API based on get/configure/start/stop/release mechanisms. Two kind of resources are handled by the MFD driver. - The filters: - 4 instances available for L4 and H7 - composed with a SInC filter and an integrator - The transceivers or channels - 8 instances available for L4 and H7 - can be connected to serial transceivers (SPI or Manchester mode) internal parallel transceivers (from memory or internal ADC) - associated monitoring: analog watchdog, short circuit detector, extreme detector (monitoring support will be part of a specific patch-set)) Principle OF the DFSDM IP is to connect one or several channels to a filter to process Sigma delta ADC or PDM microphone data. Two types of child devices can de declared: IIO for the management of Sigma Delta ADC conversion. ASoC for PDM microphone audio capture. For details on IP and use case examples please refer to this document: http://www.st.com/content/ccc/resource/training/technical/product_training/… Remark: For audio part a patch is proposed to update core part to add copy support in soc_dmaengine_pcm. Rational is that output data register in DFSDM contains audio sample on 24 MSB + channel ID on the 8 LSB. Proposal is to allow to register a copy ops in soc_dmaengine_pcm to be able to perform post-processing. Back up if not accepted can be to create a pcm_engine in stm32 driver. Not part of this patch-set, but should come as add-on patches: - IIO management of Analog watchdog, short-circuit detection and clock absence detector, with associated IRQs management. - IIO trigger and buffer management. Arnaud Pouliquen (6): MFD: add bindings for STM32 DFSDM driver MFD: add STM32 DFSDM support IIO: add bindings for STM32 DFSDM ADC driver IIO: add STM32 DFSDM ADC support ASoC: add bindings for STM32 DFSDM driver ASoC: add STM32 DFSDM support olivier moysan (1): ASoC: dmaengine_pcm: add copy support .../bindings/iio/adc/st,stm32-dfsdm-adc.txt | 60 ++ .../devicetree/bindings/mfd/stm32-dfsdm.txt | 68 ++ .../devicetree/bindings/sound/st,sm32-adfsdm.txt | 84 ++ drivers/iio/adc/Kconfig | 9 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/stm32-dfsdm-adc.c | 676 +++++++++++++ drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 2 + drivers/mfd/stm32-dfsdm-reg.h | 220 +++++ drivers/mfd/stm32-dfsdm.c | 1044 ++++++++++++++++++++ include/linux/mfd/stm32-dfsdm.h | 324 ++++++ include/sound/dmaengine_pcm.h | 3 + sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/soc-generic-dmaengine-pcm.c | 37 +- sound/soc/stm/Kconfig | 10 + sound/soc/stm/Makefile | 2 + sound/soc/stm/stm32_adfsdm.c | 686 +++++++++++++ 18 files changed, 3237 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt create mode 100644 Documentation/devicetree/bindings/mfd/stm32-dfsdm.txt create mode 100644 Documentation/devicetree/bindings/sound/st,sm32-adfsdm.txt create mode 100644 drivers/iio/adc/stm32-dfsdm-adc.c create mode 100644 drivers/mfd/stm32-dfsdm-reg.h create mode 100644 drivers/mfd/stm32-dfsdm.c create mode 100644 include/linux/mfd/stm32-dfsdm.h create mode 100644 sound/soc/stm/Kconfig create mode 100644 sound/soc/stm/Makefile create mode 100644 sound/soc/stm/stm32_adfsdm.c -- 1.9.1

7 42

[alsa-devel] [PATCH v2 00/10] Add sun8i A33 audio driver
by Mylène Josserand 03 Feb '17

03 Feb '17

Hello everyone, This a V2 of my Allwinner A33 (sun8i) audio codec driver. Tested on linux-next-20170105 tag with one remaining patch from Chen-Yu's series: http://lkml.iu.edu/hypermail/linux/kernel/1611.3/01256.html Patch to apply before this serie: https://patchwork.kernel.org/patch/9423999/ Changes since V1: - Remove the analog codec driver as a better version has been committed by Chen-Yu Tsai and is already merged. - Remove the audio-card as simple-card can be used - The DMA maxburst is set to 8 in the sun4i-i2s instead of adding the maxburst of 4 in Sun6i dma engine. - Create a new compatible for sun4i-i2s to handle the reset line. - Fix various problems in sun8i-codec driver according to V1's reviews - Add the pm_runtime hooks in sun8i-codec driver to prepare/ unprepare clocks. - Update the DTS according to Chen-Yu's analog codec driver. - Rename sun8i-codec's clocks to "bus" and "mod" - The first "delay" issue from V1 is fixed by using a delay when enabling the headphone amplifier to let the amplifier being up. Patch 1 increases the DMA maxburst value of sun4i-i2s to 8. See Chen-Yu's commit log for more details: https://patchwork.kernel.org/patch/9411805/ Patch 2 adds the CLK_SET_RATE_PARENT flag to ccu sun8i-a33 clocks. Patches 3 and 4 add a new compatible "allwinner,sun6i-a31-i2s" to handle the reset line for sun4i-i2s driver. It uses a quirk to use a version with or without reset lines. Patch 5 adds the sun8i codec driver which represents the digital part of the A33 codec. It supports only playback features. Path 6 fixes the previous issue of a "first time delay" in V1 (see cover letter). Do not hesitate if you have comments on this patch. Patches 7 adds the dt-bindings documentation for new audio driver added in this serie (sun8i-codec). Patch 8 adds the cpu DAI, codec and audio nodes to sun8i-a33 device tree. Patches 9 and 10 enable the audio on Parrot and Sinlinx's boards. The DAI for this A33 codec is the same than for A20: "sun4i-i2s". Currently, all the drivers handle only the playback feature. The other ones (such as capture) and all other interfaces except headphone are not supported. I will send a patch to handle the capture with microphones in next few weeks. Examples of amixer commands: amixer set 'Headphone' 75% amixer set 'Headphone' on amixer set 'DAC' on amixer set 'Right DAC Mixer RSlot 0' on amixer set 'Left DAC Mixer LSlot 0' on It was tested on Parrot and Sinlinx boards. Let me know if you have any comments on this serie. Thank you in advance, Best regards, Mylène Josserand (10): ASoC: sun4i-i2s: Increase DMA max burst to 8 clk: ccu-sun8i-a33: Add CLK_SET_RATE_PARENT to ac-dig dt-bindings: sound: Add new reset compatible for sun4i-i2s ASoC: sun4i-i2s: Add quirks to handle new compatible for reset ASoC: Add sun8i digital audio codec ASoC: sun8i-codec-analog: Add amplifier event to fix first delay dt-bindings: sound: Add sun8i audio documentation ARM: dts: sun8i: Add audio codec, dai and card for A33 ARM: dts: sun8i: parrot: Enable audio nodes ARM: dts: sun8i: sinlinx: Enable audio nodes .../devicetree/bindings/sound/sun4i-i2s.txt | 23 + .../devicetree/bindings/sound/sun8i-codec.txt | 76 +++ arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 8 + arch/arm/boot/dts/sun8i-a33.dtsi | 47 ++ arch/arm/boot/dts/sun8i-r16-parrot.dts | 8 + drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +- sound/soc/sunxi/Kconfig | 11 + sound/soc/sunxi/Makefile | 1 + sound/soc/sunxi/sun4i-i2s.c | 61 ++- sound/soc/sunxi/sun8i-codec-analog.c | 30 +- sound/soc/sunxi/sun8i-codec.c | 531 +++++++++++++++++++++ 11 files changed, 791 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/sun8i-codec.txt create mode 100644 sound/soc/sunxi/sun8i-codec.c -- 2.11.0

3 24

[alsa-devel] [PATCH v4 2/2] ASoc: Add devictree bindings for CS35L35 CODEC
by Brian Austin 02 Feb '17

02 Feb '17

Add devicetree bindings documentatin for Cirrus Logic CS35L35 Boosted Amplifier Signed-off-by: Brian Austin <brian.austin(a)cirrus.com> --- .../devicetree/bindings/sound/cs35l35.txt | 171 +++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cs35l35.txt diff --git a/Documentation/devicetree/bindings/sound/cs35l35.txt b/Documentation/devicetree/bindings/sound/cs35l35.txt new file mode 100644 index 0000000..8a93b1b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs35l35.txt @@ -0,0 +1,171 @@ +CS35L35 Speaker Amplifier + +Required properties: + + - compatible : "cirrus,cs35l35" + + - reg : the I2C address of the device for I2C + + - VA-supply, VP-supply : power supplies for the device, + as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + + - interrupt-parent : Specifies the phandle of the interrupt controller to + which the IRQs from CS35L35 are delivered to. + - interrupts : IRQ line info CS35L35. + (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + for further information relating to interrupt properties) + +Optional properties: + - reset-gpios : gpio used to reset the amplifier + + - cirrus,stereo-config : Boolean to determine if there are 2 AMPs for a + Stereo configuration + + - cirrus,audio-channel : Set Location of Audio Signal on Serial Port + 0 = Data Packet received on Left I2S Channel + 1 = Data Packet received on Right I2S Channel + + - cirrus,advisory-channel : Set Location of Advisory Signal on Serial Port + 0 = Data Packet received on Left I2S Channel + 1 = Data Packet received on Right I2S Channel + + - cirrus,shared-boost : Boolean to enable ClassH tracking of Advisory Signal + if 2 Devices share Boost BST_CTL + + - cirrus,sp-drv-strength : Value for setting the Serial Port drive strength + Table 3-10 of the datasheet lists drive-strength specifications + 0 = 1x (Default) + 1 = .5x + + - cirrus,bst-pdn-fet-on : Boolean to determine if the Boost PDN control + powers down with a rectification FET On or Off. If VSPK is supplied + externally then FET is off. + + - cirrus,boost-ctl : Boost Converter control word. + Step Size: 100 + 0x00 = (Default) VP + Range is 0x01...0x41 + + - cirrus,boost-ipk : Boost-converter peak current limit. + Configures the peak current by monitoring the current through the boost FET. + Step size: 112 + 0x07 = (Default) 2.46 Amps + Range is 0x00...0x19 + + - cirrus,amp-gain-zc : Boolean to determine if to use Amplifier gain-change + zero-cross + +Optional H/G Algorithm sub-node: + + The cs35l35 node can have a single "cirrus,classh-internal-algo" sub-node + that will disable automatic control of the internal H/G Algorithm. + + It is strongly recommended that the Datasheet be referenced when adjusting + or using these Class H Algorithm controls over the internal Algorithm. + Serious damage can occur to the Device and surrounding components. + + - cirrus,classh-internal-algo : Sub-node for the Internal Class H Algorithm + See Section 4.3 Internal Class H Algorithm in the Datasheet. + If not used, the device manages the ClassH Algorithm internally. + +Optional properties for the "cirrus,classh-internal-algo" Sub-node + + Section 7.29 Class H Control + - cirrus,classh-bst-overide : Boolean + - cirrus,classh-bst-max-limit + - cirrus,classh-mem-depth + + Section 7.30 Class H Headroom Control + - cirrus,classh-headroom + + Section 7.31 Class H Release Rate + - cirrus,classh-release-rate + + Section 7.32 Class H Weak FET Drive Control + - cirrus,classh-wk-fet-disable + - cirrus,classh-wk-fet-delay + - cirrus,classh-wk-fet-thld + + Section 7.34 Class H VP Control + - cirrus,classh-vpch-auto + - cirrus,classh-vpch-rate + - cirrus,classh-vpch-man + +Optional Monitor Signal Format sub-node: + + The cs35l35 node can have a single "cirrus,monitor-signal-format" sub-node + for adjusting the Depth, Location and Frame of the Monitoring Signals + for Algorithms. + + See Sections 4.8.2 through 4.8.4 Serial-Port Control in the Datasheet + + -cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formating + on the I2S Port. Each of the 3 8 bit values in the array contain the settings + for depth, location, and frame. + + If not used, the defaults for the 6 monitor signals is used. + + Sections 7.44 - 7.53 lists values for the depth, location, and frame + for each monitoring signal. + + - cirrus,imon : 3 8 bit values to set the depth, location, and frame + of the IMON monitor signal. + + - cirrus,vmon : 3 8 bit values to set the depth, location, and frame + of the VMON monitor signal. + + - cirrus,vpmon : 3 8 bit values to set the depth, location, and frame + of the VPMON monitor signal. + + - cirrus,vbstmon : 3 8 bit values to set the depth, location, and frame + of the VBSTMON monitor signal + + - cirrus,vpbrstat : 3 8 bit values to set the depth, location, and frame + of the VPBRSTAT monitor signal + + - cirrus,zerofill : 3 8 bit values to set the depth, location, and frame\ + of the ZEROFILL packet in the monitor signal + +Example: + +cs35l35: cs35l35@20 { + compatible = "cirrus,cs35l35"; + reg = <0x20>; + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + reset-gpios = <&axi_gpio 54 0>; + interrupt-parent = <&gpio8>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + cirrus,boost-ctl = <0x41>; + + cirrus,stereo-config; + cirrus,audio-channel = <0x00>; + cirrus,advisory-channel = <0x01>; + cirrus,shared-boost; + + cirrus,classh-internal-algo { + cirrus,classh-bst-overide; + cirrus,classh-bst-max-limit = <0x01>; + cirrus,classh-mem-depth = <0x01>; + cirrus,classh-release-rate = <0x08>; + cirrus,classh-headroom-millivolt = <0x0B>; + cirrus,classh-wk-fet-disable = <0x01>; + cirrus,classh-wk-fet-delay = <0x04>; + cirrus,classh-wk-fet-thld = <0x01>; + cirrus,classh-vpch-auto = <0x01>; + cirrus,classh-vpch-rate = <0x02>; + cirrus,classh-vpch-man = <0x05>; + }; + + /* Depth, Location, Frame */ + cirrus,monitor-signal-format { + cirrus,imon = /bits/ 8 <0x03 0x00 0x01>; + cirrus,vmon = /bits/ 8 <0x03 0x00 0x00>; + cirrus,vpmon = /bits/ 8 <0x03 0x04 0x00>; + cirrus,vbstmon = /bits/ 8 <0x03 0x04 0x01>; + cirrus,vpbrstat = /bits/ 8 <0x00 0x04 0x00>; + cirrus,zerofill = /bits/ 8 <0x00 0x00 0x00>; + }; + +}; -- 1.9.1

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