July 2016 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [PATCH 0/2] ASoC: Extended SPDIF support to Allwinner A31 SoCs
by codekipper＠gmail.com 22 Aug '16

22 Aug '16

From: Marcus Cooper <codekipper(a)gmail.com> This patch set extends the current support of the Allwinner SPDIF transceiver to include the A31 SoC. For now just the SPDIF transmitter has been tested on the Mele I7. In order for this patch set to be functional then we require changes to the clocks and the device tree. For those that are interested I've pushed all the required patches here https://github.com/codekipper/linux-sunxi/commits/a31-spdif Thanks in advance, CK Marcus Cooper (2): ASoC: sunxi: Add bindings for sun6i to SPDIF ASoC: sunxi: compatibility for sun6i to SPDIF .../devicetree/bindings/sound/sunxi,sun4i-spdif.txt | 3 +++ sound/soc/sunxi/sun4i-spdif.c | 17 ++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) -- 2.9.2

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[alsa-devel] [PATCH v1 00/14] clk/mfd/ASoC/ARM: OMAP4/5: McPDM/twl6040 pdmclk support
by Peter Ujfalusi 15 Aug '16

15 Aug '16

Hi, Changes since v1: - Added Rob's Acked-by to patch 5 and 14 - Check the return value of clk_prepare_enable() calls in the last patch this is something I wanted to do for a long time... First of all: sorry for the cross domain series. I did tested alone all the domain patches and they are not causing any regression. When they come together we will have ability to control the pdmclk needed by McPDM. CLK patches: The driver was w/o DT support and needed some cleanup so we can use the driver. I have also renamed it to twl6040-pdmclk from twl6040-clk to be precise. MFD patches: The regmap_sync() was not working since the twl6040 does not support bulk access and now we are going to create the needed child for the pdmclk. ARM patches: Updatding the board DTS files and add the needed lines for the pdmclk. ASoC patches: The machine driver needs to select the twl6040-clk driver as it will be used by the omap-mcpdm. I needed to do some cleanup and add also suspend/resume support before adding the code for pdmclk handling since I don't want to keep the twl6040 powered on when the board is suspended. At the moment it is not possible to do true dynamic twl6040 power up/down due to pop noises, but I will be looking at that later. The driver in the future will fail if it is not able to get the pdmclk to avoid kernel crash (McPDM registers are not accessible when pdmclk is not available). I have tested the patches by domain and also in all (I hope) permutation they could be. I have not experienced any regression. Regards, Peter --- Peter Ujfalusi (14): clk: twl6040: Correct clk_ops clk: twl6040: Register the clock as of_clk_provider clk: twl6040: Rename the driver and use consistent names in the code mfd: twl6040: The chip does not support bulk access mfd: twl6040: Register child device for twl6040-pdmclk ARM: dts: omap5-board-common: Add pdmclk binding for audio ARM: dts: omap4-panda-common: Add pdmclk binding for audio ARM: dts: omap4-sdp: Add pdmclk binding for audio ARM: dts: omap4-var-som-om44: Add pdmclk binding for audio ARM: dts: omap4-duovero: Add pdmclk binding for audio ASoC: omap: Kconfig: SND_OMAP_SOC_OMAP_ABE_TWL6040 to select CLK_TWL6040 ASoC: omap-mcpdm: Move the WD enable write inside omap_mcpdm_open_streams() ASoC: omap-mcpdm: Support for suspend resume ASoC: omap-mcpdm: Add support for pdmclk clock handling Documentation/devicetree/bindings/mfd/twl6040.txt | 1 + .../devicetree/bindings/sound/omap-mcpdm.txt | 10 +++ arch/arm/boot/dts/omap4-duovero.dtsi | 5 ++ arch/arm/boot/dts/omap4-panda-common.dtsi | 5 ++ arch/arm/boot/dts/omap4-sdp.dts | 5 ++ arch/arm/boot/dts/omap4-var-som-om44.dtsi | 5 ++ arch/arm/boot/dts/omap5-board-common.dtsi | 5 ++ drivers/clk/clk-twl6040.c | 80 ++++++++++++--------- drivers/mfd/twl6040.c | 6 ++ include/linux/mfd/twl6040.h | 2 +- sound/soc/omap/Kconfig | 1 + sound/soc/omap/omap-mcpdm.c | 84 ++++++++++++++++++++-- 12 files changed, 170 insertions(+), 39 deletions(-) -- 2.8.3

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[alsa-devel] [PATCH v2 0/2] ASoC: Extended SPDIF support to Allwinner A31 SoCs
by codekipper＠gmail.com 12 Aug '16

12 Aug '16

From: Marcus Cooper <codekipper(a)gmail.com> This patch set extends the current support of the Allwinner SPDIF transceiver to include the A31 SoC. For now just the SPDIF transmitter has been tested on the Mele I7. In order for this patch set to be functional then we require changes to the clocks and the device tree. For those that are interested I've pushed all the required patches here https://github.com/codekipper/linux-sunxi/commits/a31-spdif Thanks in advance, CK --- Changes since v1: - Corrected mistake in bindings documentation Marcus Cooper (2): ASoC: sunxi: Add bindings for sun6i to SPDIF ASoC: sunxi: compatibility for sun6i to SPDIF .../devicetree/bindings/sound/sunxi,sun4i-spdif.txt | 3 +++ sound/soc/sunxi/sun4i-spdif.c | 17 ++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) -- 2.9.2

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Re: [alsa-devel] SND_PCM_STREAM_CAPTURE and SND_PCM_NONBLOCK producing strange artifacts
by Takashi Iwai 11 Aug '16

11 Aug '16

Please don't drop Cc to ML. Also avoid top-post. On Tue, 05 Jul 2016 09:02:12 +0200, Trent Reed wrote: > > Thanks Takashi, > > My implementation does only use the "hw:N" devices, unfortunately - I am > not using MMAP because I was under the impression that you must poll when > directly accessing the hardware. And yes, 48kHz is the exact rate I'm > attempting. :( > I do have an update, though - I'm able to reproduce the issue quite simply > by running the ALSA test application latency with the following command: > > `latency -P <playback-device> -C <capture-device> -r 48000` > > This, as far as I understand from the source code, should open R/W > interleaved streams on ("hw:2" is what I'm using for both, though the > problem persists in non-duplex mode, e.g. "hw:2" "hw:0") in non-blocking > mode without polling. > > What happens is the latency application does normalize around some value > (say, 16ms roundtrip time), but the audio is awful and broken, a lot of > this "static" I'm talking about. It seems to me that it's the same problem > that I have in my above-mentioned sample code. > > I would love to help more, so if I can in any way, please let me know! But > I feel at a loss for how to further debug. The latency program is too complex to analyze the issue. Check arecord with --nonblock --test-nowait options and with the hw device. Does the issue happen always? Or does it depend on the buffer or period size? Takashi > > Thanks, > - Trent Reed > > On Mon, Jul 4, 2016 at 11:52 PM, Takashi Iwai <tiwai(a)suse.de> wrote: > > > On Sat, 02 Jul 2016 23:58:28 +0200, > > Trent Reed wrote: > > > > > > (Ping) > > > > > > I'm afraid I still don't understand why this is failing. I found that a > > > call to sdn_pcm_wait() when -EAGAIN is returned fixes the problem because > > > it waits for samples to be ready, but I don't understand why it is a > > > problem in the first place. Much of the sample code is written in a way > > > that suggests that the call to snd_pcm_wait() is optional, and only > > > required when directly reading/writing from the device (MMAP, I'm not > > doing > > > this). > > > > > > I'm just wondering what is wrong with basically looping over a call to > > > snd_pcm_readi() in non-blocking mode, reacting to errors, and capturing > > > frames. This produces awful static (which is basically garbage samples), > > is > > > it a requirement that I call snd_pcm_wait() when -EAGAIN is passed back > > to > > > wait for a full period to be ready? > > > > Well, in the API level, it should work as you expected. So there must > > be definitely some bug(s). But it's hard to spot out, as there are > > several layers behind the scene. > > > > As a first shot, try to reproduce without alsa-lib plugins, i.e. only > > with "hw" PCM device, if not done yet. Also, it's interesting to see > > whether it happens with or without mmap r/w. > > > > Another point is whether it depends on the parameter. Did you try > > 48kHz instead of 44.1kHz? > > > > > > Takashi > > > > > > > > > > Thanks, > > > - Trent Reed > > > > > > > > > On Tue, Jun 28, 2016 at 7:27 PM, Trent Reed <treed0803(a)gmail.com> wrote: > > > > > > > Hey All, > > > > > > > > I've been banging my head against the wall for about a week on this > > bug. > > > > The following gist shows my sample reproduction code: > > > > https://gist.github.com/TReed0803/985c5d5c3d295245e19006a27be447c3 > > > > > > > > I'm simply opening up a non-blocking PCM capture stream and writing the > > > > contents of the reads to stdout. > > > > (Originally, I was writing to the playback stream, but I was hearing > > this > > > > strange static occasionally!) > > > > > > > > It's the static I'm trying to debug. It doesn't happen every time. In > > > > fact, sometimes I'll go a few consecutive executions without hearing > > it. > > > > I was able to capture some of the bad data, and I loaded it up in > > Audacity > > > > for visualization: > > > > > > > > > > https://drive.google.com/file/d/0B-1aumGKQcQTcUJoZzIwRWhYSFE/view?usp=shari… > > > > > > > > It looks like the internal buffer occasionally is sending me more data > > > > than it actually captured, and I end up either reading old PCM data > > from > > > > the internal ring buffer, or (at the very beginning) a bunch of zeros. > > > > > > > > Can anyone help me understand what is going on? What could cause these > > > > definitely incorrect samples to be recorded? (I get the same effect > > > > regardless of hardware, but I will list hardware just in case.) > > > > > > > > I hope I have all the information you might need: > > > > Hardware: Samson Meteor Mic (USB-Audio, USB Mixer) [Though, it even > > > > happens with my built-in microphone] > > > > ALSA version: Advanced Linux Sound Architecture Driver Version > > > > k4.4.0-28-generic. > > > > apt-cache policy (installed alsa-lib version): 1.1.0-0ubuntu1 > > > > > > > > Thanks, > > > > - Trent Reed > > > > > > > _______________________________________________ > > > Alsa-devel mailing list > > > Alsa-devel(a)alsa-project.org > > > http://mailman.alsa-project.org/mailman/listinfo/alsa-devel > > >

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[alsa-devel] [PATCH] ASoC: rt5659: Add mclk controls
by Nicolin Chen 11 Aug '16

11 Aug '16

The codec driver should control the mclk. So this patch adds this support. Signed-off-by: Nicolin Chen <nicoleotsuka(a)gmail.com> --- Documentation/devicetree/bindings/sound/rt5659.txt | 3 +++ sound/soc/codecs/rt5659.c | 24 ++++++++++++++++++++++ sound/soc/codecs/rt5659.h | 1 + 3 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/rt5659.txt b/Documentation/devicetree/bindings/sound/rt5659.txt index 5f79e7f..1766e05 100644 --- a/Documentation/devicetree/bindings/sound/rt5659.txt +++ b/Documentation/devicetree/bindings/sound/rt5659.txt @@ -12,6 +12,9 @@ Required properties: Optional properties: +- clocks: The phandle of the master clock to the CODEC +- clock-names: Should be "mclk" + - realtek,in1-differential - realtek,in3-differential - realtek,in4-differential diff --git a/sound/soc/codecs/rt5659.c b/sound/soc/codecs/rt5659.c index 1b30914..d9ead96 100644 --- a/sound/soc/codecs/rt5659.c +++ b/sound/soc/codecs/rt5659.c @@ -9,6 +9,7 @@ * published by the Free Software Foundation. */ +#include <linux/clk.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/init.h> @@ -3565,7 +3566,9 @@ static int rt5659_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) static int rt5659_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec); + int ret; switch (level) { case SND_SOC_BIAS_PREPARE: @@ -3582,6 +3585,17 @@ static int rt5659_set_bias_level(struct snd_soc_codec *codec, RT5659_PWR_FV1 | RT5659_PWR_FV2); break; + case SND_SOC_BIAS_STANDBY: + if (dapm->bias_level == SND_SOC_BIAS_OFF) { + ret = clk_prepare_enable(rt5659->mclk); + if (ret) { + dev_err(codec->dev, + "failed to enable MCLK: %d\n", ret); + return ret; + } + } + break; + case SND_SOC_BIAS_OFF: regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1, RT5659_PWR_LDO, 0); @@ -3591,6 +3605,7 @@ static int rt5659_set_bias_level(struct snd_soc_codec *codec, RT5659_PWR_MB | RT5659_PWR_VREF2); regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC, RT5659_DIG_GATE_CTRL, 0); + clk_disable_unprepare(rt5659->mclk); break; default: @@ -4020,6 +4035,15 @@ static int rt5659_i2c_probe(struct i2c_client *i2c, regmap_write(rt5659->regmap, RT5659_RESET, 0); + /* Check if MCLK provided */ + rt5659->mclk = devm_clk_get(&i2c->dev, "mclk"); + if (IS_ERR(rt5659->mclk)) { + if (PTR_ERR(rt5659->mclk) == -EPROBE_DEFER) + return -EPROBE_DEFER; + /* Otherwise mark the mclk pointer to NULL */ + rt5659->mclk = NULL; + } + rt5659_calibrate(rt5659); /* line in diff mode*/ diff --git a/sound/soc/codecs/rt5659.h b/sound/soc/codecs/rt5659.h index d31c9e5..d69b0eb 100644 --- a/sound/soc/codecs/rt5659.h +++ b/sound/soc/codecs/rt5659.h @@ -1796,6 +1796,7 @@ struct rt5659_priv { struct gpio_desc *gpiod_reset; struct snd_soc_jack *hs_jack; struct delayed_work jack_detect_work; + struct clk *mclk; int sysclk; int sysclk_src; -- 2.1.4

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[alsa-devel] [PATCH 00/49] ASoC: add simple-card-core and standardize "simple" card
by Kuninori Morimoto 10 Aug '16

10 Aug '16

Hi Mark These are very big patch-set, but basically just cleanup for simple-card driver. Now, we have simple-card driver, but it is not simple today. I would like to cleanup this. And Renesas already have rsrc-card driver which is supporting DPCM, and it is based on simple-card. This measn rsrc-card and simple-card are very similar. Thus, I would like to share these code between rsrc-card and simple-card. This rsrc-card is only used from Renesas (actually, there is no upstream user, current user is only me, by local). But this is not Renesas special driver, I can say it is DPCM version of simple-card. I would like to open it for all of ALSA people. But, not merge simple-card <-> rsrc-card, to avoid diffcult future maintenance. Thus, rsrc-card will be simple-dpcm-audio-card, and we can maintenance both simple-card, and simple-dpcm-card. I'm not sure this is good nameing. And finally, we will need HDMI sound support which uses graph base probing. I know it needs more discussion with V4L2 people. But in my understanding, basically, we can reuse simple-card base feature/function on graph base driver somehow. I would like to standardize simple card style, and use/share it with graph driver too. It will be simple-graph-card ? I'm not sure. But I think we can share same code, and can avoid development from 0. These patch are for it. Basically, it pickups common function/feature from simple-card and rsrc-card, and standardize each feature/parse/init etc in simple-card-core. Because of this patch-set, "simple-card" become "simple" again :) I tested these (simple-card, rsrc-card) on my lager, Salvator boards. But I couldn't test some feature. I hope test it on many environment. 1) - 4) cleanup for these patch-set 5) - 19) pickuped common function/feature and put it to simple-card-core 20) - 32) use simple-card-core on simple-card 33) - 46) use simple-card-core on rsrc-card 47) - 49) rename rsrc-card to simple-dpcm-audio-card Kuninori Morimoto (49): 1) ASoC: simple-card: remove duplicate header 2) ASoC: rsrc-card: remove duplicate header 3) ASoC: rsrc-card: remove unused dai_num 4) ASoC: simple-card: platform also uses asoc_simple_card_sub_parse_of() 5) ASoC: add new simple-card-core.c 6) ASoC: simple-card-core: add asoc_simple_card_parse_tdm() 7) ASoC: simple-card-core: add asoc_simple_card_parse_dailink_name() 8) ASoC: simple-card-core: add asoc_simple_card_parse_card_name() 9) ASoC: simple-card-core: add asoc_simple_card_parse_card_prefix() 10) ASoC: simple-card-core: add asoc_simple_card_parse_card_widgets() 11) ASoC: simple-card-core: add asoc_simple_card_parse_card_widgets() 12) ASoC: simple-card-core: add asoc_simple_card_parse_clk() 13) ASoC: simple-card-core: add asoc_simple_card_parse_endpoint() 14) ASoC: simple-card-core: add asoc_simple_card_parse_dpcm() 15) ASoC: simple-card-core: add asoc_simple_card_init_jack() 16) ASoC: simple-card-core: add asoc_simple_card_init_dai() 17) ASoC: simple-card-core: add asoc_simple_card_canonicalize_dailink() 18) ASoC: simple-card-core: add asoc_simple_card_canonicalize_cpu() 19) ASoC: simple-card-core: add asoc_simple_card_clean_reference() 20) ASoC: simple-card: use asoc_simple_card_parse_daifmt() 21) ASoC: simple-card: use asoc_simple_card_parse_clk() 22) ASoC: simple-card: use asoc_simple_card_parse_endpoint() 23) ASoC: simple-card: use asoc_simple_card_parse_tdm() 24) ASoC: simple-card: use asoc_simple_card_parse_card_name() 25) ASoC: simple-card: use asoc_simple_card_parse_card_route() 26) ASoC: simple-card: use asoc_simple_card_parse_card_widgets() 27) ASoC: simple-card: use asoc_simple_card_parse_dailink_name() 28) ASoC: simple-card: use asoc_simple_card_init_jack() 29) ASoC: simple-card: use asoc_simple_card_init_dai() 30) ASoC: simple-card: use asoc_simple_card_canonicalize_dailink() 31) ASoC: simple-card: use asoc_simple_card_canonicalize_cpu() 32) ASoC: simple-card: use asoc_simple_card_clean_reference() 33) ASoC: rsrc-card: use asoc_simple_card_parse_daifmt() 34) ASoC: rsrc-card: use asoc_simple_card_parse_dailink_name() 35) ASoC: rsrc-card: use asoc_simple_dai instead of rsrc_card_dai 36) ASoC: rsrc-card: use asoc_simple_card_parse_clk() 37) ASoC: rsrc-card: use asoc_simple_card_parse_endpoint() 38) ASoC: rsrc-card: use asoc_simple_card_parse_card_name() 39) ASoC: rsrc-card: use asoc_simple_card_parse_card_prefix() 40) ASoC: rsrc-card: use asoc_simple_card_parse_dpcm() 41) ASoC: rsrc-card: use asoc_simple_card_parse_card_route() 42) ASoC: rsrc-card: use asoc_simple_card_parse_tdm() 43) ASoC: rsrc-card: use asoc_simple_card_init_dai() 44) ASoC: rsrc-card: use asoc_simple_card_canonicalize_cpu() 45) ASoC: rsrc-card: use asoc_simple_card_canonicalize_dailink() 46) ASoC: rsrc-card: use asoc_simple_card_clean_reference() 47) ASoC: rsrc-card: rename rsrc-card to simple-dpcm-card phase1 48) ASoC: rsrc-card: rename rsrc-card to simple-dpcm-card phase2 49) ASoC: rsrc-card: rename rsrc-card to simple-dpcm-card phase3 Documentation/devicetree/bindings/sound/renesas,rsrc-card.txt | 75 -------------- Documentation/devicetree/bindings/sound/simple-dpcm-card.txt | 79 +++++++++++++++ include/sound/simple_card.h | 11 +-- include/sound/simple_card_core.h | 106 ++++++++++++++++++++ sound/soc/generic/Kconfig | 10 ++ sound/soc/generic/Makefile | 4 + sound/soc/generic/simple-card-core.c | 409 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ sound/soc/generic/simple-card.c | 359 ++++++++++++------------------------------------------------------ sound/soc/generic/simple-dpcm-card.c | 330 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ sound/soc/sh/Kconfig | 5 - sound/soc/sh/rcar/Makefile | 3 - sound/soc/sh/rcar/rsrc-card.c | 529 -------------------------------------------------------------------------------------------------- 12 files changed, 999 insertions(+), 921 deletions(-)

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[alsa-devel] [PATCH v4 2/4] mfd: Add Samsung Exynos Low Power Audio Subsystem driver
by Sylwester Nawrocki 10 Aug '16

10 Aug '16

This patch adds common driver for the Top block of the Samsung Exynos SoC Low Power Audio Subsystem. This is a minimal driver which prepares resources for IP blocks like I2S, audio DMA and UART and exposes a regmap for the Top block registers. Also system power ops are added to ensure the Audio Subsystem is operational after system suspend/resume cycle. Signed-off-by: Inha Song <ideal.song(a)samsung.com> Signed-off-by: Beomho Seo <beomho.seo(a)samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki(a)samsung.com> --- Changes since v3: - moved from sound/soc/samsung and rewritten as a MFD driver, - PMU register definitions moved to include/linux/mfd/syscon/exynos5-pmu.h, - added regmap for LPASS Top SFR region, - cleaned up register bit field defintions. Changes since v2: - move misplaced SND_SAMSUNG_AUDSS Kconfig symbol addition to this patch. --- drivers/mfd/Kconfig | 8 ++ drivers/mfd/Makefile | 1 + drivers/mfd/exynos-lpass.c | 185 +++++++++++++++++++++++++++++++++ include/linux/mfd/syscon/exynos5-pmu.h | 4 +- 4 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 drivers/mfd/exynos-lpass.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 1bcf601..fc2dffb 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -270,6 +270,14 @@ config MFD_DLN2 etc. must be enabled in order to use the functionality of the device. +config MFD_EXYNOS_LPASS + tristate "Samsung Exynos SoC Low Power Audio Subsystem" + select MFD_CORE + select REGMAP_MMIO + help + Select this option to enable support for Samsung Exynos Low Power + Audio Subsystem. + config MFD_MC13XXX tristate depends on (SPI_MASTER || I2C) diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 42a66e1..5c4be31 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o obj-$(CONFIG_MFD_CROS_EC) += cros_ec.o obj-$(CONFIG_MFD_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_MFD_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_MFD_EXYNOS_LPASS) += exynos-lpass.o rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o obj-$(CONFIG_MFD_RTSX_PCI) += rtsx_pci.o diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c new file mode 100644 index 0000000..956ce1f --- /dev/null +++ b/drivers/mfd/exynos-lpass.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd. + * + * Authors: Inha Song <ideal.song(a)samsung.com> + * Sylwester Nawrocki <s.nawrocki(a)samsung.com> + * + * Samsung Exynos SoC series Low Power Audio Subsystem driver. + * + * This module provides regmap for the Top SFR region and instantiates + * devices for IP blocks like DMAC, I2S, UART. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/exynos5-pmu.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/types.h> + +/* LPASS Top register definitions */ +#define SFR_LPASS_CORE_SW_RESET (0x08) +#define LPASS_SB_SW_RESET (1 << 11) +#define LPASS_UART_SW_RESET (1 << 10) +#define LPASS_PCM_SW_RESET (1 << 9) +#define LPASS_I2S_SW_RESET (1 << 8) +#define LPASS_WDT1_SW_RESET (1 << 4) +#define LPASS_WDT0_SW_RESET (1 << 3) +#define LPASS_TIMER_SW_RESET (1 << 2) +#define LPASS_MEM_SW_RESET (1 << 1) +#define LPASS_DMA_SW_RESET (1 << 0) + +#define SFR_LPASS_INTR_CA5_MASK (0x48) +#define SFR_LPASS_INTR_CPU_MASK (0x58) +#define LPASS_INTR_APM (1 << 9) +#define LPASS_INTR_MIF (1 << 8) +#define LPASS_INTR_TIMER (1 << 7) +#define LPASS_INTR_DMA (1 << 6) +#define LPASS_INTR_GPIO (1 << 5) +#define LPASS_INTR_I2S (1 << 4) +#define LPASS_INTR_PCM (1 << 3) +#define LPASS_INTR_SLIMBUS (1 << 2) +#define LPASS_INTR_UART (1 << 1) +#define LPASS_INTR_SFR (1 << 0) + +struct exynos_lpass { + struct regmap *pmu; + struct regmap *top; +}; + +static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) +{ + unsigned int val = 0; + + regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val); + + val &= ~mask; + regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); + + usleep_range(100, 150); + + val |= mask; + regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); +} + +static void exynos_lpass_enable(struct exynos_lpass *lpass) +{ + /* Unmask SFR, DMA and I2S interrupt */ + regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, + LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); + + regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, + LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); + + /* Activate related PADs from retention state */ + regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, + EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR); + + exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET); + exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET); + exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET); +} + +static void exynos_lpass_disable(struct exynos_lpass *lpass) +{ + /* Mask any unmasked IP interrupt sources */ + regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0); + regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0); + + /* Deactivate related PADs from retention state */ + regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 0); +} + +static const struct regmap_config exynos_lpass_reg_conf = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xfc, + .fast_io = true, +}; + +static int exynos_lpass_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct exynos_lpass *lpass; + void __iomem *base_top; + struct resource *res; + + if (!dev->of_node) + return -ENODEV; + + lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL); + if (!lpass) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + base_top = devm_ioremap_resource(dev, res); + if (IS_ERR(base_top)) + return PTR_ERR(base_top); + + lpass->top = regmap_init_mmio(dev, base_top, + &exynos_lpass_reg_conf); + if (IS_ERR(lpass->top)) { + dev_err(dev, "LPASS top regmap initialization failed\n"); + return PTR_ERR(lpass->top); + } + + lpass->pmu = syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,pmu-syscon"); + if (IS_ERR(lpass->pmu)) { + dev_err(dev, "Failed to lookup PMU regmap\n"); + return PTR_ERR(lpass->pmu); + } + + platform_set_drvdata(pdev, lpass); + exynos_lpass_enable(lpass); + + return of_platform_populate(dev->of_node, NULL, NULL, dev); +} + +static int exynos_lpass_suspend(struct device *dev) +{ + struct exynos_lpass *lpass = dev_get_drvdata(dev); + + exynos_lpass_disable(lpass); + return 0; +} + +static int exynos_lpass_resume(struct device *dev) +{ + struct exynos_lpass *lpass = dev_get_drvdata(dev); + + exynos_lpass_enable(lpass); + return 0; +} + +static const struct of_device_id exynos_lpass_of_match[] = { + { .compatible = "samsung,exynos5433-lpass" }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos_lpass_of_match); + +static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend, + exynos_lpass_resume); + +static struct platform_driver exynos_lpass_driver = { + .driver = { + .name = "exynos-lpass", + .pm = &lpass_pm_ops, + .of_match_table = exynos_lpass_of_match, + }, + .probe = exynos_lpass_probe, +}; +module_platform_driver(exynos_lpass_driver); + +MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h index 76f30f9..c28ff21 100644 --- a/include/linux/mfd/syscon/exynos5-pmu.h +++ b/include/linux/mfd/syscon/exynos5-pmu.h @@ -43,8 +43,10 @@ #define EXYNOS5433_MIPI_PHY2_CONTROL (0x718) #define EXYNOS5_PHY_ENABLE BIT(0) - #define EXYNOS5_MIPI_PHY_S_RESETN BIT(1) #define EXYNOS5_MIPI_PHY_M_RESETN BIT(2) +#define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028) +#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR BIT(28) + #endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */ -- 1.9.1

2 7

[alsa-devel] [PATCH] ASoC: nau8810: Add driver for Nuvoton codec chip NAU88C10
by John Hsu 09 Aug '16

09 Aug '16

The driver is for codec NAU88C10 of Nuvoton Technology Corporation. Signed-off-by: John Hsu <KCHSU0(a)nuvoton.com> --- .../devicetree/bindings/sound/nau8810.txt | 16 + sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/nau8810.c | 833 +++++++++++++++++++++ sound/soc/codecs/nau8810.h | 272 +++++++ 5 files changed, 1128 insertions(+) create mode 100755 Documentation/devicetree/bindings/sound/nau8810.txt create mode 100755 sound/soc/codecs/nau8810.c create mode 100755 sound/soc/codecs/nau8810.h diff --git a/Documentation/devicetree/bindings/sound/nau8810.txt b/Documentation/devicetree/bindings/sound/nau8810.txt new file mode 100755 index 0000000..05830e4 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nau8810.txt @@ -0,0 +1,16 @@ +NAU8810 audio CODEC + +This device supports I2C only. + +Required properties: + + - compatible : "nuvoton,nau8810" + + - reg : the I2C address of the device. + +Example: + +codec: nau8810@1a { + compatible = "nuvoton,nau8810"; + reg = <0x1a>; +}; diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index cb57f8f..bbd7324 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -91,6 +91,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_MAX9877 if I2C select SND_SOC_MC13783 if MFD_MC13XXX select SND_SOC_ML26124 if I2C + select SND_SOC_NAU8810 if I2C select SND_SOC_NAU8825 if I2C select SND_SOC_HDMI_CODEC select SND_SOC_PCM1681 if I2C @@ -1046,6 +1047,10 @@ config SND_SOC_MC13783 config SND_SOC_ML26124 tristate +config SND_SOC_NAU8810 + tristate "Nuvoton Technology Corporation NAU88C10 CODEC" + depends on I2C + config SND_SOC_NAU8825 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 550a174..3c15bc5 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -84,6 +84,7 @@ snd-soc-max9850-objs := max9850.o snd-soc-max9860-objs := max9860.o snd-soc-mc13783-objs := mc13783.o snd-soc-ml26124-objs := ml26124.o +snd-soc-nau8810-objs := nau8810.o snd-soc-nau8825-objs := nau8825.o snd-soc-hdmi-codec-objs := hdmi-codec.o snd-soc-pcm1681-objs := pcm1681.o @@ -301,6 +302,7 @@ obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o obj-$(CONFIG_SND_SOC_MAX9860) += snd-soc-max9860.o obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o +obj-$(CONFIG_SND_SOC_NAU8810) += snd-soc-nau8810.o obj-$(CONFIG_SND_SOC_NAU8825) += snd-soc-nau8825.o obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o obj-$(CONFIG_SND_SOC_PCM1681) += snd-soc-pcm1681.o diff --git a/sound/soc/codecs/nau8810.c b/sound/soc/codecs/nau8810.c new file mode 100755 index 0000000..d03e9c76 --- /dev/null +++ b/sound/soc/codecs/nau8810.c @@ -0,0 +1,833 @@ +/* + * nau8810.c -- NAU8810 ALSA Soc Audio driver + * + * Copyright 2016 Nuvoton Technology Corp. + * + * Author: David Lin <ctlin0(a)nuvoton.com> + * + * Based on WM8974.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/initval.h> +#include <sound/tlv.h> + +#include "nau8810.h" + + +static const int nau8810_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 }; + +static const struct reg_default nau8810_reg_defaults[] = { + { NAU8810_REG_POWER1, 0x0000 }, + { NAU8810_REG_POWER2, 0x0000 }, + { NAU8810_REG_POWER3, 0x0000 }, + { NAU8810_REG_IFACE, 0x0050 }, + { NAU8810_REG_COMP, 0x0000 }, + { NAU8810_REG_CLOCK, 0x0140 }, + { NAU8810_REG_SMPLR, 0x0000 }, + { NAU8810_REG_DAC, 0x0000 }, + { NAU8810_REG_DACGAIN, 0x00FF }, + { NAU8810_REG_ADC, 0x0100 }, + { NAU8810_REG_ADCGAIN, 0x00FF }, + { NAU8810_REG_EQ1, 0x012C }, + { NAU8810_REG_EQ2, 0x002C }, + { NAU8810_REG_EQ3, 0x002C }, + { NAU8810_REG_EQ4, 0x002C }, + { NAU8810_REG_EQ5, 0x002C }, + { NAU8810_REG_DACLIM1, 0x0032 }, + { NAU8810_REG_DACLIM2, 0x0000 }, + { NAU8810_REG_NOTCH1, 0x0000 }, + { NAU8810_REG_NOTCH2, 0x0000 }, + { NAU8810_REG_NOTCH3, 0x0000 }, + { NAU8810_REG_NOTCH4, 0x0000 }, + { NAU8810_REG_ALC1, 0x0038 }, + { NAU8810_REG_ALC2, 0x000B }, + { NAU8810_REG_ALC3, 0x0032 }, + { NAU8810_REG_NOISEGATE, 0x0000 }, + { NAU8810_REG_PLLN, 0x0008 }, + { NAU8810_REG_PLLK1, 0x000C }, + { NAU8810_REG_PLLK2, 0x0093 }, + { NAU8810_REG_PLLK3, 0x00E9 }, + { NAU8810_REG_ATTEN, 0x0000 }, + { NAU8810_REG_INPUT_SIGNAL, 0x0003 }, + { NAU8810_REG_PGAGAIN, 0x0010 }, + { NAU8810_REG_ADCBOOST, 0x0100 }, + { NAU8810_REG_OUTPUT, 0x0002 }, + { NAU8810_REG_SPKMIX, 0x0001 }, + { NAU8810_REG_SPKGAIN, 0x0039 }, + { NAU8810_REG_MONOMIX, 0x0001 }, + { NAU8810_REG_POWER4, 0x0000 }, + { NAU8810_REG_TSLOTCTL1, 0x0000 }, + { NAU8810_REG_TSLOTCTL2, 0x0020 }, + { NAU8810_REG_DEVICE_REVID, 0x00EF }, + { NAU8810_REG_I2C_DEVICEID, 0x001A }, + { NAU8810_REG_ADDITIONID, 0x00CA }, + { NAU8810_REG_RESERVE, 0x0124 }, + { NAU8810_REG_OUTCTL, 0x0001 }, + { NAU8810_REG_ALC1ENHAN1, 0x0000 }, + { NAU8810_REG_ALC1ENHAN2, 0x0039 }, + { NAU8810_REG_MISCCTL, 0x0000 }, + { NAU8810_REG_OUTTIEOFF, 0x0000 }, + { NAU8810_REG_AGCP2POUT, 0x0000 }, + { NAU8810_REG_AGCPOUT, 0x0000 }, + { NAU8810_REG_AMTCTL, 0x0000 }, + { NAU8810_REG_OUTTIEOFFMAN, 0x0000 }, +}; + +static bool nau8810_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8810_REG_RESET ... NAU8810_REG_SMPLR: + case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN: + case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN: + case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5: + case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2: + case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4: + case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN: + case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN: + case NAU8810_REG_ADCBOOST: + case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX: + case NAU8810_REG_SPKGAIN: + case NAU8810_REG_MONOMIX: + case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2: + case NAU8810_REG_DEVICE_REVID ... NAU8810_REG_RESERVE: + case NAU8810_REG_ALC1ENHAN1 ... NAU8810_REG_ALC1ENHAN2: + case NAU8810_REG_MISCCTL: + case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN: + return true; + default: + return false; + } +} + +static bool nau8810_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8810_REG_RESET ... NAU8810_REG_SMPLR: + case NAU8810_REG_DAC ... NAU8810_REG_DACGAIN: + case NAU8810_REG_ADC ... NAU8810_REG_ADCGAIN: + case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5: + case NAU8810_REG_DACLIM1 ... NAU8810_REG_DACLIM2: + case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4: + case NAU8810_REG_ALC1 ... NAU8810_REG_ATTEN: + case NAU8810_REG_INPUT_SIGNAL ... NAU8810_REG_PGAGAIN: + case NAU8810_REG_ADCBOOST: + case NAU8810_REG_OUTPUT ... NAU8810_REG_SPKMIX: + case NAU8810_REG_SPKGAIN: + case NAU8810_REG_MONOMIX: + case NAU8810_REG_POWER4 ... NAU8810_REG_TSLOTCTL2: + case NAU8810_REG_ALC1ENHAN1 ... NAU8810_REG_ALC1ENHAN2: + case NAU8810_REG_MISCCTL: + case NAU8810_REG_OUTTIEOFF ... NAU8810_REG_OUTTIEOFFMAN: + return true; + default: + return false; + } +} + +static bool nau8810_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8810_REG_RESET: + case NAU8810_REG_EQ1 ... NAU8810_REG_EQ5: + case NAU8810_REG_NOTCH1 ... NAU8810_REG_NOTCH4: + return true; + default: + return false; + } +} + +static int nau8810_reg_write(void *context, unsigned int reg, + unsigned int value) +{ + struct i2c_client *client = context; + uint8_t buf[2]; + __be16 *out = (void *)buf; + int ret; + + *out = cpu_to_be16((reg << 9) | value); + ret = i2c_master_send(client, buf, sizeof(buf)); + if (ret == sizeof(buf)) + return 0; + else if (ret < 0) + return ret; + else + return -EIO; +} + +static int nau8810_reg_read(void *context, unsigned int reg, + unsigned int *value) +{ + struct i2c_client *client = context; + struct i2c_msg xfer[2]; + uint8_t reg_buf; + uint16_t val_buf; + int ret; + + reg_buf = (uint8_t)(reg << 1); + xfer[0].addr = client->addr; + xfer[0].len = sizeof(reg_buf); + xfer[0].buf = &reg_buf; + xfer[0].flags = 0; + + xfer[1].addr = client->addr; + xfer[1].len = sizeof(val_buf); + xfer[1].buf = (uint8_t *)&val_buf; + xfer[1].flags = I2C_M_RD; + + ret = i2c_transfer(client->adapter, xfer, ARRAY_SIZE(xfer)); + if (ret < 0) + return ret; + else if (ret != ARRAY_SIZE(xfer)) + return -EIO; + + *value = be16_to_cpu(val_buf); + + return 0; +} + +static const char * const nau8810_companding[] = { + "Off", "NC", "u-law", "A-law" +}; +static const char * const nau8810_deemp[] = { + "None", "32kHz", "44.1kHz", "48kHz" +}; +static const char * const nau8810_eqmode[] = {"Capture", "Playback" }; +static const char * const nau8810_bw[] = {"Narrow", "Wide" }; +static const char * const nau8810_eq1[] = { + "80Hz", "105Hz", "135Hz", "175Hz" +}; +static const char * const nau8810_eq2[] = { + "230Hz", "300Hz", "385Hz", "500Hz" +}; +static const char * const nau8810_eq3[] = { + "650Hz", "850Hz", "1.1kHz", "1.4kHz" +}; +static const char * const nau8810_eq4[] = { + "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" +}; +static const char * const nau8810_eq5[] = { + "5.3kHz", "6.9kHz", "9kHz", "11.7kHz" +}; +static const char * const nau8810_alc[] = {"Normal", "Limiter" }; + +static const struct soc_enum nau8810_enum[] = { + SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_ADCCM_SFT, + ARRAY_SIZE(nau8810_companding), nau8810_companding), + SOC_ENUM_SINGLE(NAU8810_REG_COMP, NAU8810_DACCM_SFT, + ARRAY_SIZE(nau8810_companding), nau8810_companding), + SOC_ENUM_SINGLE(NAU8810_REG_DAC, NAU8810_DEEMP_SFT, + ARRAY_SIZE(nau8810_deemp), nau8810_deemp), + SOC_ENUM_SINGLE(NAU8810_REG_EQ1, NAU8810_EQM_SFT, + ARRAY_SIZE(nau8810_eqmode), nau8810_eqmode), + + SOC_ENUM_SINGLE(NAU8810_REG_EQ1, NAU8810_EQ1CF_SFT, + ARRAY_SIZE(nau8810_eq1), nau8810_eq1), + SOC_ENUM_SINGLE(NAU8810_REG_EQ2, NAU8810_EQ2BW_SFT, + ARRAY_SIZE(nau8810_bw), nau8810_bw), + SOC_ENUM_SINGLE(NAU8810_REG_EQ2, NAU8810_EQ2CF_SFT, + ARRAY_SIZE(nau8810_eq2), nau8810_eq2), + SOC_ENUM_SINGLE(NAU8810_REG_EQ3, NAU8810_EQ3BW_SFT, + ARRAY_SIZE(nau8810_bw), nau8810_bw), + + SOC_ENUM_SINGLE(NAU8810_REG_EQ3, NAU8810_EQ3CF_SFT, + ARRAY_SIZE(nau8810_eq3), nau8810_eq3), + SOC_ENUM_SINGLE(NAU8810_REG_EQ4, NAU8810_EQ4BW_SFT, + ARRAY_SIZE(nau8810_bw), nau8810_bw), + SOC_ENUM_SINGLE(NAU8810_REG_EQ4, NAU8810_EQ4CF_SFT, + ARRAY_SIZE(nau8810_eq4), nau8810_eq4), + SOC_ENUM_SINGLE(NAU8810_REG_EQ5, NAU8810_EQ5CF_SFT, + ARRAY_SIZE(nau8810_eq5), nau8810_eq5), + + SOC_ENUM_SINGLE(NAU8810_REG_ALC3, NAU8810_ALCM_SFT, + ARRAY_SIZE(nau8810_alc), nau8810_alc), +}; + +static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); +static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); +static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0); +static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0); + +static const struct snd_kcontrol_new nau8810_snd_controls[] = { + + SOC_ENUM("ADC Companding", nau8810_enum[0]), + SOC_ENUM("DAC Companding", nau8810_enum[1]), + SOC_ENUM("DAC De-emphasis", nau8810_enum[2]), + SOC_ENUM("EQ Function", nau8810_enum[3]), + SOC_ENUM("EQ1 Cut Off", nau8810_enum[4]), + SOC_ENUM("EQ2 Bandwidth", nau8810_enum[5]), + SOC_ENUM("EQ2 Cut Off", nau8810_enum[6]), + SOC_ENUM("EQ3 Bandwidth", nau8810_enum[7]), + SOC_ENUM("EQ3 Cut Off", nau8810_enum[8]), + SOC_ENUM("EQ4 Bandwidth", nau8810_enum[9]), + SOC_ENUM("EQ4 Cut Off", nau8810_enum[10]), + SOC_ENUM("EQ5 Cut Off", nau8810_enum[11]), + SOC_ENUM("ALC Mode", nau8810_enum[12]), + + SOC_SINGLE("Digital Loopback Switch", NAU8810_REG_COMP, + NAU8810_ADDAP_SFT, 1, 0), + + SOC_SINGLE("DAC Inversion Switch", NAU8810_REG_DAC, + NAU8810_DACPL_SFT, 1, 0), + SOC_SINGLE_TLV("Playback Gain", NAU8810_REG_DACGAIN, + NAU8810_DACGAIN_SFT, 0xff, 0, digital_tlv), + + SOC_SINGLE("High Pass Filter Switch", NAU8810_REG_ADC, + NAU8810_HPFEN_SFT, 1, 0), + SOC_SINGLE("High Pass Cut Off", NAU8810_REG_ADC, + NAU8810_HPF_SFT, 0x7, 0), + + SOC_SINGLE("ADC Inversion Switch", NAU8810_REG_ADC, + NAU8810_ADCPL_SFT, 1, 0), + SOC_SINGLE_TLV("Capture Gain", NAU8810_REG_ADCGAIN, + NAU8810_ADCGAIN_SFT, 0xff, 0, digital_tlv), + + SOC_SINGLE_TLV("EQ1 Gain", NAU8810_REG_EQ1, + NAU8810_EQ1GC_SFT, 0x18, 1, eq_tlv), + SOC_SINGLE_TLV("EQ2 Gain", NAU8810_REG_EQ2, + NAU8810_EQ2GC_SFT, 0x18, 1, eq_tlv), + SOC_SINGLE_TLV("EQ3 Gain", NAU8810_REG_EQ3, + NAU8810_EQ3GC_SFT, 0x18, 1, eq_tlv), + SOC_SINGLE_TLV("EQ4 Gain", NAU8810_REG_EQ4, + NAU8810_EQ4GC_SFT, 0x18, 1, eq_tlv), + SOC_SINGLE_TLV("EQ5 Gain", NAU8810_REG_EQ5, + NAU8810_EQ5GC_SFT, 0x18, 1, eq_tlv), + + SOC_SINGLE("DAC Limiter Switch", NAU8810_REG_DACLIM1, + NAU8810_DACLIMEN_SFT, 1, 0), + SOC_SINGLE("DAC Limiter Decay", NAU8810_REG_DACLIM1, + NAU8810_DACLIMDCY_SFT, 0xf, 0), + SOC_SINGLE("DAC Limiter Attack", NAU8810_REG_DACLIM1, + NAU8810_DACLIMATK_SFT, 0xf, 0), + + SOC_SINGLE("DAC Limiter Threshold", NAU8810_REG_DACLIM2, + NAU8810_DACLIMTHL_SFT, 0x7, 0), + SOC_SINGLE("DAC Limiter Boost", NAU8810_REG_DACLIM2, + NAU8810_DACLIMBST_SFT, 0xf, 0), + + SOC_SINGLE("ALC Enable Switch", NAU8810_REG_ALC1, + NAU8810_ALCEN_SFT, 1, 0), + SOC_SINGLE("ALC Max Gain", NAU8810_REG_ALC1, + NAU8810_ALCMXGAIN_SFT, 0x7, 0), + SOC_SINGLE("ALC Min Gain", NAU8810_REG_ALC1, + NAU8810_ALCMINGAIN_SFT, 0x7, 0), + + SOC_SINGLE("ALC ZC Switch", NAU8810_REG_ALC2, + NAU8810_ALCZC_SFT, 1, 0), + SOC_SINGLE("ALC Hold", NAU8810_REG_ALC2, + NAU8810_ALCHT_SFT, 0xf, 0), + SOC_SINGLE("ALC Target", NAU8810_REG_ALC2, + NAU8810_ALCSL_SFT, 0xf, 0), + + SOC_SINGLE("ALC Decay", NAU8810_REG_ALC3, + NAU8810_ALCDCY_SFT, 0xf, 0), + SOC_SINGLE("ALC Attack", NAU8810_REG_ALC3, + NAU8810_ALCATK_SFT, 0xf, 0), + + SOC_SINGLE("ALC Noise Gate Switch", NAU8810_REG_NOISEGATE, + NAU8810_ALCNEN_SFT, 1, 0), + SOC_SINGLE("ALC Noise Gate Threshold", NAU8810_REG_NOISEGATE, + NAU8810_ALCNTH_SFT, 0x7, 0), + + SOC_SINGLE("PGA ZC Switch", NAU8810_REG_PGAGAIN, + NAU8810_PGAZC_SFT, 1, 0), + SOC_SINGLE_TLV("PGA Volume", NAU8810_REG_PGAGAIN, + NAU8810_PGAGAIN_SFT, 0x3f, 0, inpga_tlv), + + SOC_SINGLE("Speaker ZC Switch", NAU8810_REG_SPKGAIN, + NAU8810_SPKZC_SFT, 1, 0), + SOC_SINGLE("Speaker Mute Switch", NAU8810_REG_SPKGAIN, + NAU8810_SPKMT_SFT, 1, 0), + SOC_SINGLE_TLV("Speaker Volume", NAU8810_REG_SPKGAIN, + NAU8810_SPKGAIN_SFT, 0x3f, 0, spk_tlv), + + SOC_SINGLE("Capture Boost(+20dB)", NAU8810_REG_ADCBOOST, + NAU8810_PGABST_SFT, 1, 0), + SOC_SINGLE("Mono Mute Switch", NAU8810_REG_MONOMIX, + NAU8810_MOUTMXMT_SFT, 1, 0), + + SOC_SINGLE("DAC Oversampling Rate(128x) Switch", NAU8810_REG_DAC, + NAU8810_DACOS_SFT, 1, 0), + SOC_SINGLE("ADC Oversampling Rate(128x) Switch", NAU8810_REG_ADC, + NAU8810_ADCOS_SFT, 1, 0), +}; + +/* Speaker Output Mixer */ +static const struct snd_kcontrol_new nau8810_speaker_mixer_controls[] = { + SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_SPKMIX, + NAU8810_BYPSPK_SFT, 1, 0), + SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_SPKMIX, + NAU8810_DACSPK_SFT, 1, 0), +}; + +/* Mono Output Mixer */ +static const struct snd_kcontrol_new nau8810_mono_mixer_controls[] = { + SOC_DAPM_SINGLE("Line Bypass Switch", NAU8810_REG_MONOMIX, + NAU8810_BYPMOUT_SFT, 1, 0), + SOC_DAPM_SINGLE("PCM Playback Switch", NAU8810_REG_MONOMIX, + NAU8810_DACMOUT_SFT, 1, 0), +}; + +/* PGA Mute */ +static const struct snd_kcontrol_new nau8810_inpga_mute[] = { + SOC_DAPM_SINGLE("PGA Mute Switch", NAU8810_REG_PGAGAIN, + NAU8810_PGAMT_SFT, 1, 0), +}; + +/* Input PGA */ +static const struct snd_kcontrol_new nau8810_inpga[] = { + SOC_DAPM_SINGLE("MicN Switch", NAU8810_REG_INPUT_SIGNAL, + NAU8810_NMICPGA_SFT, 1, 0), + SOC_DAPM_SINGLE("MicP Switch", NAU8810_REG_INPUT_SIGNAL, + NAU8810_PMICPGA_SFT, 1, 0), +}; + +/* Mic Input boost vol */ +static const struct snd_kcontrol_new nau8810_mic_boost_controls = + SOC_DAPM_SINGLE("Mic Volume", NAU8810_REG_ADCBOOST, + NAU8810_PMICBSTGAIN_SFT, 0x7, 0); + +static const struct snd_soc_dapm_widget nau8810_dapm_widgets[] = { + SND_SOC_DAPM_MIXER("Speaker Mixer", NAU8810_REG_POWER3, + NAU8810_SPKMX_EN_SFT, 0, &nau8810_speaker_mixer_controls[0], + ARRAY_SIZE(nau8810_speaker_mixer_controls)), + SND_SOC_DAPM_MIXER("Mono Mixer", NAU8810_REG_POWER3, + NAU8810_MOUTMX_EN_SFT, 0, &nau8810_mono_mixer_controls[0], + ARRAY_SIZE(nau8810_mono_mixer_controls)), + SND_SOC_DAPM_DAC("DAC", "HiFi Playback", NAU8810_REG_POWER3, + NAU8810_DAC_EN_SFT, 0), + SND_SOC_DAPM_ADC("ADC", "HiFi Capture", NAU8810_REG_POWER2, + NAU8810_ADC_EN_SFT, 0), + SND_SOC_DAPM_PGA("SpkN Out", NAU8810_REG_POWER3, + NAU8810_NSPK_EN_SFT, 0, NULL, 0), + SND_SOC_DAPM_PGA("SpkP Out", NAU8810_REG_POWER3, + NAU8810_PSPK_EN_SFT, 0, NULL, 0), + SND_SOC_DAPM_PGA("Mono Out", NAU8810_REG_POWER3, + NAU8810_MOUT_EN_SFT, 0, NULL, 0), + + SND_SOC_DAPM_MIXER("Input PGA", NAU8810_REG_POWER2, + NAU8810_PGA_EN_SFT, 0, nau8810_inpga, + ARRAY_SIZE(nau8810_inpga)), + SND_SOC_DAPM_MIXER("Input Boost Stage", NAU8810_REG_POWER2, + NAU8810_BST_EN_SFT, 0, nau8810_inpga_mute, + ARRAY_SIZE(nau8810_inpga_mute)), + + SND_SOC_DAPM_SUPPLY("Mic Bias", NAU8810_REG_POWER1, + NAU8810_MICBIAS_EN_SFT, 0, NULL, 0), + + SND_SOC_DAPM_INPUT("MICN"), + SND_SOC_DAPM_INPUT("MICP"), + SND_SOC_DAPM_OUTPUT("MONOOUT"), + SND_SOC_DAPM_OUTPUT("SPKOUTP"), + SND_SOC_DAPM_OUTPUT("SPKOUTN"), +}; + +static const struct snd_soc_dapm_route nau8810_dapm_routes[] = { + /* Mono output mixer */ + {"Mono Mixer", "PCM Playback Switch", "DAC"}, + {"Mono Mixer", "Line Bypass Switch", "Input Boost Stage"}, + + /* Speaker output mixer */ + {"Speaker Mixer", "PCM Playback Switch", "DAC"}, + {"Speaker Mixer", "Line Bypass Switch", "Input Boost Stage"}, + + /* Outputs */ + {"Mono Out", NULL, "Mono Mixer"}, + {"MONOOUT", NULL, "Mono Out"}, + {"SpkN Out", NULL, "Speaker Mixer"}, + {"SpkP Out", NULL, "Speaker Mixer"}, + {"SPKOUTN", NULL, "SpkN Out"}, + {"SPKOUTP", NULL, "SpkP Out"}, + + /* Input Boost Stage */ + {"ADC", NULL, "Input Boost Stage"}, + {"Input Boost Stage", NULL, "Input PGA"}, + {"Input Boost Stage", NULL, "MICP"}, + + /* Input PGA */ + {"Input PGA", "MicN Switch", "MICN"}, + {"Input PGA", "MicP Switch", "MICP"}, +}; + +static int nau8810_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); + + nau8810->sysclk = freq; + dev_dbg(nau8810->dev, "master sysclk %dHz\n", nau8810->sysclk); + + return 0; +} + +static int nau8810_config_clkdiv(struct nau8810 *nau8810, int div, int rate) +{ + struct regmap *regmap = nau8810->regmap; + int i, sclk, imclk; + + switch (nau8810->div_id) { + case NAU8810_MCLK_DIV_PLL: + /* master clock from PLL and enable PLL */ + regmap_update_bits(regmap, NAU8810_REG_CLOCK, + NAU8810_MCLKSEL_MASK, (div << NAU8810_MCLKSEL_SFT)); + regmap_update_bits(regmap, NAU8810_REG_POWER1, + NAU8810_PLL_EN, NAU8810_PLL_EN); + regmap_update_bits(regmap, NAU8810_REG_CLOCK, + NAU8810_CLKM_MASK, NAU8810_CLKM_PLL); + break; + + case NAU8810_MCLK_DIV_MCLK: + /* Configure the master clock prescaler div to make system + * clock to approximate the internal master clock (IMCLK); + * and large or equal to IMCLK. + */ + div = 0; + imclk = rate * 256; + for (i = 1; i < ARRAY_SIZE(nau8810_mclk_scaler); i++) { + sclk = (nau8810->sysclk * 10) / + nau8810_mclk_scaler[i]; + if (sclk < imclk) + break; + div = i; + } + dev_dbg(nau8810->dev, + "master clock prescaler %x for fs %d\n", div, rate); + + /* master clock from MCLK and disable PLL */ + regmap_update_bits(regmap, NAU8810_REG_CLOCK, + NAU8810_MCLKSEL_MASK, (div << NAU8810_MCLKSEL_SFT)); + regmap_update_bits(regmap, NAU8810_REG_CLOCK, + NAU8810_CLKM_MASK, NAU8810_CLKM_MCLK); + regmap_update_bits(regmap, NAU8810_REG_POWER1, + NAU8810_PLL_EN, 0); + break; + + case NAU8810_BCLK_DIV: + regmap_update_bits(regmap, NAU8810_REG_CLOCK, + NAU8810_BCLKSEL_MASK, (div << NAU8810_BCLKSEL_SFT)); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int nau8810_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) +{ + struct snd_soc_codec *codec = dai->codec; + struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); + int ret = 0; + + nau8810->div_id = div_id; + if (div_id != NAU8810_MCLK_DIV_MCLK) + /* Defer the master clock prescaler configuration to DAI + * hardware parameter if master clock from MCLK because + * it needs runtime fs information to get the proper div. + */ + ret = nau8810_config_clkdiv(nau8810, div, 0); + + return ret; +} + +static int nau8810_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); + u16 ctrl1_val = 0, ctrl2_val = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + ctrl2_val |= NAU8810_CLKIO_MASTER; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + ctrl1_val |= NAU8810_AIFMT_I2S; + break; + case SND_SOC_DAIFMT_RIGHT_J: + break; + case SND_SOC_DAIFMT_LEFT_J: + ctrl1_val |= NAU8810_AIFMT_LEFT; + break; + case SND_SOC_DAIFMT_DSP_A: + ctrl1_val |= NAU8810_AIFMT_PCM_A; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + ctrl1_val |= NAU8810_BCLKP_IB | NAU8810_FSP_IF; + break; + case SND_SOC_DAIFMT_IB_NF: + ctrl1_val |= NAU8810_BCLKP_IB; + break; + case SND_SOC_DAIFMT_NB_IF: + ctrl1_val |= NAU8810_FSP_IF; + break; + default: + return -EINVAL; + } + + regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE, + NAU8810_AIFMT_MASK | NAU8810_FSP_IF | + NAU8810_BCLKP_IB, ctrl1_val); + regmap_update_bits(nau8810->regmap, NAU8810_REG_CLOCK, + NAU8810_CLKIO_MASK, ctrl2_val); + + return 0; +} + +static int nau8810_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); + int val_len = 0, val_rate = 0; + + switch (params_width(params)) { + case 16: + break; + case 20: + val_len |= NAU8810_WLEN_20; + break; + case 24: + val_len |= NAU8810_WLEN_24; + break; + case 32: + val_len |= NAU8810_WLEN_32; + break; + } + + switch (params_rate(params)) { + case 8000: + val_rate |= NAU8810_SMPLR_8K; + break; + case 11025: + val_rate |= NAU8810_SMPLR_12K; + break; + case 16000: + val_rate |= NAU8810_SMPLR_16K; + break; + case 22050: + val_rate |= NAU8810_SMPLR_24K; + break; + case 32000: + val_rate |= NAU8810_SMPLR_32K; + break; + case 44100: + case 48000: + break; + } + + regmap_update_bits(nau8810->regmap, NAU8810_REG_IFACE, + NAU8810_WLEN_MASK, val_len); + regmap_update_bits(nau8810->regmap, NAU8810_REG_SMPLR, + NAU8810_SMPLR_MASK, val_rate); + + /* If the master clock is from MCLK, provide the runtime FS for driver + * to get the master clock prescaler configuration. + */ + if (nau8810->div_id == NAU8810_MCLK_DIV_MCLK) + nau8810_config_clkdiv(nau8810, 0, params_rate(params)); + + return 0; +} + +static int nau8810_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); + struct regmap *map = nau8810->regmap; + + switch (level) { + case SND_SOC_BIAS_ON: + case SND_SOC_BIAS_PREPARE: + regmap_update_bits(map, NAU8810_REG_POWER1, + NAU8810_REFIMP_MASK, NAU8810_REFIMP_80K); + break; + + case SND_SOC_BIAS_STANDBY: + regmap_update_bits(map, NAU8810_REG_POWER1, + NAU8810_IOBUF_EN | NAU8810_ABIAS_EN, + NAU8810_IOBUF_EN | NAU8810_ABIAS_EN); + + if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { + regcache_sync(map); + regmap_update_bits(map, NAU8810_REG_POWER1, + NAU8810_REFIMP_MASK, NAU8810_REFIMP_3K); + mdelay(100); + } + regmap_update_bits(map, NAU8810_REG_POWER1, + NAU8810_REFIMP_MASK, NAU8810_REFIMP_300K); + break; + + case SND_SOC_BIAS_OFF: + regmap_write(map, NAU8810_REG_POWER1, 0); + regmap_write(map, NAU8810_REG_POWER2, 0); + regmap_write(map, NAU8810_REG_POWER3, 0); + break; + } + + return 0; +} + + +#define NAU8810_RATES (SNDRV_PCM_RATE_8000_48000) + +#define NAU8810_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static const struct snd_soc_dai_ops nau8810_ops = { + .hw_params = nau8810_pcm_hw_params, + .set_fmt = nau8810_set_dai_fmt, + .set_sysclk = nau8810_set_sysclk, + .set_clkdiv = nau8810_set_clkdiv, +}; + +static struct snd_soc_dai_driver nau8810_dai = { + .name = "nau8810-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, /* Only 1 channel of data */ + .rates = NAU8810_RATES, + .formats = NAU8810_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, /* Only 1 channel of data */ + .rates = NAU8810_RATES, + .formats = NAU8810_FORMATS, + }, + .ops = &nau8810_ops, + .symmetric_rates = 1, +}; + +static const struct regmap_config nau8810_regmap_config = { + .reg_bits = 7, + .val_bits = 9, + + .max_register = NAU8810_REG_MAX, + .readable_reg = nau8810_readable_reg, + .writeable_reg = nau8810_writeable_reg, + .volatile_reg = nau8810_volatile_reg, + .reg_read = nau8810_reg_read, + .reg_write = nau8810_reg_write, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = nau8810_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(nau8810_reg_defaults), +}; + +static int nau8810_probe(struct snd_soc_codec *codec) +{ + struct nau8810 *nau8810 = snd_soc_codec_get_drvdata(codec); + + regmap_write(nau8810->regmap, NAU8810_REG_RESET, 0x00); + + return 0; +} + +static struct snd_soc_codec_driver soc_codec_dev_nau8810 = { + .probe = nau8810_probe, + .set_bias_level = nau8810_set_bias_level, + .suspend_bias_off = true, + + .controls = nau8810_snd_controls, + .num_controls = ARRAY_SIZE(nau8810_snd_controls), + .dapm_widgets = nau8810_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(nau8810_dapm_widgets), + .dapm_routes = nau8810_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(nau8810_dapm_routes), +}; + +static int nau8810_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct device *dev = &i2c->dev; + struct nau8810 *nau8810 = dev_get_platdata(dev); + + if (!nau8810) { + nau8810 = devm_kzalloc(dev, sizeof(*nau8810), GFP_KERNEL); + if (!nau8810) + return -ENOMEM; + } + i2c_set_clientdata(i2c, nau8810); + + nau8810->regmap = devm_regmap_init(dev, NULL, + i2c, &nau8810_regmap_config); + if (IS_ERR(nau8810->regmap)) + return PTR_ERR(nau8810->regmap); + + nau8810->dev = dev; + + return snd_soc_register_codec(dev, + &soc_codec_dev_nau8810, &nau8810_dai, 1); +} + +static int nau8810_i2c_remove(struct i2c_client *client) +{ + snd_soc_unregister_codec(&client->dev); + + return 0; +} + +static const struct i2c_device_id nau8810_i2c_id[] = { + { "nau8810", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, nau8810_i2c_id); + +#ifdef CONFIG_OF +static const struct of_device_id nau8810_of_match[] = { + { .compatible = "nuvoton,nau8810", }, + { } +}; +MODULE_DEVICE_TABLE(of, nau8810_of_match); +#endif + +static struct i2c_driver nau8810_i2c_driver = { + .driver = { + .name = "nau8810", + .of_match_table = of_match_ptr(nau8810_of_match), + }, + .probe = nau8810_i2c_probe, + .remove = nau8810_i2c_remove, + .id_table = nau8810_i2c_id, +}; + +module_i2c_driver(nau8810_i2c_driver); + +MODULE_DESCRIPTION("ASoC NAU8810 driver"); +MODULE_AUTHOR("David Lin <ctlin0(a)nuvoton.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/nau8810.h b/sound/soc/codecs/nau8810.h new file mode 100755 index 0000000..174d26e --- /dev/null +++ b/sound/soc/codecs/nau8810.h @@ -0,0 +1,272 @@ +/* + * NAU8810 ALSA SoC audio driver + * + * Copyright 2016 Nuvoton Technology Corp. + * Author: David Lin <ctlin0(a)nuvoton.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __NAU8810_H__ +#define __NAU8810_H__ + +#define NAU8810_REG_RESET 0x00 +#define NAU8810_REG_POWER1 0x01 +#define NAU8810_REG_POWER2 0x02 +#define NAU8810_REG_POWER3 0x03 +#define NAU8810_REG_IFACE 0x04 +#define NAU8810_REG_COMP 0x05 +#define NAU8810_REG_CLOCK 0x06 +#define NAU8810_REG_SMPLR 0x07 +#define NAU8810_REG_DAC 0x0A +#define NAU8810_REG_DACGAIN 0x0B +#define NAU8810_REG_ADC 0x0E +#define NAU8810_REG_ADCGAIN 0x0F +#define NAU8810_REG_EQ1 0x12 +#define NAU8810_REG_EQ2 0x13 +#define NAU8810_REG_EQ3 0x14 +#define NAU8810_REG_EQ4 0x15 +#define NAU8810_REG_EQ5 0x16 +#define NAU8810_REG_DACLIM1 0x18 +#define NAU8810_REG_DACLIM2 0x19 +#define NAU8810_REG_NOTCH1 0x1B +#define NAU8810_REG_NOTCH2 0x1C +#define NAU8810_REG_NOTCH3 0x1D +#define NAU8810_REG_NOTCH4 0x1E +#define NAU8810_REG_ALC1 0x20 +#define NAU8810_REG_ALC2 0x21 +#define NAU8810_REG_ALC3 0x22 +#define NAU8810_REG_NOISEGATE 0x23 +#define NAU8810_REG_PLLN 0x24 +#define NAU8810_REG_PLLK1 0x25 +#define NAU8810_REG_PLLK2 0x26 +#define NAU8810_REG_PLLK3 0x27 +#define NAU8810_REG_ATTEN 0x28 +#define NAU8810_REG_INPUT_SIGNAL 0x2C +#define NAU8810_REG_PGAGAIN 0x2D +#define NAU8810_REG_ADCBOOST 0x2F +#define NAU8810_REG_OUTPUT 0x31 +#define NAU8810_REG_SPKMIX 0x32 +#define NAU8810_REG_SPKGAIN 0x36 +#define NAU8810_REG_MONOMIX 0x38 +#define NAU8810_REG_POWER4 0x3A +#define NAU8810_REG_TSLOTCTL1 0x3B +#define NAU8810_REG_TSLOTCTL2 0x3C +#define NAU8810_REG_DEVICE_REVID 0x3E +#define NAU8810_REG_I2C_DEVICEID 0x3F +#define NAU8810_REG_ADDITIONID 0x40 +#define NAU8810_REG_RESERVE 0x41 +#define NAU8810_REG_OUTCTL 0x45 +#define NAU8810_REG_ALC1ENHAN1 0x46 +#define NAU8810_REG_ALC1ENHAN2 0x47 +#define NAU8810_REG_MISCCTL 0x49 +#define NAU8810_REG_OUTTIEOFF 0x4B +#define NAU8810_REG_AGCP2POUT 0x4C +#define NAU8810_REG_AGCPOUT 0x4D +#define NAU8810_REG_AMTCTL 0x4E +#define NAU8810_REG_OUTTIEOFFMAN 0x4F +#define NAU8810_REG_MAX NAU8810_REG_OUTTIEOFFMAN + + +/* NAU8810_REG_POWER1 (0x1) */ +#define NAU8810_DCBUF_EN (0x1 << 8) +#define NAU8810_PLL_EN (0x1 << 5) +#define NAU8810_MICBIAS_EN_SFT 4 +#define NAU8810_ABIAS_EN (0x1 << 3) +#define NAU8810_IOBUF_EN (0x1 << 2) +#define NAU8810_REFIMP_MASK 0x3 +#define NAU8810_REFIMP_DIS 0x0 +#define NAU8810_REFIMP_80K 0x1 +#define NAU8810_REFIMP_300K 0x2 +#define NAU8810_REFIMP_3K 0x3 + +/* NAU8810_REG_POWER2 (0x2) */ +#define NAU8810_BST_EN_SFT 4 +#define NAU8810_PGA_EN_SFT 2 +#define NAU8810_ADC_EN_SFT 0 + +/* NAU8810_REG_POWER3 (0x3) */ +#define NAU8810_DAC_EN_SFT 0 +#define NAU8810_SPKMX_EN_SFT 2 +#define NAU8810_MOUTMX_EN_SFT 3 +#define NAU8810_PSPK_EN_SFT 5 +#define NAU8810_NSPK_EN_SFT 6 +#define NAU8810_MOUT_EN_SFT 7 + +/* NAU8810_REG_IFACE (0x4) */ +#define NAU8810_AIFMT_SFT 3 +#define NAU8810_AIFMT_MASK (0x3 << NAU8810_AIFMT_SFT) +#define NAU8810_AIFMT_RIGHT (0x0 << NAU8810_AIFMT_SFT) +#define NAU8810_AIFMT_LEFT (0x1 << NAU8810_AIFMT_SFT) +#define NAU8810_AIFMT_I2S (0x2 << NAU8810_AIFMT_SFT) +#define NAU8810_AIFMT_PCM_A (0x3 << NAU8810_AIFMT_SFT) +#define NAU8810_WLEN_SFT 5 +#define NAU8810_WLEN_MASK (0x3 << NAU8810_WLEN_SFT) +#define NAU8810_WLEN_16 (0x0 << NAU8810_WLEN_SFT) +#define NAU8810_WLEN_20 (0x1 << NAU8810_WLEN_SFT) +#define NAU8810_WLEN_24 (0x2 << NAU8810_WLEN_SFT) +#define NAU8810_WLEN_32 (0x3 << NAU8810_WLEN_SFT) +#define NAU8810_FSP_IF (0x1 << 7) +#define NAU8810_BCLKP_IB (0x1 << 8) + +/* NAU8810_REG_COMP (0x5) */ +#define NAU8810_ADDAP_SFT 0 +#define NAU8810_ADCCM_SFT 1 +#define NAU8810_DACCM_SFT 3 + +/* NAU8810_REG_CLOCK (0x6) */ +#define NAU8810_CLKIO_MASK 0x1 +#define NAU8810_CLKIO_SLAVE 0x0 +#define NAU8810_CLKIO_MASTER 0x1 +#define NAU8810_BCLKSEL_SFT 2 +#define NAU8810_BCLKSEL_MASK (0x7 << NAU8810_BCLKSEL_SFT) +#define NAU8810_BCLKDIV_1 (0x0 << NAU8810_BCLKSEL_SFT) +#define NAU8810_BCLKDIV_2 (0x1 << NAU8810_BCLKSEL_SFT) +#define NAU8810_BCLKDIV_4 (0x2 << NAU8810_BCLKSEL_SFT) +#define NAU8810_BCLKDIV_8 (0x3 << NAU8810_BCLKSEL_SFT) +#define NAU8810_BCLKDIV_16 (0x4 << NAU8810_BCLKSEL_SFT) +#define NAU8810_BCLKDIV_32 (0x5 << NAU8810_BCLKSEL_SFT) +#define NAU8810_MCLKSEL_SFT 5 +#define NAU8810_MCLKSEL_MASK (0x7 << NAU8810_MCLKSEL_SFT) +#define NAU8810_CLKM_SFT 8 +#define NAU8810_CLKM_MASK (0x1 << NAU8810_CLKM_SFT) +#define NAU8810_CLKM_MCLK (0x0 << NAU8810_CLKM_SFT) +#define NAU8810_CLKM_PLL (0x1 << NAU8810_CLKM_SFT) + +/* NAU8810_REG_SMPLR (0x7) */ +#define NAU8810_SMPLR_SFT 1 +#define NAU8810_SMPLR_MASK (0x7 << NAU8810_SMPLR_SFT) +#define NAU8810_SMPLR_48K (0x0 << NAU8810_SMPLR_SFT) +#define NAU8810_SMPLR_32K (0x1 << NAU8810_SMPLR_SFT) +#define NAU8810_SMPLR_24K (0x2 << NAU8810_SMPLR_SFT) +#define NAU8810_SMPLR_16K (0x3 << NAU8810_SMPLR_SFT) +#define NAU8810_SMPLR_12K (0x4 << NAU8810_SMPLR_SFT) +#define NAU8810_SMPLR_8K (0x5 << NAU8810_SMPLR_SFT) + +/* NAU8810_REG_DAC (0xA) */ +#define NAU8810_DACPL_SFT 0 +#define NAU8810_DACOS_SFT 3 +#define NAU8810_DEEMP_SFT 4 + +/* NAU8810_REG_DACGAIN (0xB) */ +#define NAU8810_DACGAIN_SFT 0 + +/* NAU8810_REG_ADC (0xE) */ +#define NAU8810_ADCPL_SFT 0 +#define NAU8810_ADCOS_SFT 3 +#define NAU8810_HPF_SFT 4 +#define NAU8810_HPFEN_SFT 8 + +/* NAU8810_REG_ADCGAIN (0xF) */ +#define NAU8810_ADCGAIN_SFT 0 + +/* NAU8810_REG_EQ1 (0x12) */ +#define NAU8810_EQ1GC_SFT 0 +#define NAU8810_EQ1CF_SFT 5 +#define NAU8810_EQM_SFT 8 + +/* NAU8810_REG_EQ2 (0x13) */ +#define NAU8810_EQ2GC_SFT 0 +#define NAU8810_EQ2CF_SFT 5 +#define NAU8810_EQ2BW_SFT 8 + +/* NAU8810_REG_EQ3 (0x14) */ +#define NAU8810_EQ3GC_SFT 0 +#define NAU8810_EQ3CF_SFT 5 +#define NAU8810_EQ3BW_SFT 8 + +/* NAU8810_REG_EQ4 (0x15) */ +#define NAU8810_EQ4GC_SFT 0 +#define NAU8810_EQ4CF_SFT 5 +#define NAU8810_EQ4BW_SFT 8 + +/* NAU8810_REG_EQ5 (0x16) */ +#define NAU8810_EQ5GC_SFT 0 +#define NAU8810_EQ5CF_SFT 5 + +/* NAU8810_REG_DACLIM1 (0x18) */ +#define NAU8810_DACLIMATK_SFT 0 +#define NAU8810_DACLIMDCY_SFT 4 +#define NAU8810_DACLIMEN_SFT 8 + +/* NAU8810_REG_DACLIM2 (0x19) */ +#define NAU8810_DACLIMBST_SFT 0 +#define NAU8810_DACLIMTHL_SFT 4 + +/* NAU8810_REG_ALC1 (0x20) */ +#define NAU8810_ALCMINGAIN_SFT 0 +#define NAU8810_ALCMXGAIN_SFT 3 +#define NAU8810_ALCEN_SFT 8 + +/* NAU8810_REG_ALC2 (0x21) */ +#define NAU8810_ALCSL_SFT 0 +#define NAU8810_ALCHT_SFT 4 +#define NAU8810_ALCZC_SFT 8 + +/* NAU8810_REG_ALC3 (0x22) */ +#define NAU8810_ALCATK_SFT 0 +#define NAU8810_ALCDCY_SFT 4 +#define NAU8810_ALCM_SFT 8 + +/* NAU8810_REG_NOISEGATE (0x23) */ +#define NAU8810_ALCNTH_SFT 0 +#define NAU8810_ALCNEN_SFT 3 + +/* NAU8810_REG_PLLN (0x24) */ +#define NAU8810_PLLN_MASK 0xF +#define NAU8810_PLLMCLK_DIV2 (0x1 << 4) + +/* NAU8810_REG_PLLK1 (0x25) */ +#define NAU8810_PLLK1_MASK 0x3F + +/* NAU8810_REG_PLLK2 (0x26) */ +#define NAU8810_PLLK2_MASK 0x1FF + +/* NAU8810_REG_PLLK3 (0x27) */ +#define NAU8810_PLLK3_MASK 0x1FF + +/* NAU8810_REG_INPUT_SIGNAL (0x2C) */ +#define NAU8810_PMICPGA_SFT 0 +#define NAU8810_NMICPGA_SFT 1 + +/* NAU8810_REG_PGAGAIN (0x2D) */ +#define NAU8810_PGAGAIN_SFT 0 +#define NAU8810_PGAMT_SFT 6 +#define NAU8810_PGAZC_SFT 7 + +/* NAU8810_REG_ADCBOOST (0x2F) */ +#define NAU8810_PMICBSTGAIN_SFT 4 +#define NAU8810_PGABST_SFT 8 + +/* NAU8810_REG_SPKMIX (0x32) */ +#define NAU8810_DACSPK_SFT 0 +#define NAU8810_BYPSPK_SFT 1 + +/* NAU8810_REG_SPKGAIN (0x36) */ +#define NAU8810_SPKGAIN_SFT 0 +#define NAU8810_SPKMT_SFT 6 +#define NAU8810_SPKZC_SFT 7 + +/* NAU8810_REG_MONOMIX (0x38) */ +#define NAU8810_DACMOUT_SFT 0 +#define NAU8810_BYPMOUT_SFT 1 +#define NAU8810_MOUTMXMT_SFT 6 + + +/* Clock divider Id's */ +enum { + NAU8810_MCLK_DIV_PLL, + NAU8810_MCLK_DIV_MCLK, + NAU8810_BCLK_DIV, +}; + +struct nau8810 { + struct device *dev; + struct regmap *regmap; + int sysclk; + int div_id; +}; + +#endif -- 2.6.4

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[alsa-devel] [PATCH 0/7] ASoC: simple-card: add parse_clk / parse_dai
by Kuninori Morimoto 08 Aug '16

08 Aug '16

Hi Mark These add parse_clk / parse_dai to simple utiles. I know that we want to use "devm_" version of of_clk_get(), and now I'm posting its patch to kernel ML, but it still under discussion. Thus, this patch is using current style (with small fixup). I will replace it to devm version if it was accepted. Kuninori Morimoto (7): ASoC: simple-card-utils: add asoc_simple_card_parse_clk() ASoC: simple-card: use asoc_simple_card_parse_clk() ASoC: rsrc-card: use asoc_simple_card_parse_clk() ASoC: simple-card-utils: add asoc_simple_card_parse_dai() ASoC: simple-card: use asoc_simple_card_parse_dai() ASoC: rsrc-card: use asoc_simple_card_parse_dai() ASoC: simple-card: remove asoc_simple_card_sub_parse_of() include/sound/simple_card_utils.h | 25 ++++++++ sound/soc/generic/simple-card-utils.c | 69 ++++++++++++++++++++ sound/soc/generic/simple-card.c | 116 ++++++++++------------------------ sound/soc/sh/rcar/rsrc-card.c | 93 ++++++--------------------- 4 files changed, 146 insertions(+), 157 deletions(-) -- 1.9.1

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[alsa-devel] [PATCH v4 1/4] mfd: Add DT bindings documentation for Samsung Exynos LPASS
by Sylwester Nawrocki 05 Aug '16

05 Aug '16

This patch adds documentation of the DT bindings for the Samsung Exynos SoC Low Power Audio Subsystem. Signed-off-by: Sylwester Nawrocki <s.nawrocki(a)samsung.com> --- There were few rather significant additions since v3 and I had to drop tags: Acked-by: Rob Herring <robh(a)kernel.org> Acked-by: Krzysztof Kozlowski <k.kozlowski(a)samsung.com> Changes since v3: - moved to Documentation/devicetree/bindings/mfd, - added #address-cells, #size-cells, ranges as required properties, - added description of the IP block subnodes and links to their binding's documentation. Changes since v2: - none. --- .../bindings/mfd/samsung,exynos5433-lpass.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt new file mode 100644 index 0000000..7e97c0d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt @@ -0,0 +1,21 @@ + +Samsung Exynos SoC Low Power Audio Subsystem (LPASS) + +Required properties: + + - compatible : "samsung,exynos5433-lpass" + - reg : should contain the LPASS top SFR region location and size + - samsung,pmu-syscon : the phandle to the Power Management Unit node + - #address-cells: should be 1 + - #size-cells: should be 1 + - ranges: must be present + +Each IP block of the Low Power Audio Subsystem should be specified +as an optional sub-node. For "samsung,exynos5433-lpass" compatible +this includes: UART, SLIMBUS, PCM, I2S, DMAC, Timers 0...4, WDT 0...1 +devices. + +Bindings of the sub-nodes are described in: + Documentation/devicetree/bindings/serial/samsung_uart.txt + Documentation/devicetree/bindings/sound/samsung-i2s.txt + Documentation/devicetree/bindings/dma/arm-pl330.txt -- 1.9.1

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