November 2016 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [PATCH 0/2] ASoC: tlv320aic31xx: Support for tlv320dac3101
by Peter Ujfalusi 12 Nov '16

12 Nov '16

Hi, Adding missing compatible declaration for dac3100 and add support for dac3101. Regards, Peter --- Peter Ujfalusi (2): ASoC: tlv320aic31xx: Add missing of_device_id for dac3100 ASoC: tlv320aic31xx: Add support for tlv320dac3101 Documentation/devicetree/bindings/sound/tlv320aic31xx.txt | 1 + sound/soc/codecs/tlv320aic31xx.c | 3 +++ sound/soc/codecs/tlv320aic31xx.h | 1 + 3 files changed, 5 insertions(+) -- 2.10.2

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[alsa-devel] [PATCH 1/1 linux-next] ALSA: opl4: don't opencode IS_REACHABLE()
by Fabian Frederick 12 Nov '16

12 Nov '16

Signed-off-by: Fabian Frederick <fabf(a)skynet.be> --- sound/drivers/opl4/opl4_lib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/drivers/opl4/opl4_lib.c b/sound/drivers/opl4/opl4_lib.c index 89c7aa0..240656e 100644 --- a/sound/drivers/opl4/opl4_lib.c +++ b/sound/drivers/opl4/opl4_lib.c @@ -153,7 +153,7 @@ static int snd_opl4_detect(struct snd_opl4 *opl4) return 0; } -#if defined(CONFIG_SND_SEQUENCER) || (defined(MODULE) && defined(CONFIG_SND_SEQUENCER_MODULE)) +#if IS_REACHABLE(CONFIG_SND_SEQUENCER) static void snd_opl4_seq_dev_free(struct snd_seq_device *seq_dev) { struct snd_opl4 *opl4 = seq_dev->private_data; @@ -249,7 +249,7 @@ int snd_opl4_create(struct snd_card *card, snd_opl4_create_mixer(opl4); snd_opl4_create_proc(opl4); -#if defined(CONFIG_SND_SEQUENCER) || (defined(MODULE) && defined(CONFIG_SND_SEQUENCER_MODULE)) +#if IS_REACHABLE(CONFIG_SND_SEQUENCER) opl4->seq_client = -1; if (opl4->hardware < OPL3_HW_OPL4_ML) snd_opl4_create_seq_dev(opl4, seq_device); -- 2.7.4

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[alsa-devel] [RFC 00/17] clk: Add per-controller locks to fix deadlocks
by Krzysztof Kozlowski 12 Nov '16

12 Nov '16

Hi, RFC, please, do not apply, maybe except patch #1 which is harmless. Introduction ============ The patchset brings new entity: clock controller representing a hardware block. The clock controller comes with its own prepare lock which is used then in many places. The idea is to fix the deadlock mentioned in commit 10ff4c5239a1 ("i2c: exynos5: Fix possible ABBA deadlock by keeping I2C clock prepared") and commit 34e81ad5f0b6 ("i2c: s3c2410: fix ABBA deadlock by keeping clock prepared"). Disclaimer ========== Request for comments, so: 1. Only exynos_defconfig builds, 2. A lot of FIXME/TODO note still, 3. Checkpatch not run, lines not aligned, 4. Other (non-exynos) drivers not converted, 5. Probably not yet bisectable, 6. Locking became quite complex. The previous one lock was simple. Inefficient and dead-lock prone but simple. Because of clock hierarchy spanning through controllers, the new locking became quite complicated. I don't like it but... Details ======= In Exynos-based boards case the deadlock occurs between clock's prepare_lock and regmap-i2c's lock: CPU #0: CPU #1: lock(regmap) s2mps11-clk: clk_prepare_lock() i2c-exynos: clk_prepare_lock() - wait lock(regmap) - wait The clk_prepare_lock() on both CPUs come from different clock drivers and components: 1. I2C clock is part of SoC block and is required by i2c-s3c2410/i2c-exynos5 driver, 2. S2MPS11 clock is separate device, however driver uses I2C regmap. The deadlock was reported by lockdep (always) and was happening in 20% of boots of Odroid XU3 with multi_v7 defconfig. Workaround for deadlock was implemented by removing prepare/unprepare calls from I2C transfers. However these are just workarounds... which after applying this patch can be reverted. Additionally Marek Szyprowski's work on domains/clocks/pinctrl exposed the deadlock again in different configuration. Comments as usual are welcomed. Best regards, Krzysztof Krzysztof Kozlowski (17): clk: bcm2835: Rename clk_register to avoid name conflict clk: Add clock controller to fine-grain the prepare lock clk: s2mps11: Switch to new clock controller API clk: samsung: Allocate a clock controller in context clk: fixed-rate: Switch to new clock controller API clk: gate: Switch to new clock controller API clk: mux: Switch to new clock controller API clk: fixed-factor: Switch to new clock controller API clk: divider: Switch to new clock controller API clk: composite: Switch to new clock controller API clk: gpio: Switch to new clock controller API ASoC: samsung: Switch to new clock controller API clk: samsung: audss: samsung: Switch to new clock controller API clk: samsung: clkout: samsung: Switch to new clock controller API clk: Use per-controller locking Revert "i2c: exynos5: Fix possible ABBA deadlock by keeping I2C clock prepared" Revert "i2c: s3c2410: fix ABBA deadlock by keeping clock prepared" drivers/clk/bcm/clk-bcm2835.c | 8 +- drivers/clk/clk-composite.c | 8 +- drivers/clk/clk-divider.c | 10 +- drivers/clk/clk-fixed-factor.c | 11 +- drivers/clk/clk-fixed-rate.c | 28 +- drivers/clk/clk-fractional-divider.c | 5 +- drivers/clk/clk-gate.c | 8 +- drivers/clk/clk-gpio.c | 29 +- drivers/clk/clk-mux.c | 32 ++- drivers/clk/clk-s2mps11.c | 10 +- drivers/clk/clk.c | 456 +++++++++++++++++++++++++++----- drivers/clk/samsung/clk-exynos-audss.c | 30 ++- drivers/clk/samsung/clk-exynos-clkout.c | 11 +- drivers/clk/samsung/clk.c | 25 +- drivers/clk/samsung/clk.h | 1 + drivers/i2c/busses/i2c-exynos5.c | 24 +- drivers/i2c/busses/i2c-s3c2410.c | 23 +- include/linux/clk-provider.h | 88 ++++-- include/linux/clk.h | 1 + sound/soc/samsung/i2s.c | 13 +- 20 files changed, 612 insertions(+), 209 deletions(-) -- 1.9.1

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[alsa-devel] [asoc:topic/arizona 10/13] sound/soc/codecs/wm_adsp.c:758:8: error: implicit declaration of function 'wm_coeff_base_reg'
by kbuild test robot 11 Nov '16

11 Nov '16

tree: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git topic/arizona head: a23ebba845fee07cce00659c06844845b24da290 commit: f4f0c4c60c3959a8f3650850b799049161732e91 [10/13] ASoC: wm_adsp: Signal firmware shutdown through event control config: x86_64-allmodconfig (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901 reproduce: git checkout f4f0c4c60c3959a8f3650850b799049161732e91 # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): include/linux/compiler.h:253:8: sparse: attribute 'no_sanitize_address': unknown attribute sound/soc/codecs/wm_adsp.c:758:15: sparse: undefined identifier 'wm_coeff_base_reg' sound/soc/codecs/wm_adsp.c:762:9: sparse: undefined identifier 'wm_adsp_mem_region_name' sound/soc/codecs/wm_adsp.c:802:9: sparse: undefined identifier 'wm_adsp_mem_region_name' sound/soc/codecs/wm_adsp.c:1112:24: sparse: no member 'type' in struct wm_coeff_ctl sound/soc/codecs/wm_adsp.c: In function 'wm_coeff_write_acked_control': >> sound/soc/codecs/wm_adsp.c:758:8: error: implicit declaration of function 'wm_coeff_base_reg' [-Werror=implicit-function-declaration] ret = wm_coeff_base_reg(ctl, &reg); ^~~~~~~~~~~~~~~~~ In file included from include/linux/printk.h:305:0, from include/linux/kernel.h:13, from include/linux/list.h:8, from include/linux/module.h:9, from sound/soc/codecs/wm_adsp.c:13: sound/soc/codecs/wm_adsp.c:764:4: error: implicit declaration of function 'wm_adsp_mem_region_name' [-Werror=implicit-function-declaration] wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); ^ include/linux/dynamic_debug.h:135:9: note: in definition of macro 'dynamic_dev_dbg' ##__VA_ARGS__); \ ^~~~~~~~~~~ sound/soc/codecs/wm_adsp.c:46:2: note: in expansion of macro 'dev_dbg' dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) ^~~~~~~ sound/soc/codecs/wm_adsp.c:762:2: note: in expansion of macro 'adsp_dbg' adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", ^~~~~~~~ sound/soc/codecs/wm_adsp.c:46:21: warning: format '%s' expects argument of type 'char *', but argument 7 has type 'int' [-Wformat=] dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) ^ include/linux/dynamic_debug.h:134:39: note: in definition of macro 'dynamic_dev_dbg' __dynamic_dev_dbg(&descriptor, dev, fmt, \ ^~~ sound/soc/codecs/wm_adsp.c:46:2: note: in expansion of macro 'dev_dbg' dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) ^~~~~~~ sound/soc/codecs/wm_adsp.c:762:2: note: in expansion of macro 'adsp_dbg' adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", ^~~~~~~~ sound/soc/codecs/wm_adsp.c:42:22: warning: format '%s' expects argument of type 'char *', but argument 6 has type 'int' [-Wformat=] dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) ^ sound/soc/codecs/wm_adsp.c:802:2: note: in expansion of macro 'adsp_warn' adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", ^~~~~~~~~ sound/soc/codecs/wm_adsp.c: In function 'wm_adsp_signal_event_controls': sound/soc/codecs/wm_adsp.c:1112:10: error: 'struct wm_coeff_ctl' has no member named 'type' if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT) ^~ cc1: some warnings being treated as errors vim +/wm_coeff_base_reg +758 sound/soc/codecs/wm_adsp.c 752 { 753 struct wm_adsp *dsp = ctl->dsp; 754 u32 val = cpu_to_be32(event_id); 755 unsigned int reg; 756 int i, ret; 757 > 758 ret = wm_coeff_base_reg(ctl, &reg); 759 if (ret) 760 return ret; 761 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation

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[alsa-devel] [PATCH] ASoC: doc: ReSTize codec_to_codec.txt
by Takashi Iwai 11 Nov '16

11 Nov '16

Yet another simple conversion from a plain text file. Renamed to codec-to-codec.rst to align with others. Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- Mark, this is the rest one in your branch, which I pulled now. It's already in topic/restize-docs branch, so I can merge to for-next as is if it's OK. .../codec_to_codec.txt => soc/codec-to-codec.rst} | 79 ++++++++++++---------- Documentation/sound/soc/index.rst | 1 + 2 files changed, 43 insertions(+), 37 deletions(-) rename Documentation/sound/{alsa/soc/codec_to_codec.txt => soc/codec-to-codec.rst} (68%) diff --git a/Documentation/sound/alsa/soc/codec_to_codec.txt b/Documentation/sound/soc/codec-to-codec.rst similarity index 68% rename from Documentation/sound/alsa/soc/codec_to_codec.txt rename to Documentation/sound/soc/codec-to-codec.rst index 704a6483652c..810109d7500d 100644 --- a/Documentation/sound/alsa/soc/codec_to_codec.txt +++ b/Documentation/sound/soc/codec-to-codec.rst @@ -1,37 +1,41 @@ +============================================== Creating codec to codec dai link for ALSA dapm -=================================================== +============================================== Mostly the flow of audio is always from CPU to codec so your system will look as below: +:: - --------- --------- -| | dai | | - CPU -------> codec -| | | | - --------- --------- + --------- --------- + | | dai | | + CPU -------> codec + | | | | + --------- --------- In case your system looks as below: - --------- - | | - codec-2 - | | - --------- - | - dai-2 - | - ---------- --------- -| | dai-1 | | - CPU -------> codec-1 -| | | | - ---------- --------- - | - dai-3 - | - --------- - | | - codec-3 - | | - --------- +:: + + --------- + | | + codec-2 + | | + --------- + | + dai-2 + | + ---------- --------- + | | dai-1 | | + CPU -------> codec-1 + | | | | + ---------- --------- + | + dai-3 + | + --------- + | | + codec-3 + | | + --------- Suppose codec-2 is a bluetooth chip and codec-3 is connected to a speaker and you have a below scenario: @@ -42,20 +46,21 @@ connection should be used. Your dai_link should appear as below in your machine file: +:: -/* - * this pcm stream only supports 24 bit, 2 channel and - * 48k sampling rate. - */ -static const struct snd_soc_pcm_stream dsp_codec_params = { + /* + * this pcm stream only supports 24 bit, 2 channel and + * 48k sampling rate. + */ + static const struct snd_soc_pcm_stream dsp_codec_params = { .formats = SNDRV_PCM_FMTBIT_S24_LE, .rate_min = 48000, .rate_max = 48000, .channels_min = 2, .channels_max = 2, -}; + }; -{ + { .name = "CPU-DSP", .stream_name = "CPU-DSP", .cpu_dai_name = "samsung-i2s.0", @@ -66,8 +71,8 @@ static const struct snd_soc_pcm_stream dsp_codec_params = { | SND_SOC_DAIFMT_CBM_CFM, .ignore_suspend = 1, .params = &dsp_codec_params, -}, -{ + }, + { .name = "DSP-CODEC", .stream_name = "DSP-CODEC", .cpu_dai_name = "wm0010-sdi2", @@ -77,7 +82,7 @@ static const struct snd_soc_pcm_stream dsp_codec_params = { | SND_SOC_DAIFMT_CBM_CFM, .ignore_suspend = 1, .params = &dsp_codec_params, -}, + }, Above code snippet is motivated from sound/soc/samsung/speyside.c. diff --git a/Documentation/sound/soc/index.rst b/Documentation/sound/soc/index.rst index e142a0f25c5b..e57df2dab2fd 100644 --- a/Documentation/sound/soc/index.rst +++ b/Documentation/sound/soc/index.rst @@ -17,3 +17,4 @@ The documentation is spilt into the following sections:- clocking jack dpcm + codec-to-codec -- 2.10.2

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[alsa-devel] [PATCH] ALSA: hda - Fix mic regression by ASRock mobo fixup
by Takashi Iwai 11 Nov '16

11 Nov '16

The commit [1a3f099101b8: ALSA: hda - Fix surround output pins for ASRock B150M mobo] introduced a fixup of pin configs for ASRock mobos to fix the surround outputs. However, this overrides the pin configs of the mic pins as if they are outputs-only, effectively disabling the mic inputs. Of course, it's a regression wrt mic functionality. Actually the pins 0x18 and 0x1a don't need to be changed; we just need to disable the bogus pins 0x14 and 0x15. Then the auto-parser will pick up mic pins as switchable and assign the surround outputs there. This patch removes the incorrect pin overrides of NID 0x18 and 0x1a from the ASRock fixup. Fixes: 1a3f099101b8 ('ALSA: hda - Fix surround output pins for ASRock...') Reported-and-tested-by: Vitor Antunes <vitor.hda(a)gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=187431 Cc: <stable(a)vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai(a)suse.de> --- sound/pci/hda/patch_realtek.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 2f909dd8b7b8..ea81c08ddc7a 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -6907,8 +6907,6 @@ static const struct hda_fixup alc662_fixups[] = { .v.pins = (const struct hda_pintbl[]) { { 0x15, 0x40f000f0 }, /* disabled */ { 0x16, 0x40f000f0 }, /* disabled */ - { 0x18, 0x01014011 }, /* LO */ - { 0x1a, 0x01014012 }, /* LO */ { } } }, -- 2.10.2

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[alsa-devel] [PATCH 00/10] ASoC: Modernize documents
by Takashi Iwai 11 Nov '16

11 Nov '16

Hi, this patchset converts the ASoC text documents to ReST format, which has been recently introduced to the kernel tree. The conversions are really simple since the original texts were already well formatted. The files are moved to Documentation/sound/soc, and TOC is to the index page. All the patches are found in topic/rest-docs branch of sound git tree. The new file after 4.9 isn't covered yet, as the branch is based on 4.9-rc4. I found only soc/codec_to_codec.txt in linux-next, and it seems easy to convert. Mark, let me know how you'd like to organize. I can pull your branch and convert in my side, or you pull mine and do it on yours. thanks, Takashi === Takashi Iwai (10): ASoC: doc: ReSTize overview.txt ASoC: doc: ReSTize codec.txt ASoC: doc: ReSTize DAI.txt ASoC: doc: ReSTize dapm.txt ASoC: doc: ReSTize platform.txt ASoC: doc: ReSTize machine.txt ASoC: doc: ReSTize pops_clicks.txt ASoC: doc: ReSTize clocking.txt ASoC: doc: ReSTize jack.txt ASoC: doc: ReSTize DPCM.txt Documentation/sound/index.rst | 1 + .../{alsa/soc/clocking.txt => soc/clocking.rst} | 13 +- .../sound/{alsa/soc/codec.txt => soc/codec.rst} | 75 +++--- .../sound/{alsa/soc/DAI.txt => soc/dai.rst} | 28 ++- .../sound/{alsa/soc/dapm.txt => soc/dapm.rst} | 249 ++++++++++-------- .../sound/{alsa/soc/DPCM.txt => soc/dpcm.rst} | 280 +++++++++++---------- Documentation/sound/soc/index.rst | 19 ++ .../sound/{alsa/soc/jack.txt => soc/jack.rst} | 1 + .../{alsa/soc/machine.txt => soc/machine.rst} | 22 +- .../{alsa/soc/overview.txt => soc/overview.rst} | 32 +-- .../{alsa/soc/platform.txt => soc/platform.rst} | 31 +-- .../soc/pops_clicks.txt => soc/pops-clicks.rst} | 15 +- 12 files changed, 417 insertions(+), 349 deletions(-) rename Documentation/sound/{alsa/soc/clocking.txt => soc/clocking.rst} (94%) rename Documentation/sound/{alsa/soc/codec.txt => soc/codec.rst} (84%) rename Documentation/sound/{alsa/soc/DAI.txt => soc/dai.rst} (71%) rename Documentation/sound/{alsa/soc/dapm.txt => soc/dapm.rst} (62%) rename Documentation/sound/{alsa/soc/DPCM.txt => soc/dpcm.rst} (57%) create mode 100644 Documentation/sound/soc/index.rst rename Documentation/sound/{alsa/soc/jack.txt => soc/jack.rst} (99%) rename Documentation/sound/{alsa/soc/machine.txt => soc/machine.rst} (90%) rename Documentation/sound/{alsa/soc/overview.txt => soc/overview.rst} (83%) rename Documentation/sound/{alsa/soc/platform.txt => soc/platform.rst} (81%) rename Documentation/sound/{alsa/soc/pops_clicks.txt => soc/pops-clicks.rst} (87%) -- 2.10.2

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[alsa-devel] Applied "ASoC: nau8825: Disable short Frame Sync detection logic" to the asoc tree
by Mark Brown 11 Nov '16

11 Nov '16

The patch ASoC: nau8825: Disable short Frame Sync detection logic has been applied to the asoc tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 93dfec758ff2d0292be35cafd239e929a8973b73 Mon Sep 17 00:00:00 2001 From: John Hsu <KCHSU0(a)nuvoton.com> Date: Fri, 11 Nov 2016 12:34:12 +0800 Subject: [PATCH] ASoC: nau8825: Disable short Frame Sync detection logic If the short Frame Sync detection logic enabled, the logic will check the short frame sync threshold. If frame sync is less than the setting; for example, frame sync less than 252 MCLK, the short frame sync signal is flagged, digital filter temporary mute and skip that data. If the system was intended for sampling rate change which could create temporary short frame sync and not enough MIPS to run the digital filter. But the situation doesn't happen in ALSA architecure. Thus the Frame Sync is always stable, then no require to do the detection. Therefore, the dirver disables the function for better performance. Signed-off-by: John Hsu <KCHSU0(a)nuvoton.com> Signed-off-by: Mark Brown <broonie(a)kernel.org> --- sound/soc/codecs/nau8825.c | 3 +++ sound/soc/codecs/nau8825.h | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c index e643be91d762..0db618b2f2b8 100644 --- a/sound/soc/codecs/nau8825.c +++ b/sound/soc/codecs/nau8825.c @@ -1811,6 +1811,9 @@ static void nau8825_init_regs(struct nau8825 *nau8825) NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L); regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R); + /* Disable short Frame Sync detection logic */ + regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT, + NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET); } static const struct regmap_config nau8825_regmap_config = { diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h index 1c63e2abafa9..6365c9c3f8d9 100644 --- a/sound/soc/codecs/nau8825.h +++ b/sound/soc/codecs/nau8825.h @@ -246,6 +246,11 @@ #define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT) #define NAU8825_I2S_BLK_DIV_MASK 0x7 +/* LEFT_TIME_SLOT (0x1e) */ +#define NAU8825_FS_ERR_CMP_SEL_SFT 14 +#define NAU8825_FS_ERR_CMP_SEL_MASK (0x3 << NAU8825_FS_ERR_CMP_SEL_SFT) +#define NAU8825_DIS_FS_SHORT_DET (1 << 13) + /* BIQ_CTRL (0x20) */ #define NAU8825_BIQ_WRT_SFT 4 #define NAU8825_BIQ_WRT_EN (1 << NAU8825_BIQ_WRT_SFT) -- 2.10.2

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[alsa-devel] [PATCH] ASoC: nau8825: AD/DA over sampling rate configuration
by John Hsu 11 Nov '16

11 Nov '16

Over Sampling Rate (OSR) is defined as CLK_ADC frequency divided by the audio sample rate (Fs). OSR = CLK_ADC / FS The available OSRs are 32, 64, 128 or 256. Note that the OSR and Fs values must be selected such that the maximum frequency of CLK_ADC is less than 6.144 MHz. It is recommended to match the relationship between OSR and clock SRC according to following Table. ADC_RATE: 00(OSR=32) | CLK_ADC_SRC: 11(CODEC 1/8) ADC_RATE: 01(OSR=64) | CLK_ADC_SRC: 10(CODEC1/4) ADC_RATE: 10(OSR=128) | CLK_ADC_SRC: 01(CODEC 1/2) ADC_RATE: 11(OSR=256) | CLK_ADC_SRC: 00(CODEC CLK) The over sampling rate about DAC follows the same rule with ADCs. The driver changes the OSR to 64 value when initiation for better FLL performance and applies the dynamic SRC change by different OSR. Signed-off-by: John Hsu <KCHSU0(a)nuvoton.com> --- sound/soc/codecs/nau8825.c | 78 ++++++++++++++++++++++++++++++++++++++++++++-- sound/soc/codecs/nau8825.h | 4 +++ 2 files changed, 79 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c index e643be9..d74f642 100644 --- a/sound/soc/codecs/nau8825.c +++ b/sound/soc/codecs/nau8825.c @@ -43,6 +43,8 @@ #define GAIN_AUGMENT 22500 #define SIDETONE_BASE 207000 +/* the maximum frequency of CLK_ADC and CLK_DAC */ +#define CLK_DA_AD_MAX 6144000 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, unsigned int freq); @@ -95,6 +97,27 @@ static const struct nau8825_fll_attr fll_pre_scalar[] = { { 8, 0x3 }, }; +/* over sampling rate */ +struct nau8825_osr_attr { + unsigned int osr; + unsigned int clk_src; +}; + +static const struct nau8825_osr_attr osr_dac_sel[] = { + { 64, 2 }, /* OSR 64, SRC 1/4 */ + { 256, 0 }, /* OSR 256, SRC 1 */ + { 128, 1 }, /* OSR 128, SRC 1/2 */ + { 0, 0 }, + { 32, 3 }, /* OSR 32, SRC 1/8 */ +}; + +static const struct nau8825_osr_attr osr_adc_sel[] = { + { 32, 3 }, /* OSR 32, SRC 1/8 */ + { 64, 2 }, /* OSR 64, SRC 1/4 */ + { 128, 1 }, /* OSR 128, SRC 1/2 */ + { 256, 0 }, /* OSR 256, SRC 1 */ +}; + static const struct reg_default nau8825_reg_defaults[] = { { NAU8825_REG_ENA_CTRL, 0x00ff }, { NAU8825_REG_IIC_ADDR_SET, 0x0 }, @@ -1179,16 +1202,65 @@ static const struct snd_soc_dapm_route nau8825_dapm_routes[] = { {"HPOR", NULL, "Class G"}, }; +static int nau8825_clock_check(struct nau8825 *nau8825, + int stream, int rate, int osr) +{ + int osrate; + + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (osr >= ARRAY_SIZE(osr_dac_sel)) + return -EINVAL; + osrate = osr_dac_sel[osr].osr; + } else { + if (osr >= ARRAY_SIZE(osr_adc_sel)) + return -EINVAL; + osrate = osr_adc_sel[osr].osr; + } + + if (!osrate || rate * osr > CLK_DA_AD_MAX) { + dev_err(nau8825->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n"); + return -EINVAL; + } + + return 0; +} + static int nau8825_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec); - unsigned int val_len = 0; + unsigned int val_len = 0, osr; nau8825_sema_acquire(nau8825, 2 * HZ); + /* CLK_DAC or CLK_ADC = OSR * FS + * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) + * multiplied by the audio sample rate (Fs). Note that the OSR and Fs + * values must be selected such that the maximum frequency is less + * than 6.144 MHz. + */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr); + osr &= NAU8825_DAC_OVERSAMPLE_MASK; + if (nau8825_clock_check(nau8825, substream->stream, + params_rate(params), osr)) + return -EINVAL; + regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, + NAU8825_CLK_DAC_SRC_MASK, + osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT); + } else { + regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr); + osr &= NAU8825_ADC_SYNC_DOWN_MASK; + if (nau8825_clock_check(nau8825, substream->stream, + params_rate(params), osr)) + return -EINVAL; + regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, + NAU8825_CLK_ADC_SRC_MASK, + osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT); + } + switch (params_width(params)) { case 16: val_len |= NAU8825_I2S_DL_16; @@ -1774,9 +1846,9 @@ static void nau8825_init_regs(struct nau8825 *nau8825) * (audible hiss). Set it to something better. */ regmap_update_bits(regmap, NAU8825_REG_ADC_RATE, - NAU8825_ADC_SYNC_DOWN_MASK, NAU8825_ADC_SYNC_DOWN_128); + NAU8825_ADC_SYNC_DOWN_MASK, NAU8825_ADC_SYNC_DOWN_64); regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, - NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_128); + NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64); /* Disable DACR/L power */ regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h index 1c63e2a..58ea95b 100644 --- a/sound/soc/codecs/nau8825.h +++ b/sound/soc/codecs/nau8825.h @@ -115,6 +115,10 @@ #define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) #define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) #define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) +#define NAU8825_CLK_ADC_SRC_SFT 6 +#define NAU8825_CLK_ADC_SRC_MASK (0x3 << NAU8825_CLK_ADC_SRC_SFT) +#define NAU8825_CLK_DAC_SRC_SFT 4 +#define NAU8825_CLK_DAC_SRC_MASK (0x3 << NAU8825_CLK_DAC_SRC_SFT) #define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0) /* FLL1 (0x04) */ -- 2.6.4

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[alsa-devel] [PATCH] ASoC: nau8825: FLL parameters finetune
by John Hsu 11 Nov '16

11 Nov '16

The driver fine-tune some parameters to improve FLL performance. Those items have description as follow. (1)ICTRL_LATCH: FLL DSP speed capability control When FLL running at high frequency with long decimal number, DSP needs to operate at high speed. FLL DSP can optimize between performance and power consumption by ICTRL_LATCH.(111 has highest power consumption.) The default setting can be used to reduce power. (2)CUTOFF500: loop filter cutoff frequency at 500Khz It will give the best FLL performance but highest power consumption to enable the cutoff frequency. FLL Loop Filter enable to reduce FLL output noise, especially,(DCO frequency)/(FLL input reference frequency) is not a integer. (3)GAIN_ERR: FLL gain error correction threshold setting The threshold is comparison between DCO and target frequency. The value 1111 has the most sensitive threshold, that is, 1111 can have the most accurate DCO to target frequency. However, the gain error setting conditionally and inversely depends on FLL input reference clock rate. Higher FLL reference input frequency can only set lower gain error, such as 0000 for input reference from MCLK=12.288Mhz. On the other side, if FLL reference input is from Frame Sync, 48KHz, higher error gain can apply such as 1111. Signed-off-by: John Hsu <KCHSU0(a)nuvoton.com> --- sound/soc/codecs/nau8825.c | 48 ++++++++++++++++++++++++++++++++++++++-------- sound/soc/codecs/nau8825.h | 5 +++++ 2 files changed, 45 insertions(+), 8 deletions(-) diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c index d74f642..8f2608a 100644 --- a/sound/soc/codecs/nau8825.c +++ b/sound/soc/codecs/nau8825.c @@ -1991,8 +1991,10 @@ static void nau8825_fll_apply(struct nau8825 *nau8825, regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK, NAU8825_CLK_SRC_MCLK | fll_param->mclk_src); + /* Make DSP operate at high speed for better performance. */ regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, - NAU8825_FLL_RATIO_MASK, fll_param->ratio); + NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK, + fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT)); /* FLL 16-bit fractional input */ regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac); /* FLL 10-bit integer input */ @@ -2008,19 +2010,22 @@ static void nau8825_fll_apply(struct nau8825 *nau8825, regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 0); if (fll_param->fll_frac) { + /* set FLL loop filter enable and cutoff frequency at 500Khz */ regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | NAU8825_FLL_FTR_SW_FILTER); regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, - NAU8825_SDM_EN, NAU8825_SDM_EN); + NAU8825_SDM_EN | NAU8825_CUTOFF500, + NAU8825_SDM_EN | NAU8825_CUTOFF500); } else { + /* disable FLL loop filter and cutoff frequency */ regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU); - regmap_update_bits(nau8825->regmap, - NAU8825_REG_FLL6, NAU8825_SDM_EN, 0); + regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, + NAU8825_SDM_EN | NAU8825_CUTOFF500, 0); } } @@ -2086,6 +2091,9 @@ static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap) NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK); regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 0); + /* Make DSP operate as default setting for power saving. */ + regmap_update_bits(regmap, NAU8825_REG_FLL1, + NAU8825_ICTRL_LATCH_MASK, 0); } static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, @@ -2129,10 +2137,13 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, NAU8825_DCO_EN, NAU8825_DCO_EN); regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); - /* Decrease the VCO frequency for power saving */ + /* Decrease the VCO frequency and make DSP operate + * as default setting for power saving. + */ regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, NAU8825_CLK_MCLK_SRC_MASK, 0xf); regmap_update_bits(regmap, NAU8825_REG_FLL1, + NAU8825_ICTRL_LATCH_MASK | NAU8825_FLL_RATIO_MASK, 0x10); regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_SDM_EN, NAU8825_SDM_EN); @@ -2156,8 +2167,13 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, * preparation halted until cross talk process finish. */ nau8825_sema_acquire(nau8825, 2 * HZ); + /* Higher FLL reference input frequency can only set lower + * gain error, such as 0000 for input reference from MCLK + * 12.288Mhz. + */ regmap_update_bits(regmap, NAU8825_REG_FLL3, - NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_MCLK); + NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, + NAU8825_FLL_CLK_SRC_MCLK | 0); /* Release the semaphone. */ nau8825_sema_release(nau8825); @@ -2173,8 +2189,16 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, * preparation halted until cross talk process finish. */ nau8825_sema_acquire(nau8825, 2 * HZ); + /* If FLL reference input is from low frequency source, + * higher error gain can apply such as 0xf which has + * the most sensitive gain error correction threshold, + * Therefore, FLL has the most accurate DCO to + * target frequency. + */ regmap_update_bits(regmap, NAU8825_REG_FLL3, - NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_BLK); + NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, + NAU8825_FLL_CLK_SRC_BLK | + (0xf << NAU8825_GAIN_ERR_SFT)); /* Release the semaphone. */ nau8825_sema_release(nau8825); @@ -2191,8 +2215,16 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, * preparation halted until cross talk process finish. */ nau8825_sema_acquire(nau8825, 2 * HZ); + /* If FLL reference input is from low frequency source, + * higher error gain can apply such as 0xf which has + * the most sensitive gain error correction threshold, + * Therefore, FLL has the most accurate DCO to + * target frequency. + */ regmap_update_bits(regmap, NAU8825_REG_FLL3, - NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_FS); + NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, + NAU8825_FLL_CLK_SRC_FS | + (0xf << NAU8825_GAIN_ERR_SFT)); /* Release the semaphone. */ nau8825_sema_release(nau8825); diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h index 58ea95b..46cd1a6 100644 --- a/sound/soc/codecs/nau8825.h +++ b/sound/soc/codecs/nau8825.h @@ -122,9 +122,13 @@ #define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0) /* FLL1 (0x04) */ +#define NAU8825_ICTRL_LATCH_SFT 10 +#define NAU8825_ICTRL_LATCH_MASK (0x7 << NAU8825_ICTRL_LATCH_SFT) #define NAU8825_FLL_RATIO_MASK (0x7f << 0) /* FLL3 (0x06) */ +#define NAU8825_GAIN_ERR_SFT 12 +#define NAU8825_GAIN_ERR_MASK (0xf << NAU8825_GAIN_ERR_SFT) #define NAU8825_FLL_INTEGER_MASK (0x3ff << 0) #define NAU8825_FLL_CLK_SRC_SFT 10 #define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT) @@ -148,6 +152,7 @@ /* FLL6 (0x9) */ #define NAU8825_DCO_EN (0x1 << 15) #define NAU8825_SDM_EN (0x1 << 14) +#define NAU8825_CUTOFF500 (0x1 << 13) /* HSD_CTRL (0xc) */ #define NAU8825_HSD_AUTO_MODE (1 << 6) -- 2.6.4

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