July 2015 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] No stream timing info with alsa pulse plugin?
by sqweek 24 Sep '15

24 Sep '15

Hi guys, I discovered on my machine that alsa_snd_pcm_status_get_tstamp (and also get_htstamp) stop working when my asoundrc invokes the pulse plugin. That is, normally they work fine but once the sound is going via pulse the returned time stamp is always zero. I'm trying to understand why that is. I couldn't really find any discussion of the pulse plugin on the archives so I'm not entirely sure I've found the right list; I was directed here via the pulseaudio bugzilla[1]. [1] https://bugs.freedesktop.org/show_bug.cgi?id=88503 Thanks for any assistance! -sqweek

4 3

[alsa-devel] [PATCH RFC v2 0/7] Implement generic ASoC HDMI codec
by Jyri Sarha 20 Sep '15

20 Sep '15

Only the first three patches are meant for serious review. The ASoC part should be ready for review in other respects but the EDID SADs handling is waiting for Russell King's DRM ELD helper patches. There is a copy-pasted not-to-be-merged patch with the same functionality in the patch series. The tda998x part is not complete and I do not think Jean-Francois' binding are ready as such either. At least the usage of reg property in a port node for something that is not an address or even guaranteed to be unique is not a good idea. Some documentation of how to configure AP0-AP4 pins (REG_ENA_AP?) would help in making a proper binding for the tda998x audio configuration. These patches, my tilcdc refactoring[1], and my latest BCLK fixes for davinci-mcasp driver [2], can be found in a branch that produces working HDMI audio on Beaglebone-Black here: https://github.com/jsarha/linux.git linux-master-bbb-hdmi-20150512 [1] http://lists.freedesktop.org/archives/dri-devel/2015-May/082537.html [2] http://mailman.alsa-project.org/pipermail/alsa-devel/2015-April/090974.html Jean-Francois Moine (1): drm/i2c: tda998x: Add support of a DT graph of ports DO NOT MERGE Jyri Sarha (6): ASoC: core: If component doesn't have of_node use parent's node instead ASoC: hdmi: Remove obsolete dummy HDMI codec ASoC: hdmi-codec: Add hdmi-codec for external HDMI-encoders ASoC: hdmi-codec: Add ELD based audio pcm rules DO NOT MERGE drm/i2c: tda998x: Register ASoC HDMI codec for audio functionality DO NOT MERGE ARM: dts: am335x-boneblack: Add HDMI audio support DO NOT MERGE .../devicetree/bindings/drm/i2c/tda998x.txt | 51 ++ arch/arm/boot/dts/am335x-boneblack.dts | 78 ++- drivers/gpu/drm/i2c/Kconfig | 1 + drivers/gpu/drm/i2c/tda998x_drv.c | 328 +++++++++++- include/sound/hdmi-codec.h | 99 ++++ include/sound/tda998x.h | 8 + sound/soc/codecs/Kconfig | 2 +- sound/soc/codecs/Makefile | 4 +- sound/soc/codecs/hdmi-codec.c | 560 +++++++++++++++++++++ sound/soc/codecs/hdmi.c | 109 ---- sound/soc/soc-core.c | 14 +- 11 files changed, 1129 insertions(+), 125 deletions(-) create mode 100644 include/sound/hdmi-codec.h create mode 100644 include/sound/tda998x.h create mode 100644 sound/soc/codecs/hdmi-codec.c delete mode 100644 sound/soc/codecs/hdmi.c -- 1.9.1

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[alsa-devel] [PATCH] ASoC: fsl_ssi: Fixing invalid fmt SND_SOC_DAIFMT_AC97 test
by Arnaud Mouiche 20 Sep '15

20 Sep '15

SND_SOC_DAIFMT_AC97 (6) has similar bits than SND_SOC_DAIFMT_DSP_A (4) and can't be tested with a simple AND operation Signed-off-by: Arnaud Mouiche <arnaud.mouiche(a)invoxia.com> --- sound/soc/fsl/fsl_ssi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 6b0c8f7..c25a1e8 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -249,7 +249,8 @@ MODULE_DEVICE_TABLE(of, fsl_ssi_ids); static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) { - return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97); + return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == + SND_SOC_DAIFMT_AC97; } static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private) @@ -945,7 +946,7 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev, CCSR_SSI_SCR_TCH_EN); } - if (fmt & SND_SOC_DAIFMT_AC97) + if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) fsl_ssi_setup_ac97(ssi_private); return 0; -- 1.9.1

2 1

[alsa-devel] Intel SST on a Bay Trail tablet
by Antonio Ospite 18 Sep '15

18 Sep '15

Hi, I am trying to get the Intel SST driver working on a Teclast X98 Air 3G [1], it's a Bay Trail tablet. The tests below have been made with 4.0.0-rc1 and the firmware files from https://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tr… The DSDT on this device is quite broken, and I am patching it to get stuff working. The audio device works just fine under Android, I don't know if that's because the Android kernel is ignoring the DSDT and is hard-coding some platform data. Anyhow, with the untouched DSDT[2] I was getting this message in dmesg[3]: [ 11.344095] platform byt-rt5640: Driver byt-rt5640 requests probe deferral [ 11.404831] resource sanity check: requesting [mem 0x91000000-0x911fffff], which spans more than ADMA0F28:00 [mem 0x91000000-0x91000fff] [ 11.404833] ------------[ cut here ]------------ [ 11.404849] WARNING: CPU: 0 PID: 213 at arch/x86/mm/ioremap.c:197 __ioremap_caller+0x22c/0x350() ... I guessed this was because the DSDT defined an ADMA0F28 device with a memory resource overlapping with the LPMA device. So I removed the overlapping resources (ADMA0F28 and SSPX0000) in the DSDT and then the driver attempted to boot the audio device but failed with this message in dmesg[4]: [ 11.602291] baytrail-pcm-audio baytrail-pcm-audio: ipc: error DSP boot timeout ... Then I noticed that the Interrupt resources of the LPMA device were out of order in the DSDT, so I put the Interrupt 0x18 as the first one[5] and now the driver can boot the device and upload the firmware to it[6]: [ 11.433460] baytrail-pcm-audio baytrail-pcm-audio: FW version: 04.05.13.a0 [ 11.433468] baytrail-pcm-audio baytrail-pcm-audio: Build type: a0 [ 11.433473] baytrail-pcm-audio baytrail-pcm-audio: Build date: Apr 2 2014 14:14:39 [ 11.448257] byt-rt5640 byt-rt5640: rt5640-aif1 <-> baytrail-pcm-audio mapping ok ... But still no sound. I can see the mixer controls in alsamixer and I tried to initialize them copying from the alsactl output from the Android kernel[7], but no, still no sound. I do not know if that matters, but the driver still emits this message: [ 11.398304] baytrail-pcm-audio baytrail-pcm-audio: error: invalid DMA engine 0 [ 11.398314] baytrail-pcm-audio baytrail-pcm-audio: sst_dma_new failed -22 ... I noticed that on the Android kernel[8] the DMA channels for the ADMA0F28 device are actually configured, the intel_mid_dma driver sets up 4 channels for it along with 2 x 6 channels for the INTL9C60 device. On the mainline kernel only the INTL9C60 device gets configured, by the dw_dmac driver and with 2 x 8 channels. I do not know much about these details tho. Also, the codec driver on the Android kernel (byt_rt5642) seems to use one GPIO as an interrupt[9]: 390: 0 1 0 0 VLV-GPIO-gpio byt-codec-int Which is pin 4 on GPO2, but the codec driver in the mainline kernel does not seem to be using this; however AFAICS in sound/soc/codecs/rt5640.c a gpio pin in only used for suspend/resume, so it is not strictly needed if it's already in the correct state, right? Last question, what is the difference between having the device detected by sound/soc/intel/sst-acpi.c (like in my case) opposed to sound/soc/intel/sst/sst_acpi.c? I can see the 80860F28 id in both the files but they seem to load different firmwares. Any idea of what is missing? It's the DSDT which still needs adjusting, or are some changes needed (also) in the kernel driver? Thanks, Antonio [1] http://ao2.it/110 [2] http://ao2.it/tmp/sst-baytrail-on-Teclast-X98-Air-3G/dsdt_sst_original.dsl [3] http://ao2.it/tmp/sst-baytrail-on-Teclast-X98-Air-3G/dmesg_mainline_sst_ori… [4] http://ao2.it/tmp/sst-baytrail-on-Teclast-X98-Air-3G/dmesg_mainline_sst_wit… [5] http://ao2.it/tmp/sst-baytrail-on-Teclast-X98-Air-3G/dsdt_sst_without_ADMA0… [6] http://ao2.it/tmp/sst-baytrail-on-Teclast-X98-Air-3G/dmesg_mainline_sst_wit… [7] http://ao2.it/tmp/sst-baytrail-on-Teclast-X98-Air-3G/android_asound.state [8] http://ao2.it/tmp/sst-baytrail-on-Teclast-X98-Air-3G/dmesg_Android_Teclast_… [9] http://ao2.it/tmp/sst-baytrail-on-Teclast-X98-Air-3G/android_proc_interrupt… -- Antonio Ospite http://ao2.it A: Because it messes up the order in which people normally read text. See http://en.wikipedia.org/wiki/Posting_style Q: Why is top-posting such a bad thing?

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[alsa-devel] [PATCH v2 1/2] ASoC: soc-compress: add a config item for soc-compress
by Jie Yang 15 Sep '15

15 Sep '15

We don't always need soc-compress in soc, here add a config item SND_SOC_COMPRESS, please add 'select SND_SOC_COMPRESS' to driver Kconfig when it is needed. Signed-off-by: Jie Yang <yang.jie(a)intel.com> --- include/sound/soc.h | 7 +++++++ sound/soc/Kconfig | 5 ++++- sound/soc/Makefile | 3 ++- sound/soc/intel/Kconfig | 1 + 4 files changed, 14 insertions(+), 2 deletions(-) diff --git a/include/sound/soc.h b/include/sound/soc.h index 93df8bf..cc1cd4f 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -440,7 +440,14 @@ int snd_soc_platform_read(struct snd_soc_platform *platform, int snd_soc_platform_write(struct snd_soc_platform *platform, unsigned int reg, unsigned int val); int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num); +#if IS_ENABLED(CONFIG_SND_SOC_COMPRESS) int soc_new_compress(struct snd_soc_pcm_runtime *rtd, int num); +#else +static inline int soc_new_compress(struct snd_soc_pcm_runtime *rtd, int num) +{ + return -EPERM; +} +#endif struct snd_pcm_substream *snd_soc_get_dai_substream(struct snd_soc_card *card, const char *dai_link, int stream); diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index e2828e1..a124759 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -9,7 +9,6 @@ menuconfig SND_SOC select SND_JACK if INPUT=y || INPUT=SND select REGMAP_I2C if I2C select REGMAP_SPI if SPI_MASTER - select SND_COMPRESS_OFFLOAD ---help--- If you want ASoC support, you should say Y here and also to the @@ -30,6 +29,10 @@ config SND_SOC_GENERIC_DMAENGINE_PCM bool select SND_DMAENGINE_PCM +config SND_SOC_COMPRESS + tristate + select SND_COMPRESS_OFFLOAD + # All the supported SoCs source "sound/soc/adi/Kconfig" source "sound/soc/atmel/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index a0e1ee6..184c1e6 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -1,6 +1,7 @@ snd-soc-core-objs := soc-core.o soc-dapm.o soc-jack.o soc-cache.o soc-utils.o -snd-soc-core-objs += soc-pcm.o soc-compress.o soc-io.o soc-devres.o soc-ops.o +snd-soc-core-objs += soc-pcm.o soc-io.o soc-devres.o soc-ops.o snd-soc-core-objs += soc-topology.o +snd-soc-core-$(CONFIG_SND_SOC_COMPRESS) += soc-compress.o ifneq ($(CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM),) snd-soc-core-objs += soc-generic-dmaengine-pcm.o diff --git a/sound/soc/intel/Kconfig b/sound/soc/intel/Kconfig index 791953f..e559174 100644 --- a/sound/soc/intel/Kconfig +++ b/sound/soc/intel/Kconfig @@ -12,6 +12,7 @@ config SND_MFLD_MACHINE config SND_SST_MFLD_PLATFORM tristate + select SND_SOC_COMPRESS config SND_SST_IPC tristate -- 1.9.1

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[alsa-devel] [PATCH 1/1] sound/usb: Add Asus Xonar U7 Mixer - input support
by Piotr G. 10 Sep '15

10 Sep '15

Hello, This is my first patch to alsa-devel, and I'm not very skilled programmer. From lsusb -vvv, I've draw Xonar U7 map with all IT OT FU CS in mixer_map.c I don't know why the driver by default doesn't parse all info correctly. With this patch you can see Line Switch and Mic Switch in alsamixer. I can record my voice in Audacity with all supported bit and sampling rates in Mono or Stereo This is temporary solution. Please correct me if the patch is not properly made. What doesn't work: - Cannot change Capture Volume for Line/Mic. No mixer control in alsamixer - Switching between Line/Mic doesn't work (Mute doesn't work) - SPDIF not tested As what I wrote at beginning I'm not skilled programmer so any help is aprreciated proc-usbmixer -> cat /proc/asound/*/usbmix usb.debug -> lsusb -vv (only Asus Xonar U7) --- sound/usb/mixer.c | 23 +++++++++++++++++++++-- sound/usb/mixer_maps.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 2 deletions(-) diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c index 6b3acba..027d160 100644 --- a/sound/usb/mixer.c +++ b/sound/usb/mixer.c @@ -818,6 +818,25 @@ static struct usb_feature_control_info audio_feature_info[] = { { "Phase Inverter Control", USB_MIXER_BOOLEAN }, }; +static struct usb_feature_control_info uac2_audio_feature_info[] = { + /* UAC2 specific */ + { "Mute Control", USB_MIXER_INV_BOOLEAN }, + { "Volume Control", USB_MIXER_S16 }, + { "Bass Control", USB_MIXER_S8 }, + { "Mid Control", USB_MIXER_S8 }, + { "Treble Control", USB_MIXER_S8 }, + { "Graphic Equalizer Control", USB_MIXER_S8 }, + { "Automatic Gain Control", USB_MIXER_BOOLEAN }, + { "Delay Control", USB_MIXER_S16 }, /* FIXME: U32 in UAC2 */ + { "Bass Boost Control", USB_MIXER_BOOLEAN }, + { "Loudness Control", USB_MIXER_BOOLEAN }, + { "Input Gain Control", USB_MIXER_S16 }, + { "Input Gain Pad Control", USB_MIXER_S16 }, + { "Phase Inverter Control", USB_MIXER_BOOLEAN }, + { "Underflow Control", USB_MIXER_BOOLEAN }, + { "Overflow Control", USB_MIXER_BOOLEAN }, +}; + /* private_free callback */ void snd_usb_mixer_elem_free(struct snd_kcontrol *kctl) { @@ -1240,7 +1259,7 @@ static void build_feature_ctl(struct mixer_build *state, void *raw_desc, snd_usb_mixer_elem_init_std(&cval->head, state->mixer, unitid); cval->control = control; cval->cmask = ctl_mask; - cval->val_type = audio_feature_info[control-1].type; + cval->val_type = uac2_audio_feature_info[control-1].type; if (ctl_mask == 0) { cval->channels = 1; /* master channel */ cval->master_readonly = readonly_mask; @@ -1318,7 +1337,7 @@ static void build_feature_ctl(struct mixer_build *state, void *raw_desc, break; default: if (!len) - strlcpy(kctl->id.name, audio_feature_info[control-1].name, + strlcpy(kctl->id.name, uac2_audio_feature_info[control-1].name, sizeof(kctl->id.name)); break; } diff --git a/sound/usb/mixer_maps.c b/sound/usb/mixer_maps.c index e5000da..07f510e 100644 --- a/sound/usb/mixer_maps.c +++ b/sound/usb/mixer_maps.c @@ -341,6 +341,48 @@ static const struct usbmix_name_map scms_usb3318_map[] = { { 0 } }; +/* ASUS Xonar U7 - USB CM6632A (ADC CS5361 // DAC Dolby CS4362A // DAC Stereo CS4398 */ +/* Topology: + +USB_IN[1]------->FU[13]-----------CS[18]--->Spk_OUT[7] + +Dig_IN[2]------->FU[14]-----------CS[19]--->Dig_OUT[8] + +Mic_IN[4]------->FU[16]---+ + SU[20]--CS[22]--->USB_OUT[11] +Line_IN[5]------>FU[17]---+ + +*/ + +static const struct usbmix_name_map xonar_u7_map[] = { + /* 1: IT PCM Analog (USB Streaming) */ + /* 2: IT PCM2 Digital (USB Streaming) */ + /* 4: IT Microphone */ + /* 5: IT Line IN */ + /* 7: OT Speaker */ + /* 8: OT SPDIF */ + /* 11 OT Capture Playback (USB Streaming) */ + { 13, "Speaker Playback" }, /* 13 FU Speaker Out Mute/Volume */ + { 14, "IEC958 Playback" }, /* 14 FU SPDIF Out Mute/Volume */ + { 16, "Mic Capture" }, /* 16 FU Capture Mic-in Mute/Volume */ + { 17, "Line Capture" }, /* 17 FU Capture Line-in Mute/Volume */ + /* 18 CS for 1 PCM (USB Streaming) Clock Source */ + /* 19 CS for 2 SPDIF (USB Streaming) Clock Source */ + { 20, "Capture Source" }, /* 20 SU Capture Source Selector */ + /* 22 CS Line-in and Mic-in Clock Source */ + { 0 } +}; + +static struct usbmix_selector_map xonar_u7_selectors[] = { +{ + .id = 20, + .count = 2, + .names = (const char*[]) {"Mic", "Line"} + }, + { 0 } /* terminator */ + +}; + /* * Control map entries */ @@ -451,6 +493,12 @@ static struct usbmix_ctl_map usbmix_ctl_maps[] = { .id = USB_ID(0x25c4, 0x0003), .map = scms_usb3318_map, }, + { + /* Asus Xonar U7 */ + .id = USB_ID(0x1043, 0x857c), + .map = xonar_u7_map, + .selector_map = xonar_u7_selectors, + }, { 0 } /* terminator */ }; -- 2.3.6

2 2

[alsa-devel] [PATCH v3 0/9] asoc: Add audio for sti platforms
by Arnaud Pouliquen 09 Sep '15

09 Sep '15

version 3 : - patch dependency: ASoC: simple card: set cpu-dai sysclk with mclk-fs (Arnaud Pouliquen) - Remark not applied: Use Russell King's patch "sound/core: add IEC958 channel status helper". => This allows to create settings based on runtime, but not compatible with iec958 controls exposed to userland (settings overwritten by snd_pcm_create_iec958_consumer) - main corrections: - rework DAI CPU declaration to use generic dma - Supress abstraction layer for uniperiph player/reader - use dapm for DAC powerup/down version 2: corrections after first review - bindings: . suppress useless dts declaration - uniperif_player.c: . Suppress standby mode in uniplayer ( will be part of a dedicated patch) . Deliver IEC and clock adjustement controls in separate patch - uniperif_reader.c: . kept as separate file as behavior and feature not same than uniplayer . minor corrections - codec/sti-sas.c . implement DAPM for DAC . rework registers declaration to separate device and driver part version 1: - First patches submission Arnaud Pouliquen (9): ASoC: sti: add binding for ASoC driver ASoC: sti: Add uniperipheral header file ASoC: sti: Add CPU DAI driver for playback ASoC: sti: Add CPU DAI driver for capture ASoC: sti: Add uniperipheral dai driver ASoC: Add ability to build sti drivers ASoC: Codec: Add sti platform codec ASoC: sti: Add clock adjustement control ASoC: sti: Add IEC control .../devicetree/bindings/sound/st,sti-asoc-card.txt | 155 +++ sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/codecs/Kconfig | 5 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/sti-sas.c | 627 ++++++++++ sound/soc/sti/Kconfig | 11 + sound/soc/sti/Makefile | 4 + sound/soc/sti/sti_uniperif.c | 254 ++++ sound/soc/sti/uniperif.h | 1229 ++++++++++++++++++++ sound/soc/sti/uniperif_player.c | 1109 ++++++++++++++++++ sound/soc/sti/uniperif_reader.c | 364 ++++++ 12 files changed, 3762 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt create mode 100644 sound/soc/codecs/sti-sas.c create mode 100644 sound/soc/sti/Kconfig create mode 100644 sound/soc/sti/Makefile create mode 100644 sound/soc/sti/sti_uniperif.c create mode 100644 sound/soc/sti/uniperif.h create mode 100644 sound/soc/sti/uniperif_player.c create mode 100644 sound/soc/sti/uniperif_reader.c -- 1.9.1

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[alsa-devel] [PATCH] ASoC: nau8825: Add driver for headset chip Nuvoton 8825
by Anatol Pomozov 29 Aug '15

29 Aug '15

Signed-off-by: Anatol Pomozov <anatol.pomozov(a)gmail.com> --- .../devicetree/bindings/sound/nau8825.txt | 14 + sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/nau8825.c | 860 +++++++++++++++++++++ sound/soc/codecs/nau8825.h | 258 +++++++ 5 files changed, 1138 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/nau8825.txt create mode 100644 sound/soc/codecs/nau8825.c create mode 100644 sound/soc/codecs/nau8825.h diff --git a/Documentation/devicetree/bindings/sound/nau8825.txt b/Documentation/devicetree/bindings/sound/nau8825.txt new file mode 100644 index 0000000..0334be3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/nau8825.txt @@ -0,0 +1,14 @@ +Nuvoton NAU8825 audio codec + +This device supports I2C only. + +Required properties: + - compatible : Must be "nuvoton,nau8825" + - reg : the I2C address of the device. This is either 0x1a (CSB=0) or 0x1b (CSB=1). + +Example: + + codec: nau8825@1a { + compatible = "nuvoton,nau8825"; + reg = <0x1a>; + }; diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 7fcbc22..1a3639c 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -78,6 +78,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_MAX9877 if I2C select SND_SOC_MC13783 if MFD_MC13XXX select SND_SOC_ML26124 if I2C + select SND_SOC_NAU8825 if I2C select SND_SOC_HDMI_CODEC select SND_SOC_PCM1681 if I2C select SND_SOC_PCM1792A if SPI_MASTER @@ -892,6 +893,9 @@ config SND_SOC_MC13783 config SND_SOC_ML26124 tristate +config SND_SOC_NAU8825 + tristate + config SND_SOC_TPA6130A2 tristate "Texas Instruments TPA6130A2 headphone amplifier" depends on I2C diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 5b46c8f..4874881 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -71,6 +71,7 @@ snd-soc-max98925-objs := max98925.o snd-soc-max9850-objs := max9850.o snd-soc-mc13783-objs := mc13783.o snd-soc-ml26124-objs := ml26124.o +snd-soc-nau8825-objs := nau8825.o snd-soc-hdmi-codec-objs := hdmi.o snd-soc-pcm1681-objs := pcm1681.o snd-soc-pcm1792a-codec-objs := pcm1792a.o @@ -262,6 +263,7 @@ obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o +obj-$(CONFIG_SND_SOC_NAU8825) += snd-soc-nau8825.o obj-$(CONFIG_SND_SOC_HDMI_CODEC) += snd-soc-hdmi-codec.o obj-$(CONFIG_SND_SOC_PCM1681) += snd-soc-pcm1681.o obj-$(CONFIG_SND_SOC_PCM1792A) += snd-soc-pcm1792a-codec.o diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c new file mode 100644 index 0000000..1c99308b --- /dev/null +++ b/sound/soc/codecs/nau8825.c @@ -0,0 +1,860 @@ +/* + * NAU8825 audio codec driver + * + * Copyright 2015 Nuvoton Technology Corp. + * Copyright 2015 Google Chromium project. + * Author: Anatol Pomozov <anatol(a)chromium.org> + * + * Licensed under the GPL-2. + */ + +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <linux/input.h> + +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/jack.h> + +#include "nau8825.h" + +struct nau8825 { + struct device *dev; + struct regmap *regmap; + struct snd_soc_dapm_context *dapm; + int irq; + struct snd_soc_jack *jack; + int button_pressed; +}; + +static const struct reg_default nau8825_reg_defaults[] = { + { NAU8825_REG_ENA_CTRL, 0x00ff }, + { NAU8825_REG_CLK_DIVIDER, 0x0050 }, + { NAU8825_REG_FLL1, 0x0 }, + { NAU8825_REG_FLL2, 0x3126 }, + { NAU8825_REG_FLL3, 0x0008 }, + { NAU8825_REG_FLL4, 0x0010 }, + { NAU8825_REG_FLL5, 0x0 }, + { NAU8825_REG_FLL6, 0x6000 }, + { NAU8825_REG_FLL_VCO_RSV, 0xf13c }, + { NAU8825_REG_HSD_CTRL, 0x000c }, + { NAU8825_REG_JACK_DET_CTRL, 0x0 }, + { NAU8825_REG_INTERRUPT_MASK, 0x0 }, + { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff }, + { NAU8825_REG_SAR_CTRL, 0x0015 }, + { NAU8825_REG_KEYDET_CTRL, 0x0110 }, + { NAU8825_REG_VDET_THRESHOLD_1, 0x0 }, + { NAU8825_REG_VDET_THRESHOLD_2, 0x0 }, + { NAU8825_REG_VDET_THRESHOLD_3, 0x0 }, + { NAU8825_REG_VDET_THRESHOLD_4, 0x0 }, + { NAU8825_REG_GPIO34_CTRL, 0x0 }, + { NAU8825_REG_GPIO12_CTRL, 0x0 }, + { NAU8825_REG_TDM_CTRL, 0x0 }, + { NAU8825_REG_I2S_PCM_CTRL1, 0x000b }, + { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 }, + { NAU8825_REG_LEFT_TIME_SLOT, 0x0 }, + { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 }, + { NAU8825_REG_BIQ_CTRL, 0x0 }, + { NAU8825_REG_BIQ_COF1, 0x0 }, + { NAU8825_REG_BIQ_COF2, 0x0 }, + { NAU8825_REG_BIQ_COF3, 0x0 }, + { NAU8825_REG_BIQ_COF4, 0x0 }, + { NAU8825_REG_BIQ_COF5, 0x0 }, + { NAU8825_REG_BIQ_COF6, 0x0 }, + { NAU8825_REG_BIQ_COF7, 0x0 }, + { NAU8825_REG_BIQ_COF8, 0x0 }, + { NAU8825_REG_BIQ_COF9, 0x0 }, + { NAU8825_REG_BIQ_COF10, 0x0 }, + { NAU8825_REG_ADC_RATE, 0x0010 }, + { NAU8825_REG_DAC_CTRL1, 0x0001 }, + { NAU8825_REG_DAC_CTRL2, 0x0 }, + { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 }, + { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, + { NAU8825_REG_MUTE_CTRL, 0x0 }, + { NAU8825_REG_HSVOL_CTRL, 0x0 }, + { NAU8825_REG_DACL_CTRL, 0x02cf }, + { NAU8825_REG_DACR_CTRL, 0x00cf }, + { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 }, + { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 }, + { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff }, + { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 }, + { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 }, + { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 }, + { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 }, + { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 }, + { NAU8825_REG_IMM_MODE_CTRL, 0x0 }, + { NAU8825_REG_CLASSG_CTRL, 0x0 }, + { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 }, + { NAU8825_REG_MISC_CTRL, 0x0 }, + { NAU8825_REG_BIAS_ADJ, 0x0 }, + { NAU8825_REG_TRIM_SETTINGS, 0x0 }, + { NAU8825_REG_ANALOG_CONTROL_1, 0x0 }, + { NAU8825_REG_ANALOG_CONTROL_2, 0x0 }, + { NAU8825_REG_ANALOG_ADC_1, 0x0011 }, + { NAU8825_REG_ANALOG_ADC_2, 0x0020 }, + { NAU8825_REG_RDAC, 0x0008 }, + { NAU8825_REG_MIC_BIAS, 0x0006 }, + { NAU8825_REG_BOOST, 0x0 }, + { NAU8825_REG_FEPGA, 0x0 }, + { NAU8825_REG_POWER_UP_CONTROL, 0x0 }, + { NAU8825_REG_CHARGE_PUMP, 0x0 }, +}; + +static bool nau8825_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8825_REG_ENA_CTRL: + case NAU8825_REG_CLK_DIVIDER ... NAU8825_REG_FLL_VCO_RSV: + case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: + case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL: + case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: + case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: + case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: + case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R: + case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: + case NAU8825_REG_MISC_CTRL: + case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS: + case NAU8825_REG_BIAS_ADJ: + case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: + case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: + case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: + case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS: + return true; + default: + return false; + } + +} + +static bool nau8825_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8825_REG_RESET ... NAU8825_REG_ENA_CTRL: + case NAU8825_REG_CLK_DIVIDER ... NAU8825_REG_FLL_VCO_RSV: + case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: + case NAU8825_REG_INTERRUPT_MASK: + case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL: + case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: + case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: + case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: + case NAU8825_REG_IMM_MODE_CTRL: + case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: + case NAU8825_REG_MISC_CTRL: + case NAU8825_REG_BIAS_ADJ: + case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: + case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: + case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: + case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP: + return true; + default: + return false; + } +} + +static bool nau8825_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case NAU8825_REG_RESET: + case NAU8825_REG_IRQ_STATUS: + case NAU8825_REG_INT_CLR_KEY_STATUS: + case NAU8825_REG_IMM_RMS_L: + case NAU8825_REG_IMM_RMS_R: + case NAU8825_REG_I2C_DEVICE_ID: + case NAU8825_REG_SARDOUT_RAM_STATUS: + case NAU8825_REG_CHARGE_PUMP_INPUT_READ: + case NAU8825_REG_GENERAL_STATUS: + return true; + default: + return false; + } +} + +static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400); +static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); +static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0); +static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); + +static const struct snd_kcontrol_new nau8825_snd_controls[] = { + SOC_SINGLE_TLV("MIC Volume", NAU8825_REG_ADC_DGAIN_CTRL, + 0, 0xff, 0, adc_vol_tlv), + SOC_DOUBLE_TLV("HP Sidetone Volume", NAU8825_REG_ADC_DGAIN_CTRL, + 12, 8, 0x0f, 0, sidetone_vol_tlv), + SOC_DOUBLE_TLV("HP Volume", NAU8825_REG_HSVOL_CTRL, + 6, 0, 0x3f, 1, dac_vol_tlv), + SOC_SINGLE_TLV("Frontend PGA Gain", NAU8825_REG_POWER_UP_CONTROL, + 8, 37, 0, fepga_gain_tlv), +}; + +static int nau8825_charge_pump_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec); + struct regmap *regmap = nau8825->regmap; + + if (SND_SOC_DAPM_EVENT_ON(event)) { + regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, + NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW); + } else { + regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, + NAU8825_JAMNODCLOW, 0); + } + + return 0; +} + +static int nau8825_output_driver_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec); + struct regmap *regmap = nau8825->regmap; + + if (SND_SOC_DAPM_EVENT_ON(event)) { + /* Power Up L and R Output Drivers */ + regmap_update_bits(regmap, NAU8825_REG_POWER_UP_CONTROL, 0x3c, + 0x3c); + /* Power up Main Output Drivers (The main driver must be turned + on after the predriver to avoid pops) */ + regmap_update_bits(regmap, NAU8825_REG_POWER_UP_CONTROL, 0x3, + 0x3); + } else { + /* Power Down L and R Output Drivers */ + regmap_update_bits(regmap, NAU8825_REG_POWER_UP_CONTROL, 0x3f, + 0x0); + } + + return 0; +} + +/* DAC Mux 0x33[9] and 0x34[9] */ +static const char * const nau8825_dac_src[] = { + "DACL", "DACR", +}; + +static SOC_ENUM_SINGLE_DECL( + nau8825_dacl_enum, NAU8825_REG_DACL_CTRL, + NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src); + +static SOC_ENUM_SINGLE_DECL( + nau8825_dacr_enum, NAU8825_REG_DACR_CTRL, + NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src); + +static const struct snd_kcontrol_new nau8825_dacl_mux = + SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum); + +static const struct snd_kcontrol_new nau8825_dacr_mux = + SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum); + +static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = { + SND_SOC_DAPM_INPUT("MIC"), + SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0), + + SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0, + NULL, 0), + + SND_SOC_DAPM_ADC("ADC", NULL, NAU8825_REG_ENA_CTRL, 8, 0), + SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0), + + /* ADC for button press detection */ + SND_SOC_DAPM_ADC("SAR", NULL, NAU8825_REG_SAR_CTRL, + NAU8825_SAR_ADC_EN_SFT, 0), + + SND_SOC_DAPM_DAC("ADACL", NULL, NAU8825_REG_RDAC, 12, 0), + SND_SOC_DAPM_DAC("ADACR", NULL, NAU8825_REG_RDAC, 13, 0), + SND_SOC_DAPM_SUPPLY("ADACL Clock", NAU8825_REG_RDAC, 8, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADACR Clock", NAU8825_REG_RDAC, 9, 0, NULL, 0), + + SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL, + NAU8825_ENABLE_DACR_SFT, 0), + SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL, + NAU8825_ENABLE_DACL_SFT, 0), + SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0), + + SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, + &nau8825_dacl_mux), + SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, + &nau8825_dacr_mux), + + SND_SOC_DAPM_PGA("HP amp L", NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0), + SND_SOC_DAPM_PGA("HP amp R", NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("HP amp power", NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, + 0), + + SND_SOC_DAPM_SUPPLY("Change Pump", NAU8825_REG_CHARGE_PUMP, 5, 0, + nau8825_charge_pump_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SUPPLY("DACL Power", NAU8825_REG_CHARGE_PUMP, 8, 1, NULL, + 0), + SND_SOC_DAPM_SUPPLY("DACR Power", NAU8825_REG_CHARGE_PUMP, 9, 1, NULL, + 0), + + SND_SOC_DAPM_OUT_DRV_E("Output Driver", SND_SOC_NOPM, 0, 0, NULL, 0, + nau8825_output_driver_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + + SND_SOC_DAPM_OUTPUT("HPOL"), + SND_SOC_DAPM_OUTPUT("HPOR"), +}; + +static const struct snd_soc_dapm_route nau8825_dapm_routes[] = { + {"Frontend PGA", NULL, "MIC"}, + {"ADC", NULL, "Frontend PGA"}, + {"ADC", NULL, "ADC Clock"}, + {"Capture", NULL, "ADC"}, + + {"DDACL", NULL, "Playback"}, + {"DDACR", NULL, "Playback"}, + {"DDACL", NULL, "DDAC Clock"}, + {"DDACR", NULL, "DDAC Clock"}, + {"DDACL", NULL, "DACL Power"}, + {"DDACR", NULL, "DACR Power"}, + {"DACL Mux", "DACL", "DDACL"}, + {"DACL Mux", "DACR", "DDACR"}, + {"DACR Mux", "DACL", "DDACL"}, + {"DACR Mux", "DACR", "DDACR"}, + {"HP amp L", NULL, "Change Pump"}, + {"HP amp R", NULL, "Change Pump"}, + {"HP amp L", NULL, "DACL Mux"}, + {"HP amp R", NULL, "DACR Mux"}, + {"HP amp L", NULL, "HP amp power"}, + {"HP amp R", NULL, "HP amp power"}, + {"ADACL", NULL, "HP amp L"}, + {"ADACR", NULL, "HP amp R"}, + {"ADACL", NULL, "ADACL Clock"}, + {"ADACR", NULL, "ADACR Clock"}, + {"Output Driver", NULL, "ADACL"}, + {"Output Driver", NULL, "ADACR"}, + {"HPOL", NULL, "Output Driver"}, + {"HPOR", NULL, "Output Driver"}, +}; + +static int nau8825_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec); + unsigned int val_len = 0; + + switch (params_width(params)) { + case 16: + val_len |= NAU8825_I2S_DL_16; + break; + case 20: + val_len |= NAU8825_I2S_DL_20; + break; + case 24: + val_len |= NAU8825_I2S_DL_24; + break; + case 32: + val_len |= NAU8825_I2S_DL_32; + break; + default: + return -EINVAL; + } + regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, + NAU8825_I2S_DL_MASK, val_len); + + return 0; +} + +static int nau8825_mute(struct snd_soc_dai *codec_dai, int mute) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec); + int reg_val; + + reg_val = mute ? NAU8825_HP_MUTE : 0; + regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, + NAU8825_HP_MUTE, reg_val); + + return 0; +} + +static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec); + unsigned int ctrl1_val = 0, ctrl2_val = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + ctrl2_val |= NAU8825_I2S_MS_MASTER; + break; + case SND_SOC_DAIFMT_CBS_CFS: + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + ctrl1_val |= NAU8825_I2S_BP_INV; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + ctrl1_val |= NAU8825_I2S_DF_I2S; + break; + case SND_SOC_DAIFMT_LEFT_J: + ctrl1_val |= NAU8825_I2S_DF_LEFT; + break; + case SND_SOC_DAIFMT_RIGHT_J: + ctrl1_val |= NAU8825_I2S_DF_RIGTH; + break; + case SND_SOC_DAIFMT_DSP_A: + ctrl1_val |= NAU8825_I2S_DF_PCM_AB; + break; + case SND_SOC_DAIFMT_DSP_B: + ctrl1_val |= NAU8825_I2S_DF_PCM_AB; + ctrl1_val |= NAU8825_I2S_PCMB_EN; + break; + default: + return -EINVAL; + } + + regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, + NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK | + NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK, + ctrl1_val); + regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, + NAU8825_I2S_MS_MASK, ctrl2_val); + + return 0; +} + +static const struct snd_soc_dai_ops nau8825_dai_ops = { + .hw_params = nau8825_hw_params, + .digital_mute = nau8825_mute, + .set_fmt = nau8825_set_dai_fmt, +}; + +#define NAU8825_RATES SNDRV_PCM_RATE_8000_192000 +#define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ + | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver nau8825_dai = { + .name = "nau8825-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = NAU8825_RATES, + .formats = NAU8825_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 1, + .rates = NAU8825_RATES, + .formats = NAU8825_FORMATS, + }, + .ops = &nau8825_dai_ops, +}; + +/** + * nau8825_enable_jack_detect - Specify a jack for event reporting + * + * @component: component to register the jack with + * @jack: jack to use to report headset and button events on + * + * After this function has been called the headset insert/remove and button + * events will be routed to the given jack. Jack can be null to stop + * reporting. + */ +int nau8825_enable_jack_detect(struct snd_soc_codec *codec, + struct snd_soc_jack *jack) +{ + struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec); + + snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_MEDIA); + snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND); + snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP); + snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN); + + nau8825->jack = jack; + + return 0; +} +EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect); + + +static bool nau8825_is_jack_inserted(struct regmap *regmap) +{ + int status; + + regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status); + return !(status & NAU8825_GPIO2JD1); +} + +static void nau8825_restart_jack_detection(struct regmap *regmap) +{ + /* this will restart the entire jack detection process including MIC/GND + * switching and create interrupts. We have to go from 0 to 1 and back + * to 0 to restart. + */ + regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, + NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART); + regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, + NAU8825_JACK_DET_RESTART, 0); +} + +static void nau8825_eject_jack(struct nau8825 *nau8825) +{ + struct snd_soc_dapm_context *dapm = nau8825->dapm; + struct regmap *regmap = nau8825->regmap; + + snd_soc_dapm_disable_pin(dapm, "SAR"); + snd_soc_dapm_disable_pin(dapm, "MICBIAS"); + /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ + regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, + NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); + /* ground HPL/HPR, MICGRND1/2 */ + regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf); + + snd_soc_dapm_sync(dapm); +} + +static int nau8825_button_decode(int value) +{ + int buttons; + + if (value & BIT(0)) + buttons |= SND_JACK_BTN_0; + if (value & BIT(1)) + buttons |= SND_JACK_BTN_1; + if (value & BIT(2)) + buttons |= SND_JACK_BTN_2; + if (value & BIT(3)) + buttons |= SND_JACK_BTN_3; + + return buttons; +} + +static int nau8825_jack_insert(struct nau8825 *nau8825) +{ + struct regmap *regmap = nau8825->regmap; + struct snd_soc_dapm_context *dapm = nau8825->dapm; + int jack_status_reg, mic_detected; + int type; + + regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg); + mic_detected = (jack_status_reg >> 10) & 3; + + switch (mic_detected) { + case 0: + /* no mic */ + type = SND_JACK_HEADPHONE; + break; + case 1: + dev_info(nau8825->dev, "OMTP (micgnd1) mic connected\n"); + type = SND_JACK_HEADSET; + + /* Unground MICGND1 */ + regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, + 1 << 2); + /* Unground HPL/R */ + regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0x3, 0); + /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */ + regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, + NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, + NAU8825_MICBIAS_JKR2); + /* Attach SARADC to MICGND1 */ + regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, + NAU8825_SAR_INPUT_MASK, + NAU8825_SAR_INPUT_JKR2); + + snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); + snd_soc_dapm_force_enable_pin(dapm, "SAR"); + snd_soc_dapm_sync(dapm); + break; + case 2: + case 3: + dev_info(nau8825->dev, "CTIA (micgnd2) mic connected\n"); + type = SND_JACK_HEADSET; + + /* Unground MICGND2 */ + regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, + 2 << 2); + /* Unground HPL/R */ + regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0x3, 0); + /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */ + regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, + NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, + NAU8825_MICBIAS_JKSLV); + /* Attach SARADC to MICGND2 */ + regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, + NAU8825_SAR_INPUT_MASK, + NAU8825_SAR_INPUT_JKSLV); + + snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); + snd_soc_dapm_force_enable_pin(dapm, "SAR"); + snd_soc_dapm_sync(dapm); + break; + } + + return type; +} + +#define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ + SND_JACK_BTN_2 | SND_JACK_BTN_3) + +static irqreturn_t nau8825_interrupt(int irq, void *data) +{ + struct nau8825 *nau8825 = (struct nau8825 *)data; + struct regmap *regmap = nau8825->regmap; + int active_irq, clear_irq = 0, event = 0, event_mask = 0; + + regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq); + + if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) == + NAU8825_JACK_EJECTION_DETECTED) { + + nau8825_eject_jack(nau8825); + event_mask |= SND_JACK_HEADSET; + clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK; + } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) { + int key_status; + + regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, + &key_status); + + /* upper 8 bits of the register are for short pressed keys, + lower 8 bits - for long pressed buttons */ + nau8825->button_pressed = nau8825_button_decode( + key_status >> 8); + + event |= nau8825->button_pressed; + event_mask |= NAU8825_BUTTONS; + clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ; + } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) { + event_mask = NAU8825_BUTTONS; + clear_irq = NAU8825_KEY_RELEASE_IRQ; + } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) { + if (nau8825_is_jack_inserted(regmap)) { + event |= nau8825_jack_insert(nau8825); + } else { + dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n"); + nau8825_eject_jack(nau8825); + } + + event_mask |= SND_JACK_HEADSET; + clear_irq = NAU8825_HEADSET_COMPLETION_IRQ; + } + + if (!clear_irq) + clear_irq = active_irq; + /* clears the rightmost interruption */ + regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); + + if (event_mask) + snd_soc_jack_report(nau8825->jack, event, event_mask); + + return IRQ_HANDLED; +} + +static void nau8825_setup_buttons(struct regmap *regmap) +{ + /* Setup Button Detect (Debounce, number of buttons, and Hysteresis) */ + regmap_write(regmap, NAU8825_REG_KEYDET_CTRL, 0x7311); + + /* Setup 4 buttons impedane according to Android specification + * https://source.android.com/accessories/headset-spec.html + * Button 0 - 0-70 Ohm + * Button 1 - 110-180 Ohm + * Button 2 - 210-290 Ohm + * Button 3 - 360-680 Ohm + */ + regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1, 0x0f1f); + regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2, 0x325f); +} + +static void nau8825_init_regs(struct regmap *regmap) +{ + /* Power down DACs for power savings */ + regmap_write(regmap, NAU8825_REG_CHARGE_PUMP, 0x0300); + /* DAC Zero Crossing Enable */ + regmap_write(regmap, NAU8825_REG_MUTE_CTRL, 0x1000); + /* VMID Enable and Tieoff */ + regmap_write(regmap, NAU8825_REG_BIAS_ADJ, 0x0060); + /* Analog Bias Enable, Disable Boost Driver, + Automatic Short circuit protection enable */ + regmap_write(regmap, NAU8825_REG_BOOST, 0x3140); + /* Ground HP Outputs[1:0], + Enable Automatic Mic/Gnd switching reading on insert interrupt[6] */ + regmap_write(regmap, NAU8825_REG_HSD_CTRL, 0x004f); + + regmap_write(regmap, NAU8825_REG_JACK_DET_CTRL, 0x01e0); + /* IRQ Output Enable, Mask Insert Interrupt */ + regmap_write(regmap, NAU8825_REG_INTERRUPT_MASK, 0x0801); + /* Jack Detect pull up (High=eject, Low=insert) */ + regmap_write(regmap, NAU8825_REG_GPIO12_CTRL, 0x0800); + /* Setup SAR ADC */ + regmap_write(regmap, NAU8825_REG_SAR_CTRL, 0x0280); + nau8825_setup_buttons(regmap); + + /* Setup ADC x128 OSR */ + regmap_write(regmap, NAU8825_REG_ADC_RATE, 0x0002); + /* Setup DAC x128 OSR */ + regmap_write(regmap, NAU8825_REG_DAC_CTRL1, 0x0082); + /* DAC bias settings */ + regmap_write(regmap, NAU8825_REG_ANALOG_CONTROL_2, 0x1003); + /* ADC Bias Settings */ + regmap_write(regmap, NAU8825_REG_ANALOG_ADC_2, 0x0260); + /* Maximize Jack Insert Debounce */ + regmap_write(regmap, NAU8825_REG_JACK_DET_CTRL, 0x00e0); + + /* Setup clocks */ + regmap_write(regmap, NAU8825_REG_ENA_CTRL, 0x0416); + + /* Chip needs one FSCLK cycle in order to generate interrupts, + as we cannot guarantee one will be provided by the system. Turning + master mode on then off enables us to generate that FSCLK cycle + with a minimum of contention on the clock bus. + Enables master mode and correctly divides BCLK and FSCLK from MCLK. + */ + regmap_write(regmap, NAU8825_REG_I2S_PCM_CTRL2, 0x2019); + regmap_write(regmap, NAU8825_REG_I2S_PCM_CTRL2, 0x0010); + + /* Mask jack insert interruption */ + regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0x0011); +} + +static const struct regmap_config nau8825_regmap_config = { + .val_bits = 16, + .reg_bits = 16, + + .max_register = NAU8825_REG_MAX, + .readable_reg = nau8825_readable_reg, + .writeable_reg = nau8825_writeable_reg, + .volatile_reg = nau8825_volatile_reg, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = nau8825_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults), +}; + +static int nau8825_codec_probe(struct snd_soc_codec *codec) +{ + struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec); + struct device *dev = codec->dev; + + nau8825->dapm = &codec->dapm; + + nau8825_init_regs(nau8825->regmap); + /* The interrupt clock is gated by x1[10:8], + * one of them needs to be enabled all the time for + * interrupts to happen. */ + snd_soc_dapm_force_enable_pin(&codec->dapm, "DDACR"); + snd_soc_dapm_sync(&codec->dapm); + + if (nau8825->irq) { + int ret = devm_request_threaded_irq(dev, nau8825->irq, NULL, + nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, + "nau8825", nau8825); + + if (ret) { + dev_err(dev, "Cannot request irq %d (%d)\n", + nau8825->irq, ret); + return ret; + } + } + nau8825_restart_jack_detection(nau8825->regmap); + + return 0; +} + +static struct snd_soc_codec_driver nau8825_codec_driver = { + .probe = nau8825_codec_probe, + + .controls = nau8825_snd_controls, + .num_controls = ARRAY_SIZE(nau8825_snd_controls), + .dapm_widgets = nau8825_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets), + .dapm_routes = nau8825_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes), +}; + +static void nau8825_reset_chip(struct regmap *regmap) +{ + regmap_write(regmap, NAU8825_REG_RESET, 0x00); + regmap_write(regmap, NAU8825_REG_RESET, 0x00); +} + +static int nau8825_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct device *dev = &i2c->dev; + struct nau8825 *nau8825; + int ret, value; + + nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL); + if (!nau8825) + return -ENOMEM; + + i2c_set_clientdata(i2c, nau8825); + + nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config); + if (IS_ERR(nau8825->regmap)) + return PTR_ERR(nau8825->regmap); + nau8825->irq = i2c->irq; + nau8825->dev = dev; + + nau8825_reset_chip(nau8825->regmap); + ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value); + if (ret < 0) { + dev_err(dev, "Failed to read device id from the NAU8825: %d\n", + ret); + return ret; + } + if ((value & NAU8825_SOFTWARE_ID_MASK) != + NAU8825_SOFTWARE_ID_NAU8825) { + dev_err(dev, "Not a NAU8825 chip\n"); + return -ENODEV; + } + + return snd_soc_register_codec(&i2c->dev, &nau8825_codec_driver, + &nau8825_dai, 1); +} + +static int nau8825_i2c_remove(struct i2c_client *client) +{ + snd_soc_unregister_codec(&client->dev); + return 0; +} + +static const struct i2c_device_id nau8825_i2c_ids[] = { + { "nau8825", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids); + +static struct i2c_driver nau8825_driver = { + .driver = { + .name = "nau8825", + .owner = THIS_MODULE, + }, + .probe = nau8825_i2c_probe, + .remove = nau8825_i2c_remove, + .id_table = nau8825_i2c_ids, +}; +module_i2c_driver(nau8825_driver); + +MODULE_DESCRIPTION("ASoC nau8825 driver"); +MODULE_AUTHOR("Anatol Pomozov <anatol(a)chromium.org>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h new file mode 100644 index 0000000..e1eb769 --- /dev/null +++ b/sound/soc/codecs/nau8825.h @@ -0,0 +1,258 @@ +/* + * NAU8825 ALSA SoC audio driver + * + * Copyright 2015 Google Inc. + * Author: Anatol Pomozov <anatol.pomozov(a)chrominium.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __NAU8825_H__ +#define __NAU8825_H__ + +#define NAU8825_REG_RESET 0x00 +#define NAU8825_REG_ENA_CTRL 0x01 +#define NAU8825_REG_CLK_DIVIDER 0x03 +#define NAU8825_REG_FLL1 0x04 +#define NAU8825_REG_FLL2 0x05 +#define NAU8825_REG_FLL3 0x06 +#define NAU8825_REG_FLL4 0x07 +#define NAU8825_REG_FLL5 0x08 +#define NAU8825_REG_FLL6 0x09 +#define NAU8825_REG_FLL_VCO_RSV 0x0a +#define NAU8825_REG_HSD_CTRL 0x0c +#define NAU8825_REG_JACK_DET_CTRL 0x0d +#define NAU8825_REG_INTERRUPT_MASK 0x0f +#define NAU8825_REG_IRQ_STATUS 0x10 +#define NAU8825_REG_INT_CLR_KEY_STATUS 0x11 +#define NAU8825_REG_INTERRUPT_DIS_CTRL 0x12 +#define NAU8825_REG_SAR_CTRL 0x13 +#define NAU8825_REG_KEYDET_CTRL 0x14 +#define NAU8825_REG_VDET_THRESHOLD_1 0x15 +#define NAU8825_REG_VDET_THRESHOLD_2 0x16 +#define NAU8825_REG_VDET_THRESHOLD_3 0x17 +#define NAU8825_REG_VDET_THRESHOLD_4 0x18 +#define NAU8825_REG_GPIO34_CTRL 0x19 +#define NAU8825_REG_GPIO12_CTRL 0x1a +#define NAU8825_REG_TDM_CTRL 0x1b +#define NAU8825_REG_I2S_PCM_CTRL1 0x1c +#define NAU8825_REG_I2S_PCM_CTRL2 0x1d +#define NAU8825_REG_LEFT_TIME_SLOT 0x1e +#define NAU8825_REG_RIGHT_TIME_SLOT 0x1f +#define NAU8825_REG_BIQ_CTRL 0x20 +#define NAU8825_REG_BIQ_COF1 0x21 +#define NAU8825_REG_BIQ_COF2 0x22 +#define NAU8825_REG_BIQ_COF3 0x23 +#define NAU8825_REG_BIQ_COF4 0x24 +#define NAU8825_REG_BIQ_COF5 0x25 +#define NAU8825_REG_BIQ_COF6 0x26 +#define NAU8825_REG_BIQ_COF7 0x27 +#define NAU8825_REG_BIQ_COF8 0x28 +#define NAU8825_REG_BIQ_COF9 0x29 +#define NAU8825_REG_BIQ_COF10 0x2a +#define NAU8825_REG_ADC_RATE 0x2b +#define NAU8825_REG_DAC_CTRL1 0x2c +#define NAU8825_REG_DAC_CTRL2 0x2d +#define NAU8825_REG_DAC_DGAIN_CTRL 0x2f +#define NAU8825_REG_ADC_DGAIN_CTRL 0x30 +#define NAU8825_REG_MUTE_CTRL 0x31 +#define NAU8825_REG_HSVOL_CTRL 0x32 +#define NAU8825_REG_DACL_CTRL 0x33 +#define NAU8825_REG_DACR_CTRL 0x34 +#define NAU8825_REG_ADC_DRC_KNEE_IP12 0x38 +#define NAU8825_REG_ADC_DRC_KNEE_IP34 0x39 +#define NAU8825_REG_ADC_DRC_SLOPES 0x3a +#define NAU8825_REG_ADC_DRC_ATKDCY 0x3b +#define NAU8825_REG_DAC_DRC_KNEE_IP12 0x45 +#define NAU8825_REG_DAC_DRC_KNEE_IP34 0x46 +#define NAU8825_REG_DAC_DRC_SLOPES 0x47 +#define NAU8825_REG_DAC_DRC_ATKDCY 0x48 +#define NAU8825_REG_IMM_MODE_CTRL 0x4c +#define NAU8825_REG_IMM_RMS_L 0x4d +#define NAU8825_REG_IMM_RMS_R 0x4e +#define NAU8825_REG_CLASSG_CTRL 0x50 +#define NAU8825_REG_OPT_EFUSE_CTRL 0x51 +#define NAU8825_REG_MISC_CTRL 0x55 +#define NAU8825_REG_I2C_DEVICE_ID 0x58 +#define NAU8825_REG_SARDOUT_RAM_STATUS 0x59 +#define NAU8825_REG_BIAS_ADJ 0x66 +#define NAU8825_REG_TRIM_SETTINGS 0x68 +#define NAU8825_REG_ANALOG_CONTROL_1 0x69 +#define NAU8825_REG_ANALOG_CONTROL_2 0x6a +#define NAU8825_REG_ANALOG_ADC_1 0x71 +#define NAU8825_REG_ANALOG_ADC_2 0x72 +#define NAU8825_REG_RDAC 0x73 +#define NAU8825_REG_MIC_BIAS 0x74 +#define NAU8825_REG_BOOST 0x76 +#define NAU8825_REG_FEPGA 0x77 +#define NAU8825_REG_POWER_UP_CONTROL 0x7f +#define NAU8825_REG_CHARGE_PUMP 0x80 +#define NAU8825_REG_CHARGE_PUMP_INPUT_READ 0x81 +#define NAU8825_REG_GENERAL_STATUS 0x82 +#define NAU8825_REG_MAX NAU8825_REG_GENERAL_STATUS + +/* ENA_CTRL (0x1) */ +#define NAU8825_ENABLE_DACR_SFT 10 +#define NAU8825_ENABLE_DACL_SFT 9 +#define NAU8825_ENABLE_ADC_SFT 8 +#define NAU8825_ENABLE_SAR_SFT 1 + +/* CLK_DIVIDER (0x3) */ +#define NAU8825_CLK_SRC_SFT 15 +#define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) +#define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) +#define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) + +/* HSD_CTRL (0xc) */ +#define NAU8825_HSD_AUTO_MODE (1 << 6) +#define NAU8825_SPKR_DWN1R_SHORT (1 << 1) +#define NAU8825_SPKR_DWN1L_SHORT (1 << 0) + +/* JACK_DET_CTRL (0xd) */ +#define NAU8825_JACK_DET_RESTART (1 << 9) + +/* IRQ_STATUS (0x10) */ +#define NAU8825_HEADSET_COMPLETION_IRQ (1 << 10) +#define NAU8825_SHORT_CIRCUIT_IRQ (1 << 9) +#define NAU8825_IMPEDANCE_MEAS_IRQ (1 << 8) +#define NAU8825_KEY_IRQ_MASK (0x7 << 5) +#define NAU8825_KEY_RELEASE_IRQ (1 << 7) +#define NAU8825_KEY_LONG_PRESS_IRQ (1 << 6) +#define NAU8825_KEY_SHORT_PRESS_IRQ (1 << 5) +#define NAU8825_MIC_DETECTION_IRQ (1 << 4) +#define NAU8825_JACK_EJECTION_IRQ_MASK (3 << 2) +#define NAU8825_JACK_EJECTION_DETECTED (1 << 2) +#define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0) +#define NAU8825_JACK_INSERTION_DETECTED (1 << 0) + +/* SAR_CTRL (0x13) */ +#define NAU8825_SAR_ADC_EN_SFT 12 +#define NAU8825_SAR_ADC_EN (1 << NAU8825_SAR_ADC_EN_SFT) +#define NAU8825_SAR_INPUT_MASK (1 << 11) +#define NAU8825_SAR_INPUT_JKSLV (1 << 11) +#define NAU8825_SAR_INPUT_JKR2 (0 << 11) + +/* KEYDET_CTRL (0x14) */ +#define NAU8825_KEYDET_LEVELS_NR_SFT 8 +#define NAU8825_KEYDET_LEVELS_NR_MASK (0x7 << 8) + +/* I2S_PCM_CTRL1 (0x1c) */ +#define NAU8825_I2S_BP_SFT 7 +#define NAU8825_I2S_BP_MASK (1 << NAU8825_I2S_BP_SFT) +#define NAU8825_I2S_BP_INV (1 << NAU8825_I2S_BP_SFT) +#define NAU8825_I2S_PCMB_SFT 6 +#define NAU8825_I2S_PCMB_MASK (1 << NAU8825_I2S_PCMB_SFT) +#define NAU8825_I2S_PCMB_EN (1 << NAU8825_I2S_PCMB_SFT) +#define NAU8825_I2S_DL_SFT 2 +#define NAU8825_I2S_DL_MASK (0x3 << NAU8825_I2S_DL_SFT) +#define NAU8825_I2S_DL_16 (0 << NAU8825_I2S_DL_SFT) +#define NAU8825_I2S_DL_20 (1 << NAU8825_I2S_DL_SFT) +#define NAU8825_I2S_DL_24 (2 << NAU8825_I2S_DL_SFT) +#define NAU8825_I2S_DL_32 (3 << NAU8825_I2S_DL_SFT) +#define NAU8825_I2S_DF_SFT 0 +#define NAU8825_I2S_DF_MASK (0x3 << NAU8825_I2S_DF_SFT) +#define NAU8825_I2S_DF_RIGTH (0 << NAU8825_I2S_DF_SFT) +#define NAU8825_I2S_DF_LEFT (1 << NAU8825_I2S_DF_SFT) +#define NAU8825_I2S_DF_I2S (2 << NAU8825_I2S_DF_SFT) +#define NAU8825_I2S_DF_PCM_AB (3 << NAU8825_I2S_DF_SFT) + +/* I2S_PCM_CTRL2 (0x1d) */ +#define NAU8825_I2S_MS_SFT 3 +#define NAU8825_I2S_MS_MASK (1 << NAU8825_I2S_MS_SFT) +#define NAU8825_I2S_MS_MASTER (1 << NAU8825_I2S_MS_SFT) +#define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT) + +/* ADC_RATE (0x2b) */ +#define NAU8825_ADC_SINC4 (1 << 4) +#define NAU8825_ADC_SINC_DOWN_MASK 3 +#define NAU8825_ADC_SINC_DOWN_32 0 +#define NAU8825_ADC_SINC_DOWN_64 1 +#define NAU8825_ADC_SINC_DOWN_128 2 +#define NAU8825_ADC_SINC_DOWN_256 3 + +/* DAC_CTRL1 (0x2c) */ +#define NAU8825_DAC_CLIP_OFF (1 << 7) +#define NAU8825_DAC_OVERSAMPLE_MASK 7 +#define NAU8825_DAC_OVERSAMPLE_64 0 +#define NAU8825_DAC_OVERSAMPLE_256 1 +#define NAU8825_DAC_OVERSAMPLE_128 2 +#define NAU8825_DAC_OVERSAMPLE_32 4 + +/* MUTE_CTRL (0x31) */ +#define NAU8825_DAC_ZERO_CROSSING_EN (1 << 9) +#define NAU8825_DAC_SOFT_MUTE (1 << 9) + +/* HSVOL_CTRL (0x32) */ +#define NAU8825_HP_MUTE (1 << 15) + +/* DACL_CTRL (0x33) */ +#define NAU8825_DACL_CH_SEL_SFT 9 + +/* DACR_CTRL (0x34) */ +#define NAU8825_DACR_CH_SEL_SFT 9 + +/* I2C_DEVICE_ID (0x58) */ +#define NAU8825_GPIO2JD1 (1 << 7) +#define NAU8825_SOFTWARE_ID_MASK 0x3 +#define NAU8825_SOFTWARE_ID_NAU8825 0x0 + +/* BIAS_ADJ (0x66) */ +#define NAU8825_BIAS_VMID (1 << 6) +#define NAU8825_BIAS_VMID_SEL_MASK (3 << 4) +#define NAU8825_BIAS_VMID_SEL_OPEN (0 << 4) +#define NAU8825_BIAS_VMID_SEL_25KOHM (1 << 4) +#define NAU8825_BIAS_VMID_SEL_125KOHM (2 << 4) +#define NAU8825_BIAS_VMID_SEL_2_5KOHM (3 << 4) + +/* ANALOG_CONTROL_2 (0x6a) */ +#define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12) +#define NAU8825_DAC_CAPACITOR_MSB (1 << 1) +#define NAU8825_DAC_CAPACITOR_LSB (1 << 0) + +/* ANALOG_ADC_2 (0x72) */ +#define NAU8825_ADC_VREFSEL_MASK (0x3 << 8) +#define NAU8825_ADC_VREFSEL_ANALOG (0 << 8) +#define NAU8825_ADC_VREFSEL_VMID (1 << 8) +#define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB (2 << 8) +#define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB (3 << 8) +#define NAU8825_POWERUP_ADCL (1 << 6) + +/* MIC_BIAS (0x74) */ +#define NAU8825_MICBIAS_JKSLV (1 << 14) +#define NAU8825_MICBIAS_JKR2 (1 << 12) +#define NAU8825_MICBIAS_POWERUP_SFT 8 + +/* BOOST (0x76) */ +#define NAU8825_PRECHARGE_DIS (1 << 13) +#define NAU8825_GLOBAL_BIAS_EN (1 << 12) +#define NAU8825_HP_BOOST_DIS (1 << 12) +#define NAU8825_SHORT_SHUTDOWN_EN (1 << 6) + +/* POWER_UP_CONTROL (0x7f) */ +#define NAU8825_POWERUP_HP_DRV_L (1 << 0) +#define NAU8825_POWERUP_HP_DRV_R (1 << 1) +#define NAU8825_POWERUP_DRV_IN_L (1 << 2) +#define NAU8825_POWERUP_DRV_IN_R (1 << 3) +#define NAU8825_POWERUP_INTEGR_L (1 << 4) +#define NAU8825_POWERUP_INTEGR_R (1 << 5) + +/* CHARGE_PUMP_AND_POWER_DOWN_CONTROL (0x80) */ +#define NAU8825_JAMNODCLOW (1 << 10) +#define NAU8825_POWER_DOWN_DACR (1 << 9) +#define NAU8825_POWER_DOWN_DACL (1 << 8) +#define NAU8825_CHANRGE_PUMP_EN (1 << 5) + + +/* System Clock Source */ +enum { + NAU8825_CLK_MCLK = 0, + NAU8825_CLK_INTERNAL, +}; + +int nau8825_enable_jack_detect(struct snd_soc_codec *codec, + struct snd_soc_jack *jack); + + +#endif /* __NAU8825_H__ */ -- 2.5.0.rc2.392.g76e840b

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[alsa-devel] Fwd: [PATCH 1/1] SPI : spi-pxa2xx : fix spi init of WM510205 codec via ACPI (resend)
by Christian Hartmann 28 Aug '15

28 Aug '15

Hi Mika, Dan et al. @Dan : thank you, I will use get_maintainer.pl as of now. @Mika: you mean I should prepare a new DSDT table and in this case overwrite the SPI value there with the 0 and load it (the DSDT table ) into a custom kernel build ?? I will do this (cause all what I want is to enable the codec and to hear sound) currently I have in the extracted DSDT table from this device the SPI1 controller for the "AUDI" device as seen in this snippet : Scope (_SB) { Device (LPEA) { Name (_ADR, Zero) // _ADR: Address Name (_HID, "80860F28" /* Intel SST Audio DSP */) // _HID: Hardware ID Name (_CID, "80860F28" /* Intel SST Audio DSP */) // _CID: Compatible ID Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28") // _DDN: DOS Device Name Name (_SUB, "17AA7004") // _SUB: Subsystem ID Name (_UID, One) // _UID: Unique ID Name (_DEP, Package (0x01) // _DEP: Dependencies { ^SPI1.AUDI }) Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 { PLPE }) .... some lines later follows the AUDI device with Device (AUDI) { Name (_HID, "WM510205") // _HID: Hardware ID Name (_CID, "WM510205") // _CID: Compatible ID Name (_DDN, "Wolfson Microelectronics Audio WM5102") // _DDN: DOS Device Name Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings { Name (SBUF, ResourceTemplate () { SpiSerialBus (0x0001, PolarityLow, FourWireMode, 0x08, ControllerInitiated, 0x007A1200, ClockPolarityLow, ClockPhaseFirst, "\\_SB.SPI1", 0x00, ResourceConsumer, , ) GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone, 0x0000, "\\_SB.GPO2", 0x00, ResourceConsumer, , ) { // Pin list 0x0004 } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.I2C7.PMIC", 0x00, ResourceConsumer, , ) { // Pin list 0x0003 } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list 0x0017 } }) Return (SBUF) /* \_SB_.SPI1.AUDI._CRS.SBUF */ } .... I t makes sense to me, to change the current value(s) in the DSDT and I have read about it to use a custom DSDT table but I am not 100% sure yet (until I have tested it). If I understand you correct, than all I have to do is to change the 'SPI1' string in this dsdt to SPI0 like ^SPI1.AUDI to ^SPI0.AUDI and this block here SpiSerialBus (0x0001, PolarityLow, FourWireMode, 0x08, ControllerInitiated, 0x007A1200, ClockPolarityLow, ClockPhaseFirst, "\\_SB.SPI1", 0x00, ResourceConsumer, , becomes SpiSerialBus (0x0000, PolarityLow, FourWireMode, 0x08, ControllerInitiated, 0x007A1200, ClockPolarityLow, ClockPhaseFirst, "\\_SB.SPI0", 0x00, ResourceConsumer, , For this case, could you please have a look in the whole DSDT table that I extract from this device? If nothing else seems relevant and the current system dsdt has to be changed as suggested, I will try this out as soon as possible @Jarkko : as you suggested , I attach the current system DSDT as a binary. I have also disassembled, and if someone needs it, I can also paste it somewhere else as a reference After all I will assembly the new dsdt and include it in my custom kernel builld as documented, but will wait for some new infos etc. thank you for you answers @all cheers chris 2015-06-25 9:36 GMT+02:00 Mika Westerberg <mika.westerberg(a)linux.intel.com>: > On Thu, Jun 25, 2015 at 09:29:31AM +0200, Christian Hartmann wrote: >> Hello Maintainer(s)s of SPI, >> >> hope I got all of you maintainers now. This email was already sent out >> last week to the alsa-devel list and I resent it here to you. >> >> I have one patch that enables the spi initialization of the WM510205 audio codec >> Without the patch, this message indicates that the codec chip fails >> with the current chipselect number in spi-pxa2xx: >> >> >> [ 0.296256] pxa2xx-spi 80860F0E:00: cs1 >= max 1 >> [ 0.296270] spi_master spi32766: failed to add SPI device >> WM510205:00 from ACPI >> >> So raise num_chipselect by one to enable the codec. The WM510202 is on >> chipselect = 1. > > The hardware only has one chipselect. > > You can fix this by specifying the correct chipselect in the ACPI > SpiSerialBus connector: > > SpiSerialBus (0, PolarityLow, FourWireMode, 8, ControllerInitiated, .. > > First parameter is the chipselect.

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[alsa-devel] [PATCH v5 0/6] Add dw_hdmi i2s audio support
by Yakir Yang 25 Aug '15

25 Aug '15

As Russell have send an series patches for dw_hdmi audio, and most important it works well on rockchip platform. Cause some patches have been achieve in Russell's series, so I abondon some patches in this verison. Here are the abondon patches that already be achieved: * drm: bridge/dw_hdmi: adjust n/cts setting order * drm: bridge/dw_hdmi: set ncts_atomic_write & cts_manual * drm: bridge/dw_hdmi: combine hdmi_set_clock_regenerator_n() and hdmi_regenerate_cts() * drm: bridge/dw_hdmi: add enable/disable to dw_hdmi_audio callbacks And I also abondon some interrupt patches that is not a common bug in dw_hdmi driver, but is a rockchip platform bug which HDMI registers would reset by CRU module after system suspend/resume (in this case HPD interrupt mask would reset, then driver can't respond hot plug event after system resume). Here are the abondon patches that used to "fix" dw_hdmi interrupt bug: * drm: bridge/dw_hdmi: add irq control to suspend/resume * drm: bridge/dw_hdmi: wrap irq control in fucntions * drm: rockchip/dw_hdmi_rockchip: add resume/suspend support Here are the leave list that I have make in my series: - add n/cts combinations for more display modes - enable audio support when sink device is HDMI monitor and has audio - rename dw_hdmi-ahb-audio.h to dw_hdmi-audio.h - add dw_hdmi i2s audio driver - add rockchip_hdmi_audio sound card driver - add dt-bindings for documentation for rockchip_hdmi_audio driver Changes in v5: - make more words in commit message. - Take Russell suggest that create "sink_has_audio" and "sink_is_hdmi" in struct hdmi, and keep vmode's mdvi changeless. - Config fc_invidconf to HDMI mode when sink device is HDMI monitor. - Take Mark Brown suggest that remove jack_status recorded, report jack status directly when hdmi plug happend, and remove devm_kfree and devm_free_irq. - Correct the MODULE_LICENSE to "GPL v2" - Move source from sound/soc/codecs to drivers/gpu/drm/bridge/ - Rename dai driver name to "dw-hdmi-i2s-hifi" - Take Mark Brown suggest that remove the no useful code in probe func, and remove the snd_soc_dai_set_fmt() snd_soc_unregister_card(), remove those noisy dev_info() - Rename codec_dai_name to "dw-hdmi-i2s-hifi" Changes in v4: - Take Dainel suggest that introduce drm_detect_monitor_audio() to judge whether source should config audio. - Replace delaywork with irq thread, and add suspend/resume interfaces, replace "dw-hdmi-audio" with consecutive strings. - Add ".pm = &snd_soc_pm_ops," Changes in v3: - Keep audio format config function in dw-hdmi-audio driver and remove audio_config & get_connect_status functions, move jack control to dw-hdmi-audio completely. - Delete the operation of jack in rockchip-hdmi-audio driver, get ready to switch to simple-audio-card driver. - modify cpu-of-node to i2s-controller Changes in v2: - Update dw_hdmi audio control interfaces, and adjust jack report process - give "codec-name" & "codec-dai-name" an const name - remove codec-name and codec-dai-name - rename rockchip,rockchip-hdmi-audio.txt to rockchip,rockchip-dw-hdmi-audio.txt Yakir Yang (6): drm: bridge/dw_hdmi: add audio support for more display resolutions drm: bridge/dw_hdmi: enable audio when sink device is HDMI and has audio drm: bridge/dw_hdmi: rename dw_hdmi-ahb-audio.h to dw_hdmi-audio.h drm: bridge/dw_hdmi-i2s-audio: add audio driver ASoC: rockchip/rockchip-hdmi-audio: add sound driver for hdmi audio dt-bindings: Add documentation for rockchip_hdmi_audio driver .../sound/rockchip,rockchip-dw-hdmi-audio.txt | 12 + drivers/gpu/drm/bridge/Kconfig | 9 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/dw_hdmi-ahb-audio.c | 2 +- .../{dw_hdmi-ahb-audio.h => dw_hdmi-audio.h} | 0 drivers/gpu/drm/bridge/dw_hdmi-i2s-audio.c | 398 +++++++++++++++++++++ drivers/gpu/drm/bridge/dw_hdmi.c | 100 +++++- drivers/gpu/drm/bridge/dw_hdmi.h | 3 + sound/soc/rockchip/Kconfig | 9 + sound/soc/rockchip/Makefile | 2 + sound/soc/rockchip/rockchip_hdmi_audio.c | 138 +++++++ 11 files changed, 658 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/rockchip,rockchip-dw-hdmi-audio.txt rename drivers/gpu/drm/bridge/{dw_hdmi-ahb-audio.h => dw_hdmi-audio.h} (100%) create mode 100644 drivers/gpu/drm/bridge/dw_hdmi-i2s-audio.c create mode 100644 sound/soc/rockchip/rockchip_hdmi_audio.c -- 2.1.2

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