Alsa-devel May 2014

alsa-devel@alsa-project.org

130 participants
288 discussions

[alsa-devel] [PATCH] ASoC: add RT5677 CODEC driver
by Oder Chiou 09 Jun '14

09 Jun '14

This patch adds the Realtek ALC5677 codec driver. Signed-off-by: Oder Chiou <oder_chiou(a)realtek.com> --- include/sound/rt5677.h | 21 + sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rt5677.c | 3498 +++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/rt5677.h | 1451 +++++++++++++++++++ 5 files changed, 4976 insertions(+) create mode 100644 include/sound/rt5677.h create mode 100644 sound/soc/codecs/rt5677.c create mode 100644 sound/soc/codecs/rt5677.h diff --git a/include/sound/rt5677.h b/include/sound/rt5677.h new file mode 100644 index 0000000..3da1431 --- /dev/null +++ b/include/sound/rt5677.h @@ -0,0 +1,21 @@ +/* + * linux/sound/rt5677.h -- Platform data for RT5677 + * + * Copyright 2013 Realtek Semiconductor Corp. + * Author: Oder Chiou <oder_chiou(a)realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_SND_RT5677_H +#define __LINUX_SND_RT5677_H + +struct rt5677_platform_data { + /* IN1 IN2 can optionally be differential */ + bool in1_diff; + bool in2_diff; +}; + +#endif diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index c59943a..08c5e3a 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -74,6 +74,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_RT5640 if I2C select SND_SOC_RT5645 if I2C select SND_SOC_RT5651 if I2C + select SND_SOC_RT5677 if I2C select SND_SOC_SGTL5000 if I2C select SND_SOC_SI476X if MFD_SI476X_CORE select SND_SOC_SIRF_AUDIO_CODEC @@ -414,6 +415,9 @@ config SND_SOC_RT5645 config SND_SOC_RT5651 tristate +config SND_SOC_RT5677 + tristate + #Freescale sgtl5000 codec config SND_SOC_SGTL5000 tristate "Freescale SGTL5000 CODEC" diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 1ccdaf0..afd8d93 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -64,6 +64,7 @@ snd-soc-rt5631-objs := rt5631.o snd-soc-rt5640-objs := rt5640.o snd-soc-rt5645-objs := rt5645.o snd-soc-rt5651-objs := rt5651.o +snd-soc-rt5677-objs := rt5677.o snd-soc-sgtl5000-objs := sgtl5000.o snd-soc-alc5623-objs := alc5623.o snd-soc-alc5632-objs := alc5632.o @@ -220,6 +221,7 @@ obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o +obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c new file mode 100644 index 0000000..833231e --- /dev/null +++ b/sound/soc/codecs/rt5677.c @@ -0,0 +1,3498 @@ +/* + * rt5677.c -- RT5677 ALSA SoC audio codec driver + * + * Copyright 2013 Realtek Semiconductor Corp. + * Author: Oder Chiou <oder_chiou(a)realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/fs.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/regmap.h> +#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <linux/spi/spi.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> + +#include "rt5677.h" + +#define RT5677_DEVICE_ID 0x6327 + +#define RT5677_PR_RANGE_BASE (0xff + 1) +#define RT5677_PR_SPACING 0x100 + +#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) + +static const struct regmap_range_cfg rt5677_ranges[] = { + { + .name = "PR", + .range_min = RT5677_PR_BASE, + .range_max = RT5677_PR_BASE + 0xfd, + .selector_reg = RT5677_PRIV_INDEX, + .selector_mask = 0xff, + .selector_shift = 0x0, + .window_start = RT5677_PRIV_DATA, + .window_len = 0x1, + }, +}; + +static const struct reg_default init_list[] = { + {RT5677_PR_BASE + 0x3d, 0x364d}, + {RT5677_PR_BASE + 0x17, 0x4fc0}, + {RT5677_PR_BASE + 0x13, 0x0312}, + {RT5677_PR_BASE + 0x1e, 0x0000}, + {RT5677_PR_BASE + 0x12, 0x0eaa}, + {RT5677_PR_BASE + 0x14, 0x018a}, +}; +#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) + +static const struct reg_default rt5677_reg[] = { + {RT5677_RESET , 0x0000}, + {RT5677_LOUT1 , 0xa800}, + {RT5677_IN1 , 0x0000}, + {RT5677_MICBIAS , 0x0000}, + {RT5677_SLIMBUS_PARAM , 0x0000}, + {RT5677_SLIMBUS_RX , 0x0000}, + {RT5677_SLIMBUS_CTRL , 0x0000}, + {RT5677_SIDETONE_CTRL , 0x000b}, + {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, + {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, + {RT5677_DAC4_DIG_VOL , 0xafaf}, + {RT5677_DAC3_DIG_VOL , 0xafaf}, + {RT5677_DAC1_DIG_VOL , 0xafaf}, + {RT5677_DAC2_DIG_VOL , 0xafaf}, + {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, + {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, + {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, + {RT5677_STO1_2_ADC_BST , 0x0000}, + {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, + {RT5677_ADC_BST_CTRL2 , 0x0000}, + {RT5677_STO3_4_ADC_BST , 0x0000}, + {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, + {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, + {RT5677_STO4_ADC_MIXER , 0xd4c0}, + {RT5677_STO3_ADC_MIXER , 0xd4c0}, + {RT5677_STO2_ADC_MIXER , 0xd4c0}, + {RT5677_STO1_ADC_MIXER , 0xd4c0}, + {RT5677_MONO_ADC_MIXER , 0xd4d1}, + {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, + {RT5677_STO1_DAC_MIXER , 0xaaaa}, + {RT5677_MONO_DAC_MIXER , 0xaaaa}, + {RT5677_DD1_MIXER , 0xaaaa}, + {RT5677_DD2_MIXER , 0xaaaa}, + {RT5677_IF3_DATA , 0x0000}, + {RT5677_IF4_DATA , 0x0000}, + {RT5677_PDM_OUT_CTRL , 0x8888}, + {RT5677_PDM_DATA_CTRL1 , 0x0000}, + {RT5677_PDM_DATA_CTRL2 , 0x0000}, + {RT5677_PDM1_DATA_CTRL2 , 0x0000}, + {RT5677_PDM1_DATA_CTRL3 , 0x0000}, + {RT5677_PDM1_DATA_CTRL4 , 0x0000}, + {RT5677_PDM2_DATA_CTRL2 , 0x0000}, + {RT5677_PDM2_DATA_CTRL3 , 0x0000}, + {RT5677_PDM2_DATA_CTRL4 , 0x0000}, + {RT5677_TDM1_CTRL1 , 0x0300}, + {RT5677_TDM1_CTRL2 , 0x0000}, + {RT5677_TDM1_CTRL3 , 0x4000}, + {RT5677_TDM1_CTRL4 , 0x0123}, + {RT5677_TDM1_CTRL5 , 0x4567}, + {RT5677_TDM2_CTRL1 , 0x0300}, + {RT5677_TDM2_CTRL2 , 0x0000}, + {RT5677_TDM2_CTRL3 , 0x4000}, + {RT5677_TDM2_CTRL4 , 0x0123}, + {RT5677_TDM2_CTRL5 , 0x4567}, + {RT5677_I2C_MASTER_CTRL1 , 0x0001}, + {RT5677_I2C_MASTER_CTRL2 , 0x0000}, + {RT5677_I2C_MASTER_CTRL3 , 0x0000}, + {RT5677_I2C_MASTER_CTRL4 , 0x0000}, + {RT5677_I2C_MASTER_CTRL5 , 0x0000}, + {RT5677_I2C_MASTER_CTRL6 , 0x0000}, + {RT5677_I2C_MASTER_CTRL7 , 0x0000}, + {RT5677_I2C_MASTER_CTRL8 , 0x0000}, + {RT5677_DMIC_CTRL1 , 0x1505}, + {RT5677_DMIC_CTRL2 , 0x0055}, + {RT5677_HAP_GENE_CTRL1 , 0x0111}, + {RT5677_HAP_GENE_CTRL2 , 0x0064}, + {RT5677_HAP_GENE_CTRL3 , 0xef0e}, + {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, + {RT5677_HAP_GENE_CTRL5 , 0xef0e}, + {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, + {RT5677_HAP_GENE_CTRL7 , 0xef0e}, + {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, + {RT5677_HAP_GENE_CTRL9 , 0xf000}, + {RT5677_HAP_GENE_CTRL10 , 0x0000}, + {RT5677_PWR_DIG1 , 0x0000}, + {RT5677_PWR_DIG2 , 0x0000}, + {RT5677_PWR_ANLG1 , 0x0055}, + {RT5677_PWR_ANLG2 , 0x0000}, + {RT5677_PWR_DSP1 , 0x0001}, + {RT5677_PWR_DSP_ST , 0x0000}, + {RT5677_PWR_DSP2 , 0x0000}, + {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, + {RT5677_PRIV_INDEX , 0x0000}, + {RT5677_PRIV_DATA , 0x0000}, + {RT5677_I2S4_SDP , 0x8000}, + {RT5677_I2S1_SDP , 0x8000}, + {RT5677_I2S2_SDP , 0x8000}, + {RT5677_I2S3_SDP , 0x8000}, + {RT5677_CLK_TREE_CTRL1 , 0x1111}, + {RT5677_CLK_TREE_CTRL2 , 0x1111}, + {RT5677_CLK_TREE_CTRL3 , 0x0000}, + {RT5677_PLL1_CTRL1 , 0x0000}, + {RT5677_PLL1_CTRL2 , 0x0000}, + {RT5677_PLL2_CTRL1 , 0x0c60}, + {RT5677_PLL2_CTRL2 , 0x2000}, + {RT5677_GLB_CLK1 , 0x0000}, + {RT5677_GLB_CLK2 , 0x0000}, + {RT5677_ASRC_1 , 0x0000}, + {RT5677_ASRC_2 , 0x0000}, + {RT5677_ASRC_3 , 0x0000}, + {RT5677_ASRC_4 , 0x0000}, + {RT5677_ASRC_5 , 0x0000}, + {RT5677_ASRC_6 , 0x0000}, + {RT5677_ASRC_7 , 0x0000}, + {RT5677_ASRC_8 , 0x0000}, + {RT5677_ASRC_9 , 0x0000}, + {RT5677_ASRC_10 , 0x0000}, + {RT5677_ASRC_11 , 0x0000}, + {RT5677_ASRC_12 , 0x0008}, + {RT5677_ASRC_13 , 0x0000}, + {RT5677_ASRC_14 , 0x0000}, + {RT5677_ASRC_15 , 0x0000}, + {RT5677_ASRC_16 , 0x0000}, + {RT5677_ASRC_17 , 0x0000}, + {RT5677_ASRC_18 , 0x0000}, + {RT5677_ASRC_19 , 0x0000}, + {RT5677_ASRC_20 , 0x0000}, + {RT5677_ASRC_21 , 0x000c}, + {RT5677_ASRC_22 , 0x0000}, + {RT5677_ASRC_23 , 0x0000}, + {RT5677_VAD_CTRL1 , 0x2184}, + {RT5677_VAD_CTRL2 , 0x010a}, + {RT5677_VAD_CTRL3 , 0x0aea}, + {RT5677_VAD_CTRL4 , 0x000c}, + {RT5677_VAD_CTRL5 , 0x0000}, + {RT5677_DSP_INB_CTRL1 , 0x0000}, + {RT5677_DSP_INB_CTRL2 , 0x0000}, + {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, + {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, + {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, + {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, + {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, + {RT5677_ADC_EQ_CTRL1 , 0x6000}, + {RT5677_ADC_EQ_CTRL2 , 0x0000}, + {RT5677_EQ_CTRL1 , 0xc000}, + {RT5677_EQ_CTRL2 , 0x0000}, + {RT5677_EQ_CTRL3 , 0x0000}, + {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, + {RT5677_JD_CTRL1 , 0x0000}, + {RT5677_JD_CTRL2 , 0x0000}, + {RT5677_JD_CTRL3 , 0x0000}, + {RT5677_IRQ_CTRL1 , 0x0000}, + {RT5677_IRQ_CTRL2 , 0x0000}, + {RT5677_GPIO_ST , 0x0000}, + {RT5677_GPIO_CTRL1 , 0x0000}, + {RT5677_GPIO_CTRL2 , 0x0000}, + {RT5677_GPIO_CTRL3 , 0x0000}, + {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, + {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, + {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, + {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, + {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, + {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, + {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, + {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, + {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, + {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, + {RT5677_MB_DRC_CTRL1 , 0x0f20}, + {RT5677_DRC1_CTRL1 , 0x001f}, + {RT5677_DRC1_CTRL2 , 0x020c}, + {RT5677_DRC1_CTRL3 , 0x1f00}, + {RT5677_DRC1_CTRL4 , 0x0000}, + {RT5677_DRC1_CTRL5 , 0x0000}, + {RT5677_DRC1_CTRL6 , 0x0029}, + {RT5677_DRC2_CTRL1 , 0x001f}, + {RT5677_DRC2_CTRL2 , 0x020c}, + {RT5677_DRC2_CTRL3 , 0x1f00}, + {RT5677_DRC2_CTRL4 , 0x0000}, + {RT5677_DRC2_CTRL5 , 0x0000}, + {RT5677_DRC2_CTRL6 , 0x0029}, + {RT5677_DRC1_HL_CTRL1 , 0x8000}, + {RT5677_DRC1_HL_CTRL2 , 0x0200}, + {RT5677_DRC2_HL_CTRL1 , 0x8000}, + {RT5677_DRC2_HL_CTRL2 , 0x0200}, + {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, + {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, + {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, + {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, + {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, + {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, + {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, + {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, + {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, + {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, + {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, + {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, + {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, + {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, + {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, + {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, + {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, + {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, + {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, + {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, + {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, + {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, + {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, + {RT5677_DIG_MISC , 0x0000}, + {RT5677_GEN_CTRL1 , 0x0000}, + {RT5677_GEN_CTRL2 , 0x0000}, + {RT5677_VENDOR_ID , 0x0000}, + {RT5677_VENDOR_ID1 , 0x10ec}, + {RT5677_VENDOR_ID2 , 0x6327}, +}; + +static bool rt5677_volatile_register(struct device *dev, unsigned int reg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { + if (reg >= rt5677_ranges[i].range_min && + reg <= rt5677_ranges[i].range_max) { + return true; + } + } + + switch (reg) { + case RT5677_RESET: + case RT5677_SLIMBUS_PARAM: + case RT5677_PDM_DATA_CTRL1: + case RT5677_PDM_DATA_CTRL2: + case RT5677_PDM1_DATA_CTRL4: + case RT5677_PDM2_DATA_CTRL4: + case RT5677_I2C_MASTER_CTRL1: + case RT5677_I2C_MASTER_CTRL7: + case RT5677_I2C_MASTER_CTRL8: + case RT5677_HAP_GENE_CTRL2: + case RT5677_PWR_DSP_ST: + case RT5677_PRIV_DATA: + case RT5677_PLL1_CTRL2: + case RT5677_PLL2_CTRL2: + case RT5677_ASRC_22: + case RT5677_ASRC_23: + case RT5677_VAD_CTRL5: + case RT5677_ADC_EQ_CTRL1: + case RT5677_EQ_CTRL1: + case RT5677_IRQ_CTRL1: + case RT5677_IRQ_CTRL2: + case RT5677_GPIO_ST: + case RT5677_DSP_INB1_SRC_CTRL4: + case RT5677_DSP_INB2_SRC_CTRL4: + case RT5677_DSP_INB3_SRC_CTRL4: + case RT5677_DSP_OUTB1_SRC_CTRL4: + case RT5677_DSP_OUTB2_SRC_CTRL4: + case RT5677_VENDOR_ID: + case RT5677_VENDOR_ID1: + case RT5677_VENDOR_ID2: + return true; + default: + return false; + } +} + +static bool rt5677_readable_register(struct device *dev, unsigned int reg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { + if (reg >= rt5677_ranges[i].range_min && + reg <= rt5677_ranges[i].range_max) { + return true; + } + } + + switch (reg) { + case RT5677_RESET: + case RT5677_LOUT1: + case RT5677_IN1: + case RT5677_MICBIAS: + case RT5677_SLIMBUS_PARAM: + case RT5677_SLIMBUS_RX: + case RT5677_SLIMBUS_CTRL: + case RT5677_SIDETONE_CTRL: + case RT5677_ANA_DAC1_2_3_SRC: + case RT5677_IF_DSP_DAC3_4_MIXER: + case RT5677_DAC4_DIG_VOL: + case RT5677_DAC3_DIG_VOL: + case RT5677_DAC1_DIG_VOL: + case RT5677_DAC2_DIG_VOL: + case RT5677_IF_DSP_DAC2_MIXER: + case RT5677_STO1_ADC_DIG_VOL: + case RT5677_MONO_ADC_DIG_VOL: + case RT5677_STO1_2_ADC_BST: + case RT5677_STO2_ADC_DIG_VOL: + case RT5677_ADC_BST_CTRL2: + case RT5677_STO3_4_ADC_BST: + case RT5677_STO3_ADC_DIG_VOL: + case RT5677_STO4_ADC_DIG_VOL: + case RT5677_STO4_ADC_MIXER: + case RT5677_STO3_ADC_MIXER: + case RT5677_STO2_ADC_MIXER: + case RT5677_STO1_ADC_MIXER: + case RT5677_MONO_ADC_MIXER: + case RT5677_ADC_IF_DSP_DAC1_MIXER: + case RT5677_STO1_DAC_MIXER: + case RT5677_MONO_DAC_MIXER: + case RT5677_DD1_MIXER: + case RT5677_DD2_MIXER: + case RT5677_IF3_DATA: + case RT5677_IF4_DATA: + case RT5677_PDM_OUT_CTRL: + case RT5677_PDM_DATA_CTRL1: + case RT5677_PDM_DATA_CTRL2: + case RT5677_PDM1_DATA_CTRL2: + case RT5677_PDM1_DATA_CTRL3: + case RT5677_PDM1_DATA_CTRL4: + case RT5677_PDM2_DATA_CTRL2: + case RT5677_PDM2_DATA_CTRL3: + case RT5677_PDM2_DATA_CTRL4: + case RT5677_TDM1_CTRL1: + case RT5677_TDM1_CTRL2: + case RT5677_TDM1_CTRL3: + case RT5677_TDM1_CTRL4: + case RT5677_TDM1_CTRL5: + case RT5677_TDM2_CTRL1: + case RT5677_TDM2_CTRL2: + case RT5677_TDM2_CTRL3: + case RT5677_TDM2_CTRL4: + case RT5677_TDM2_CTRL5: + case RT5677_I2C_MASTER_CTRL1: + case RT5677_I2C_MASTER_CTRL2: + case RT5677_I2C_MASTER_CTRL3: + case RT5677_I2C_MASTER_CTRL4: + case RT5677_I2C_MASTER_CTRL5: + case RT5677_I2C_MASTER_CTRL6: + case RT5677_I2C_MASTER_CTRL7: + case RT5677_I2C_MASTER_CTRL8: + case RT5677_DMIC_CTRL1: + case RT5677_DMIC_CTRL2: + case RT5677_HAP_GENE_CTRL1: + case RT5677_HAP_GENE_CTRL2: + case RT5677_HAP_GENE_CTRL3: + case RT5677_HAP_GENE_CTRL4: + case RT5677_HAP_GENE_CTRL5: + case RT5677_HAP_GENE_CTRL6: + case RT5677_HAP_GENE_CTRL7: + case RT5677_HAP_GENE_CTRL8: + case RT5677_HAP_GENE_CTRL9: + case RT5677_HAP_GENE_CTRL10: + case RT5677_PWR_DIG1: + case RT5677_PWR_DIG2: + case RT5677_PWR_ANLG1: + case RT5677_PWR_ANLG2: + case RT5677_PWR_DSP1: + case RT5677_PWR_DSP_ST: + case RT5677_PWR_DSP2: + case RT5677_ADC_DAC_HPF_CTRL1: + case RT5677_PRIV_INDEX: + case RT5677_PRIV_DATA: + case RT5677_I2S4_SDP: + case RT5677_I2S1_SDP: + case RT5677_I2S2_SDP: + case RT5677_I2S3_SDP: + case RT5677_CLK_TREE_CTRL1: + case RT5677_CLK_TREE_CTRL2: + case RT5677_CLK_TREE_CTRL3: + case RT5677_PLL1_CTRL1: + case RT5677_PLL1_CTRL2: + case RT5677_PLL2_CTRL1: + case RT5677_PLL2_CTRL2: + case RT5677_GLB_CLK1: + case RT5677_GLB_CLK2: + case RT5677_ASRC_1: + case RT5677_ASRC_2: + case RT5677_ASRC_3: + case RT5677_ASRC_4: + case RT5677_ASRC_5: + case RT5677_ASRC_6: + case RT5677_ASRC_7: + case RT5677_ASRC_8: + case RT5677_ASRC_9: + case RT5677_ASRC_10: + case RT5677_ASRC_11: + case RT5677_ASRC_12: + case RT5677_ASRC_13: + case RT5677_ASRC_14: + case RT5677_ASRC_15: + case RT5677_ASRC_16: + case RT5677_ASRC_17: + case RT5677_ASRC_18: + case RT5677_ASRC_19: + case RT5677_ASRC_20: + case RT5677_ASRC_21: + case RT5677_ASRC_22: + case RT5677_ASRC_23: + case RT5677_VAD_CTRL1: + case RT5677_VAD_CTRL2: + case RT5677_VAD_CTRL3: + case RT5677_VAD_CTRL4: + case RT5677_VAD_CTRL5: + case RT5677_DSP_INB_CTRL1: + case RT5677_DSP_INB_CTRL2: + case RT5677_DSP_IN_OUTB_CTRL: + case RT5677_DSP_OUTB0_1_DIG_VOL: + case RT5677_DSP_OUTB2_3_DIG_VOL: + case RT5677_DSP_OUTB4_5_DIG_VOL: + case RT5677_DSP_OUTB6_7_DIG_VOL: + case RT5677_ADC_EQ_CTRL1: + case RT5677_ADC_EQ_CTRL2: + case RT5677_EQ_CTRL1: + case RT5677_EQ_CTRL2: + case RT5677_EQ_CTRL3: + case RT5677_SOFT_VOL_ZERO_CROSS1: + case RT5677_JD_CTRL1: + case RT5677_JD_CTRL2: + case RT5677_JD_CTRL3: + case RT5677_IRQ_CTRL1: + case RT5677_IRQ_CTRL2: + case RT5677_GPIO_ST: + case RT5677_GPIO_CTRL1: + case RT5677_GPIO_CTRL2: + case RT5677_GPIO_CTRL3: + case RT5677_STO1_ADC_HI_FILTER1: + case RT5677_STO1_ADC_HI_FILTER2: + case RT5677_MONO_ADC_HI_FILTER1: + case RT5677_MONO_ADC_HI_FILTER2: + case RT5677_STO2_ADC_HI_FILTER1: + case RT5677_STO2_ADC_HI_FILTER2: + case RT5677_STO3_ADC_HI_FILTER1: + case RT5677_STO3_ADC_HI_FILTER2: + case RT5677_STO4_ADC_HI_FILTER1: + case RT5677_STO4_ADC_HI_FILTER2: + case RT5677_MB_DRC_CTRL1: + case RT5677_DRC1_CTRL1: + case RT5677_DRC1_CTRL2: + case RT5677_DRC1_CTRL3: + case RT5677_DRC1_CTRL4: + case RT5677_DRC1_CTRL5: + case RT5677_DRC1_CTRL6: + case RT5677_DRC2_CTRL1: + case RT5677_DRC2_CTRL2: + case RT5677_DRC2_CTRL3: + case RT5677_DRC2_CTRL4: + case RT5677_DRC2_CTRL5: + case RT5677_DRC2_CTRL6: + case RT5677_DRC1_HL_CTRL1: + case RT5677_DRC1_HL_CTRL2: + case RT5677_DRC2_HL_CTRL1: + case RT5677_DRC2_HL_CTRL2: + case RT5677_DSP_INB1_SRC_CTRL1: + case RT5677_DSP_INB1_SRC_CTRL2: + case RT5677_DSP_INB1_SRC_CTRL3: + case RT5677_DSP_INB1_SRC_CTRL4: + case RT5677_DSP_INB2_SRC_CTRL1: + case RT5677_DSP_INB2_SRC_CTRL2: + case RT5677_DSP_INB2_SRC_CTRL3: + case RT5677_DSP_INB2_SRC_CTRL4: + case RT5677_DSP_INB3_SRC_CTRL1: + case RT5677_DSP_INB3_SRC_CTRL2: + case RT5677_DSP_INB3_SRC_CTRL3: + case RT5677_DSP_INB3_SRC_CTRL4: + case RT5677_DSP_OUTB1_SRC_CTRL1: + case RT5677_DSP_OUTB1_SRC_CTRL2: + case RT5677_DSP_OUTB1_SRC_CTRL3: + case RT5677_DSP_OUTB1_SRC_CTRL4: + case RT5677_DSP_OUTB2_SRC_CTRL1: + case RT5677_DSP_OUTB2_SRC_CTRL2: + case RT5677_DSP_OUTB2_SRC_CTRL3: + case RT5677_DSP_OUTB2_SRC_CTRL4: + case RT5677_DSP_OUTB_0123_MIXER_CTRL: + case RT5677_DSP_OUTB_45_MIXER_CTRL: + case RT5677_DSP_OUTB_67_MIXER_CTRL: + case RT5677_DIG_MISC: + case RT5677_GEN_CTRL1: + case RT5677_GEN_CTRL2: + case RT5677_VENDOR_ID: + case RT5677_VENDOR_ID1: + case RT5677_VENDOR_ID2: + return true; + default: + return false; + } +} + +static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); +static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); +static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); +static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); +static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); + +/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ +static unsigned int bst_tlv[] = { + TLV_DB_RANGE_HEAD(7), + 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), + 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), + 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), + 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), + 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), + 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), + 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0), +}; + +static const struct snd_kcontrol_new rt5677_snd_controls[] = { + /* OUTPUT Control */ + SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, + RT5677_LOUT1_L_MUTE_SFT, 1, 1), + SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, + RT5677_LOUT2_L_MUTE_SFT, 1, 1), + SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, + RT5677_LOUT3_L_MUTE_SFT, 1, 1), + + /* DAC Digital Volume */ + SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, + RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), + SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, + RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), + SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, + RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), + SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, + RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv), + + /* IN1/IN2 Control */ + SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), + SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), + + /* ADC Digital Volume Control */ + SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, + RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), + SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, + RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), + SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, + RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), + SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, + RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), + SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, + RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), + + SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, + RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, + adc_vol_tlv), + SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, + RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, + adc_vol_tlv), + SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, + RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, + adc_vol_tlv), + SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, + RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0, + adc_vol_tlv), + SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, + RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0, + adc_vol_tlv), + + /* ADC Boost Volume Control */ + SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5677_STO1_2_ADC_BST, + RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, + adc_bst_tlv), + SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5677_STO1_2_ADC_BST, + RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, + adc_bst_tlv), + SOC_DOUBLE_TLV("STO3 ADC Boost Gain", RT5677_STO3_4_ADC_BST, + RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, + adc_bst_tlv), + SOC_DOUBLE_TLV("STO4 ADC Boost Gain", RT5677_STO3_4_ADC_BST, + RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, + adc_bst_tlv), + SOC_DOUBLE_TLV("Mono ADC Boost Gain", RT5677_ADC_BST_CTRL2, + RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, + adc_bst_tlv), +}; + +/** + * set_dmic_clk - Set parameter of dmic. + * + * @w: DAPM widget. + * @kcontrol: The kcontrol of this widget. + * @event: Event id. + * + * Choose dmic clock between 1MHz and 3MHz. + * It is better for clock to approximate 3MHz. + */ +static int set_dmic_clk(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL, i; + int rate, red, bound, temp; + + rate = rt5677->sysclk; + red = 3000000 * 12; + for (i = 0; i < ARRAY_SIZE(div); i++) { + bound = div[i] * 3000000; + if (rate > bound) + continue; + temp = bound - rate; + if (temp < red) { + red = temp; + idx = i; + } + } + + if (idx < 0) + dev_err(codec->dev, "Failed to set DMIC clock\n"); + else + regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, + RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); + return idx; +} + +static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink) +{ + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec); + unsigned int val; + + regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); + val &= RT5677_SCLK_SRC_MASK; + if (val == RT5677_SCLK_SRC_PLL1) + return 1; + else + return 0; +} + +/* Digital Mixer */ +static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, + RT5677_M_STO1_ADC_L1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, + RT5677_M_STO1_ADC_L2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, + RT5677_M_STO1_ADC_R1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, + RT5677_M_STO1_ADC_R2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, + RT5677_M_STO2_ADC_L1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, + RT5677_M_STO2_ADC_L2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, + RT5677_M_STO2_ADC_R1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, + RT5677_M_STO2_ADC_R2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, + RT5677_M_STO3_ADC_L1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, + RT5677_M_STO3_ADC_L2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, + RT5677_M_STO3_ADC_R1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, + RT5677_M_STO3_ADC_R2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, + RT5677_M_STO4_ADC_L1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, + RT5677_M_STO4_ADC_L2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, + RT5677_M_STO4_ADC_R1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, + RT5677_M_STO4_ADC_R2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, + RT5677_M_MONO_ADC_L1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, + RT5677_M_MONO_ADC_L2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { + SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, + RT5677_M_MONO_ADC_R1_SFT, 1, 1), + SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, + RT5677_M_MONO_ADC_R2_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { + SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, + RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, + RT5677_M_DAC1_L_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { + SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, + RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, + RT5677_M_DAC1_R_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { + SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER, + RT5677_M_ST_DAC1_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, + RT5677_M_DAC1_L_STO_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, + RT5677_M_DAC2_L_STO_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, + RT5677_M_DAC1_R_STO_L_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { + SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER, + RT5677_M_ST_DAC1_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, + RT5677_M_DAC1_R_STO_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, + RT5677_M_DAC2_R_STO_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, + RT5677_M_DAC1_L_STO_R_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { + SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER, + RT5677_M_ST_DAC2_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, + RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, + RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, + RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { + SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER, + RT5677_M_ST_DAC2_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, + RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, + RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, + RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { + SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, + RT5677_M_STO_L_DD1_L_SFT, 1, 1), + SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, + RT5677_M_MONO_L_DD1_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER, + RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER, + RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { + SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, + RT5677_M_STO_R_DD1_R_SFT, 1, 1), + SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, + RT5677_M_MONO_R_DD1_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER, + RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER, + RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { + SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, + RT5677_M_STO_L_DD2_L_SFT, 1, 1), + SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, + RT5677_M_MONO_L_DD2_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER, + RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER, + RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { + SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, + RT5677_M_STO_R_DD2_R_SFT, 1, 1), + SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, + RT5677_M_MONO_R_DD2_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER, + RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), + SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER, + RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { + SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_01_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_23_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_45_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_6_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_7_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_8_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_9_H_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { + SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_01_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_23_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_45_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_6_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_7_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_8_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, + RT5677_DSP_IB_9_L_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { + SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_01_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_23_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_45_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_6_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_7_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_8_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_9_H_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { + SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_01_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_23_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_45_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_6_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_7_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_8_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, + RT5677_DSP_IB_9_L_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { + SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_01_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_23_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_45_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_6_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_7_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_8_H_SFT, 1, 1), + SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_9_H_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { + SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_01_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_23_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_45_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_6_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_7_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_8_L_SFT, 1, 1), + SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, + RT5677_DSP_IB_9_L_SFT, 1, 1), +}; + + +/* Mux */ +/* DAC1 L/R source */ /* MX-29 [10:8] */ +static const char * const rt5677_dac1_src[] = { + "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", + "OB 01" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, + RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); + +static const struct snd_kcontrol_new rt5677_dac1_mux = + SOC_DAPM_ENUM("DAC1 source", rt5677_dac1_enum); + +/* ADDA1 L/R source */ /* MX-29 [1:0] */ +static const char * const rt5677_adda1_src[] = { + "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, + RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); + +static const struct snd_kcontrol_new rt5677_adda1_mux = + SOC_DAPM_ENUM("ADDA1 source", rt5677_adda1_enum); + + +/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ +static const char * const rt5677_dac2l_src[] = { + "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", + "OB 2", +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, + RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); + +static const struct snd_kcontrol_new rt5677_dac2_l_mux = + SOC_DAPM_ENUM("DAC2 L source", rt5677_dac2l_enum); + +static const char * const rt5677_dac2r_src[] = { + "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", + "OB 3", "Haptic Generator", "VAD ADC" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, + RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); + +static const struct snd_kcontrol_new rt5677_dac2_r_mux = + SOC_DAPM_ENUM("DAC2 R source", rt5677_dac2r_enum); + +/*DAC3 L/R source*/ /* MX-16 [6:4] [2:0] */ +static const char * const rt5677_dac3l_src[] = { + "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", + "SLB DAC 4", "OB 4" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, + RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); + +static const struct snd_kcontrol_new rt5677_dac3_l_mux = + SOC_DAPM_ENUM("DAC3 L source", rt5677_dac3l_enum); + +static const char * const rt5677_dac3r_src[] = { + "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", + "SLB DAC 5", "OB 5" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, + RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); + +static const struct snd_kcontrol_new rt5677_dac3_r_mux = + SOC_DAPM_ENUM("DAC3 R source", rt5677_dac3r_enum); + +/*DAC4 L/R source*/ /* MX-16 [14:12] [10:8] */ +static const char * const rt5677_dac4l_src[] = { + "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", + "SLB DAC 6", "OB 6" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, + RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); + +static const struct snd_kcontrol_new rt5677_dac4_l_mux = + SOC_DAPM_ENUM("DAC4 L source", rt5677_dac4l_enum); + +static const char * const rt5677_dac4r_src[] = { + "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", + "SLB DAC 7", "OB 7" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, + RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); + +static const struct snd_kcontrol_new rt5677_dac4_r_mux = + SOC_DAPM_ENUM("DAC4 R source", rt5677_dac4r_enum); + +/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ +static const char * const rt5677_iob_bypass_src[] = { + "Bypass", "Pass SRC" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, + RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); + +static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = + SOC_DAPM_ENUM("OB01 Bypass source", rt5677_ob01_bypass_src_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, + RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); + +static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = + SOC_DAPM_ENUM("OB23 Bypass source", rt5677_ob23_bypass_src_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, + RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); + +static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = + SOC_DAPM_ENUM("IB01 Bypass source", rt5677_ib01_bypass_src_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, + RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); + +static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = + SOC_DAPM_ENUM("IB23 Bypass source", rt5677_ib23_bypass_src_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, + RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); + +static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = + SOC_DAPM_ENUM("IB45 Bypass source", rt5677_ib45_bypass_src_enum); + +/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ +static const char * const rt5677_stereo_adc2_src[] = { + "DD MIX1", "DMIC", "Stereo DAC MIX" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, + RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); + +static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = + SOC_DAPM_ENUM("Stereo1 ADC2 source", rt5677_stereo1_adc2_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, + RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); + +static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = + SOC_DAPM_ENUM("Stereo2 ADC2 source", rt5677_stereo2_adc2_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, + RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); + +static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = + SOC_DAPM_ENUM("Stereo3 ADC2 source", rt5677_stereo3_adc2_enum); + +/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ +static const char * const rt5677_dmic_src[] = { + "DMIC1", "DMIC2", "DMIC3", "DMIC4" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, + RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); + +static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = + SOC_DAPM_ENUM("Mono DMIC L source", rt5677_mono_dmic_l_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, + RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); + +static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = + SOC_DAPM_ENUM("Mono DMIC R source", rt5677_mono_dmic_r_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, + RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); + +static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = + SOC_DAPM_ENUM("Stereo1 DMIC source", rt5677_stereo1_dmic_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, + RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); + +static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = + SOC_DAPM_ENUM("Stereo2 DMIC source", rt5677_stereo2_dmic_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, + RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); + +static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = + SOC_DAPM_ENUM("Stereo3 DMIC source", rt5677_stereo3_dmic_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, + RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); + +static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = + SOC_DAPM_ENUM("Stereo4 DMIC source", rt5677_stereo4_dmic_enum); + +/* Stereo2 ADC source */ /* MX-26 [0] */ +static const char * const rt5677_stereo2_adc_lr_src[] = { + "L", "LR" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, + RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); + +static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = + SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5677_stereo2_adc_lr_enum); + +/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ +static const char * const rt5677_stereo_adc1_src[] = { + "DD MIX1", "ADC1/2", "Stereo DAC MIX" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, + RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); + +static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = + SOC_DAPM_ENUM("Stereo1 ADC1 source", rt5677_stereo1_adc1_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, + RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); + +static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = + SOC_DAPM_ENUM("Stereo2 ADC1 source", rt5677_stereo2_adc1_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, + RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); + +static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = + SOC_DAPM_ENUM("Stereo3 ADC1 source", rt5677_stereo3_adc1_enum); + +/* Mono ADC Left source 2 */ /* MX-28 [11:10] */ +static const char * const rt5677_mono_adc2_l_src[] = { + "DD MIX1L", "DMIC", "MONO DAC MIXL" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, + RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); + +static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = + SOC_DAPM_ENUM("Mono ADC2 L source", rt5677_mono_adc2_l_enum); + +/* Mono ADC Left source 1 */ /* MX-28 [13:12] */ +static const char * const rt5677_mono_adc1_l_src[] = { + "DD MIX1L", "ADC1", "MONO DAC MIXL" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, + RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); + +static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = + SOC_DAPM_ENUM("Mono ADC1 L source", rt5677_mono_adc1_l_enum); + +/* Mono ADC Right source 2 */ /* MX-28 [3:2] */ +static const char * const rt5677_mono_adc2_r_src[] = { + "DD MIX1R", "DMIC", "MONO DAC MIXR" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, + RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); + +static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = + SOC_DAPM_ENUM("Mono ADC2 R source", rt5677_mono_adc2_r_enum); + +/* Mono ADC Right source 1 */ /* MX-28 [5:4] */ +static const char * const rt5677_mono_adc1_r_src[] = { + "DD MIX1R", "ADC2", "MONO DAC MIXR" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, + RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); + +static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = + SOC_DAPM_ENUM("Mono ADC1 R source", rt5677_mono_adc1_r_enum); + +/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ +static const char * const rt5677_stereo4_adc2_src[] = { + "DD MIX1", "DMIC", "DD MIX2" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, + RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); + +static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = + SOC_DAPM_ENUM("Stereo4 ADC2 source", rt5677_stereo4_adc2_enum); + + +/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ +static const char * const rt5677_stereo4_adc1_src[] = { + "DD MIX1", "ADC1/2", "DD MIX2" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, + RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); + +static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = + SOC_DAPM_ENUM("Stereo4 ADC1 source", rt5677_stereo4_adc1_enum); + +/* InBound0/1 Source */ /* MX-A3 [14:12] */ +static const char * const rt5677_inbound01_src[] = { + "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", + "VAD ADC/DAC1 FS" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, + RT5677_IB01_SRC_SFT, rt5677_inbound01_src); + +static const struct snd_kcontrol_new rt5677_ib01_src_mux = + SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); + +/* InBound2/3 Source */ /* MX-A3 [10:8] */ +static const char * const rt5677_inbound23_src[] = { + "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", + "DAC1 FS", "IF4 DAC" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, + RT5677_IB23_SRC_SFT, rt5677_inbound23_src); + +static const struct snd_kcontrol_new rt5677_ib23_src_mux = + SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); + +/* InBound4/5 Source */ /* MX-A3 [6:4] */ +static const char * const rt5677_inbound45_src[] = { + "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", + "IF3 DAC" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, + RT5677_IB45_SRC_SFT, rt5677_inbound45_src); + +static const struct snd_kcontrol_new rt5677_ib45_src_mux = + SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); + +/* InBound6 Source */ /* MX-A3 [2:0] */ +static const char * const rt5677_inbound6_src[] = { + "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", + "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, + RT5677_IB6_SRC_SFT, rt5677_inbound6_src); + +static const struct snd_kcontrol_new rt5677_ib6_src_mux = + SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); + +/* InBound7 Source */ /* MX-A4 [14:12] */ +static const char * const rt5677_inbound7_src[] = { + "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", + "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, + RT5677_IB7_SRC_SFT, rt5677_inbound7_src); + +static const struct snd_kcontrol_new rt5677_ib7_src_mux = + SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); + +/* InBound8 Source */ /* MX-A4 [10:8] */ +static const char * const rt5677_inbound8_src[] = { + "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", + "MONO ADC MIX L", "DACL1 FS" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, + RT5677_IB8_SRC_SFT, rt5677_inbound8_src); + +static const struct snd_kcontrol_new rt5677_ib8_src_mux = + SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); + +/* InBound9 Source */ /* MX-A4 [6:4] */ +static const char * const rt5677_inbound9_src[] = { + "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", + "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, + RT5677_IB9_SRC_SFT, rt5677_inbound9_src); + +static const struct snd_kcontrol_new rt5677_ib9_src_mux = + SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); + +/* VAD Source */ /* MX-9F [6:4] */ +static const char * const rt5677_vad_src[] = { + "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", + "STO3 ADC MIX L" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_vad_enum, RT5677_VAD_CTRL4, + RT5677_VAD_SRC_SFT, rt5677_vad_src); + +static const struct snd_kcontrol_new rt5677_vad_src_mux = + SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); + +/* Sidetone Source */ /* MX-13 [11:9] */ +static const char * const rt5677_sidetone_src[] = { + "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, + RT5677_ST_SEL_SFT, rt5677_sidetone_src); + +static const struct snd_kcontrol_new rt5677_sidetone_mux = + SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); + +/* DAC1/2 Source */ /* MX-15 [1:0] */ +static const char * const rt5677_dac12_src[] = { + "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, + RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); + +static const struct snd_kcontrol_new rt5677_dac12_mux = + SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); + +/* DAC3 Source */ /* MX-15 [5:4] */ +static const char * const rt5677_dac3_src[] = { + "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, + RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); + +static const struct snd_kcontrol_new rt5677_dac3_mux = + SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); + +/* PDM channel source */ /* MX-31 [13:12][9:8][5:4][1:0] */ +static const char * const rt5677_pdm_src[] = { + "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, + RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); + +static const struct snd_kcontrol_new rt5677_pdm1_l_mux = + SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_l_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, + RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); + +static const struct snd_kcontrol_new rt5677_pdm2_l_mux = + SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_l_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, + RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); + +static const struct snd_kcontrol_new rt5677_pdm1_r_mux = + SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_r_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, + RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); + +static const struct snd_kcontrol_new rt5677_pdm2_r_mux = + SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_r_enum); + +/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/ +static const char * const rt5677_if12_adc1_src[] = { + "STO1 ADC MIX", "OB01", "VAD ADC" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, + RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); + +static const struct snd_kcontrol_new rt5677_if1_adc1_mux = + SOC_DAPM_ENUM("IF1 ADC1 source", rt5677_if1_adc1_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, + RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); + +static const struct snd_kcontrol_new rt5677_if2_adc1_mux = + SOC_DAPM_ENUM("IF2 ADC1 source", rt5677_if2_adc1_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, + RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); + +static const struct snd_kcontrol_new rt5677_slb_adc1_mux = + SOC_DAPM_ENUM("SLB ADC1 source", rt5677_slb_adc1_enum); + +/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ +static const char * const rt5677_if12_adc2_src[] = { + "STO2 ADC MIX", "OB23" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, + RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); + +static const struct snd_kcontrol_new rt5677_if1_adc2_mux = + SOC_DAPM_ENUM("IF1 ADC2 source", rt5677_if1_adc2_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, + RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); + +static const struct snd_kcontrol_new rt5677_if2_adc2_mux = + SOC_DAPM_ENUM("IF2 ADC2 source", rt5677_if2_adc2_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, + RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); + +static const struct snd_kcontrol_new rt5677_slb_adc2_mux = + SOC_DAPM_ENUM("SLB ADC2 source", rt5677_slb_adc2_enum); + +/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ +static const char * const rt5677_if12_adc3_src[] = { + "STO3 ADC MIX", "MONO ADC MIX", "OB45" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, + RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); + +static const struct snd_kcontrol_new rt5677_if1_adc3_mux = + SOC_DAPM_ENUM("IF1 ADC3 source", rt5677_if1_adc3_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, + RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); + +static const struct snd_kcontrol_new rt5677_if2_adc3_mux = + SOC_DAPM_ENUM("IF2 ADC3 source", rt5677_if2_adc3_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, + RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); + +static const struct snd_kcontrol_new rt5677_slb_adc3_mux = + SOC_DAPM_ENUM("SLB ADC3 source", rt5677_slb_adc3_enum); + +/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ +static const char * const rt5677_if12_adc4_src[] = { + "STO4 ADC MIX", "OB67", "OB01" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, + RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); + +static const struct snd_kcontrol_new rt5677_if1_adc4_mux = + SOC_DAPM_ENUM("IF1 ADC4 source", rt5677_if1_adc4_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, + RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); + +static const struct snd_kcontrol_new rt5677_if2_adc4_mux = + SOC_DAPM_ENUM("IF2 ADC4 source", rt5677_if2_adc4_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, + RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); + +static const struct snd_kcontrol_new rt5677_slb_adc4_mux = + SOC_DAPM_ENUM("SLB ADC4 source", rt5677_slb_adc4_enum); + +/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/ +static const char * const rt5677_if34_adc_src[] = { + "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", + "MONO ADC MIX", "OB01", "OB23", "VAD ADC" +}; + +static SOC_ENUM_SINGLE_DECL( + rt5677_if3_adc_enum, RT5677_IF3_DATA, + RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); + +static const struct snd_kcontrol_new rt5677_if3_adc_mux = + SOC_DAPM_ENUM("IF3 ADC source", rt5677_if3_adc_enum); + +static SOC_ENUM_SINGLE_DECL( + rt5677_if4_adc_enum, RT5677_IF4_DATA, + RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); + +static const struct snd_kcontrol_new rt5677_if4_adc_mux = + SOC_DAPM_ENUM("IF4 ADC source", rt5677_if4_adc_enum); + +static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, + RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); + break; + + case SND_SOC_DAPM_PRE_PMD: + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, + RT5677_PWR_BST1_P, 0); + break; + + default: + return 0; + } + + return 0; +} + +static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, + RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); + break; + + case SND_SOC_DAPM_PRE_PMD: + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, + RT5677_PWR_BST2_P, 0); + break; + + default: + return 0; + } + + return 0; +} + +static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); + regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); + break; + default: + return 0; + } + + return 0; +} + +static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); + regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); + break; + default: + return 0; + } + + return 0; +} + +static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, + RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | + RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | + RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); + break; + default: + return 0; + } + + return 0; +} + +static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { + SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, + 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, + 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU), + + /* Input Side */ + /* micbias */ + SND_SOC_DAPM_SUPPLY("micbias1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, + 0, rt5677_set_micbias1_event, SND_SOC_DAPM_POST_PMU), + + /* Input Lines */ + SND_SOC_DAPM_INPUT("DMIC L1"), + SND_SOC_DAPM_INPUT("DMIC R1"), + SND_SOC_DAPM_INPUT("DMIC L2"), + SND_SOC_DAPM_INPUT("DMIC R2"), + SND_SOC_DAPM_INPUT("DMIC L3"), + SND_SOC_DAPM_INPUT("DMIC R3"), + SND_SOC_DAPM_INPUT("DMIC L4"), + SND_SOC_DAPM_INPUT("DMIC R4"), + + SND_SOC_DAPM_INPUT("IN1P"), + SND_SOC_DAPM_INPUT("IN1N"), + SND_SOC_DAPM_INPUT("IN2P"), + SND_SOC_DAPM_INPUT("IN2N"), + + SND_SOC_DAPM_INPUT("Haptic Generator"), + + SND_SOC_DAPM_PGA("DMIC1", RT5677_DMIC_CTRL1, RT5677_DMIC_1_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_PGA("DMIC2", RT5677_DMIC_CTRL1, RT5677_DMIC_2_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_PGA("DMIC3", RT5677_DMIC_CTRL1, RT5677_DMIC_3_EN_SFT, 0, + NULL, 0), + SND_SOC_DAPM_PGA("DMIC4", RT5677_DMIC_CTRL2, RT5677_DMIC_4_EN_SFT, 0, + NULL, 0), + + SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, + set_dmic_clk, SND_SOC_DAPM_PRE_PMU), + + /* Boost */ + SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, + RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, + RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + + /* ADCs */ + SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, + 0, 0), + SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, + 0, 0), + SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, + RT5677_PWR_ADC_L_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, + RT5677_PWR_ADC_R_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, + RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, + RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), + + /* ADC Mux */ + SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto1_dmic_mux), + SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto1_adc1_mux), + SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto1_adc2_mux), + SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto2_dmic_mux), + SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto2_adc1_mux), + SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto2_adc2_mux), + SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto2_adc_lr_mux), + SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto3_dmic_mux), + SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto3_adc1_mux), + SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto3_adc2_mux), + SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto4_dmic_mux), + SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto4_adc1_mux), + SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sto4_adc2_mux), + SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, + &rt5677_mono_dmic_l_mux), + SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, + &rt5677_mono_dmic_r_mux), + SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, + &rt5677_mono_adc2_l_mux), + SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, + &rt5677_mono_adc1_l_mux), + SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, + &rt5677_mono_adc1_r_mux), + SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, + &rt5677_mono_adc2_r_mux), + + /* ADC Mixer */ + SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, + RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, + RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, + RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, + RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), + SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, + rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), + SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, + rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), + SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, + rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), + SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, + rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), + SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, + rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), + SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, + rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), + SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, + rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), + SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, + rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), + SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, + RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), + SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, + rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), + SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, + RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), + SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, + rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), + + /* ADC PGA */ + SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* DSP */ + SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ib9_src_mux), + SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ib8_src_mux), + SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ib7_src_mux), + SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ib6_src_mux), + SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ib45_src_mux), + SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ib23_src_mux), + SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ib01_src_mux), + SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ib45_bypass_src_mux), + SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ib23_bypass_src_mux), + SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ib01_bypass_src_mux), + SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ob23_bypass_src_mux), + SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, + &rt5677_ob01_bypass_src_mux), + + SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* Digital Interface */ + SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, + RT5677_PWR_I2S1_BIT, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, + RT5677_PWR_I2S2_BIT, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, + RT5677_PWR_I2S3_BIT, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, + RT5677_PWR_I2S4_BIT, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, + RT5677_PWR_SLB_BIT, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* Digital Interface Select */ + SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_if1_adc1_mux), + SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_if1_adc2_mux), + SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_if1_adc3_mux), + SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_if1_adc4_mux), + SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_if2_adc1_mux), + SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_if2_adc2_mux), + SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_if2_adc3_mux), + SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_if2_adc4_mux), + SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, + &rt5677_if3_adc_mux), + SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, + &rt5677_if4_adc_mux), + SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_slb_adc1_mux), + SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_slb_adc2_mux), + SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_slb_adc3_mux), + SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_slb_adc4_mux), + + /* Audio Interface */ + SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), + + /* Sidetone Mux */ + SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, + &rt5677_sidetone_mux), + /* VAD Mux*/ + SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, + &rt5677_vad_src_mux), + + /* Tensilica DSP */ + SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, + rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), + SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, + rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), + SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, + rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), + SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, + rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), + SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, + rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), + SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, + rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), + + /* Output Side */ + /* DAC mixer before sound effect */ + SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, + rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), + SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, + rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), + SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* DAC Mux */ + SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_dac1_mux), + SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, + &rt5677_adda1_mux), + SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, + &rt5677_dac12_mux), + SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, + &rt5677_dac3_mux), + + /* DAC2 channel Mux */ + SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, + &rt5677_dac2_l_mux), + SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, + &rt5677_dac2_r_mux), + + /* DAC3 channel Mux */ + SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, + &rt5677_dac3_l_mux), + SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, + &rt5677_dac3_r_mux), + + /* DAC4 channel Mux */ + SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, + &rt5677_dac4_l_mux), + SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, + &rt5677_dac4_r_mux), + + /* DAC Mixer */ + SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, + RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2, + RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2, + RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0), + + SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, + rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), + SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, + rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), + SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, + rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), + SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, + rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), + SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, + rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), + SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, + rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), + SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, + rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), + SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, + rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), + SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* DACs */ + SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, + RT5677_PWR_DAC1_BIT, 0), + SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, + RT5677_PWR_DAC2_BIT, 0), + SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, + RT5677_PWR_DAC3_BIT, 0), + + /* PDM */ + SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, + RT5677_PWR_PDM1_BIT, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, + RT5677_PWR_PDM2_BIT, 0, NULL, 0), + + SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, + 1, &rt5677_pdm1_l_mux), + SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, + 1, &rt5677_pdm1_r_mux), + SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, + 1, &rt5677_pdm2_l_mux), + SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, + 1, &rt5677_pdm2_r_mux), + + SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, + 0, NULL, 0), + SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, + 0, NULL, 0), + SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, + 0, NULL, 0), + + /* Output Lines */ + SND_SOC_DAPM_OUTPUT("LOUT1"), + SND_SOC_DAPM_OUTPUT("LOUT2"), + SND_SOC_DAPM_OUTPUT("LOUT3"), + SND_SOC_DAPM_OUTPUT("PDM1L"), + SND_SOC_DAPM_OUTPUT("PDM1R"), + SND_SOC_DAPM_OUTPUT("PDM2L"), + SND_SOC_DAPM_OUTPUT("PDM2R"), +}; + +static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { + { "DMIC1", NULL, "DMIC L1" }, + { "DMIC1", NULL, "DMIC R1" }, + { "DMIC2", NULL, "DMIC L2" }, + { "DMIC2", NULL, "DMIC R2" }, + { "DMIC3", NULL, "DMIC L3" }, + { "DMIC3", NULL, "DMIC R3" }, + { "DMIC4", NULL, "DMIC L4" }, + { "DMIC4", NULL, "DMIC R4" }, + + { "DMIC L1", NULL, "DMIC CLK" }, + { "DMIC R1", NULL, "DMIC CLK" }, + { "DMIC L2", NULL, "DMIC CLK" }, + { "DMIC R2", NULL, "DMIC CLK" }, + { "DMIC L3", NULL, "DMIC CLK" }, + { "DMIC R3", NULL, "DMIC CLK" }, + { "DMIC L4", NULL, "DMIC CLK" }, + { "DMIC R4", NULL, "DMIC CLK" }, + + { "BST1", NULL, "IN1P" }, + { "BST1", NULL, "IN1N" }, + { "BST2", NULL, "IN2P" }, + { "BST2", NULL, "IN2N" }, + + { "IN1P", NULL, "micbias1" }, + { "IN1N", NULL, "micbias1" }, + { "IN2P", NULL, "micbias1" }, + { "IN2N", NULL, "micbias1" }, + + { "ADC 1", NULL, "BST1" }, + { "ADC 1", NULL, "ADC 1 power" }, + { "ADC 1", NULL, "ADC1 clock" }, + { "ADC 2", NULL, "BST2" }, + { "ADC 2", NULL, "ADC 2 power" }, + { "ADC 2", NULL, "ADC2 clock" }, + + { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, + { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, + { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, + { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, + + { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, + { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, + { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, + { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, + + { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, + { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, + { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, + { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, + + { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, + { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, + { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, + { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, + + { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, + { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, + { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, + { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, + + { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, + { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, + { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, + { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, + + { "ADC 1_2", NULL, "ADC 1" }, + { "ADC 1_2", NULL, "ADC 2" }, + + { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, + { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, + { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, + + { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, + { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, + { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, + + { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, + { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, + { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, + + { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, + { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, + { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, + + { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, + { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, + { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, + + { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, + { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, + { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, + + { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, + { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, + { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, + + { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, + { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, + { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, + + { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, + { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, + { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, + + { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, + { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, + { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, + + { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, + { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, + { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, + + { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, + { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, + { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, + + { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, + { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, + { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, + { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, + + { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, + { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, + { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, + + { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, + { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, + { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, + + { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, + { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, + + { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, + { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, + { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, + { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, + + { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, + { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, + + { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, + { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, + + { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, + { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, + { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, + + { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, + { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, + { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, + + { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, + { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, + + { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, + { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, + { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, + { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, + + { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, + { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, + { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, + + { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, + { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, + { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, + + { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, + { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, + + { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, + { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, + { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, + { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, + + { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, + { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, + { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, + + { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, + { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, + { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, + + { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, + { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, + + { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, + { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, + { "Mono ADC MIXL", NULL, "adc mono left filter" }, + { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, + + { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, + { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, + { "Mono ADC MIXR", NULL, "adc mono right filter" }, + { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, + + { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, + { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, + + { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, + { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, + { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, + { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, + { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, + + { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, + { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, + { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, + + { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, + { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, + + { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, + { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, + { "IF1 ADC3 Mux", "OB45", "OB45" }, + + { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, + { "IF1 ADC4 Mux", "OB67", "OB67" }, + { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, + + { "AIF1TX", NULL, "I2S1" }, + { "AIF1TX", NULL, "IF1 ADC1 Mux" }, + { "AIF1TX", NULL, "IF1 ADC2 Mux" }, + { "AIF1TX", NULL, "IF1 ADC3 Mux" }, + { "AIF1TX", NULL, "IF1 ADC4 Mux" }, + + { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, + { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, + { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, + + { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, + { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, + + { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, + { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, + { "IF2 ADC3 Mux", "OB45", "OB45" }, + + { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, + { "IF2 ADC4 Mux", "OB67", "OB67" }, + { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, + + { "AIF2TX", NULL, "I2S2" }, + { "AIF2TX", NULL, "IF2 ADC1 Mux" }, + { "AIF2TX", NULL, "IF2 ADC2 Mux" }, + { "AIF2TX", NULL, "IF2 ADC3 Mux" }, + { "AIF2TX", NULL, "IF2 ADC4 Mux" }, + + { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, + { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, + { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, + { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, + { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, + { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, + { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, + { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, + + { "AIF3TX", NULL, "I2S3" }, + { "AIF3TX", NULL, "IF3 ADC Mux" }, + + { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, + { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, + { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, + { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, + { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, + { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, + { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, + { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, + + { "AIF4TX", NULL, "I2S4" }, + { "AIF4TX", NULL, "IF4 ADC Mux" }, + + { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, + { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, + { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, + + { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, + { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, + + { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, + { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, + { "SLB ADC3 Mux", "OB45", "OB45" }, + + { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, + { "SLB ADC4 Mux", "OB67", "OB67" }, + { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, + + { "SLBTX", NULL, "SLB" }, + { "SLBTX", NULL, "SLB ADC1 Mux" }, + { "SLBTX", NULL, "SLB ADC2 Mux" }, + { "SLBTX", NULL, "SLB ADC3 Mux" }, + { "SLBTX", NULL, "SLB ADC4 Mux" }, + + { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, + { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, + { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, + { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, + { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" }, + + { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, + { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, + + { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, + { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, + { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, + { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, + { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, + { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, + + { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, + { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, + + { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, + { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, + { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, + { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, + { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, + + { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, + { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, + + { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" }, + { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" }, + { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, + { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, + { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, + { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, + { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, + { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, + + { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" }, + { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" }, + { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, + { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, + { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, + { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, + { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, + { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, + + { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, + { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, + { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, + { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, + { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, + { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, + + { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, + { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, + { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, + { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, + { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, + { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, + { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, + + { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, + { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, + { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, + { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, + { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, + { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, + { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, + + { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, + { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, + { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, + { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, + { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, + { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, + { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, + + { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, + { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, + { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, + { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, + { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, + { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, + { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, + + { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, + { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, + { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, + { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, + { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, + { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, + { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, + + { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, + { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, + { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, + { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, + { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, + { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, + { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, + + { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, + { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, + { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, + { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, + { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, + { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, + { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, + + { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, + { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, + { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, + { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, + + { "OutBound2", NULL, "OB23 Bypass Mux" }, + { "OutBound3", NULL, "OB23 Bypass Mux" }, + { "OutBound4", NULL, "OB4 MIX" }, + { "OutBound5", NULL, "OB5 MIX" }, + { "OutBound6", NULL, "OB6 MIX" }, + { "OutBound7", NULL, "OB7 MIX" }, + + { "OB45", NULL, "OutBound4" }, + { "OB45", NULL, "OutBound5" }, + { "OB67", NULL, "OutBound6" }, + { "OB67", NULL, "OutBound7" }, + + { "IF1 DAC0", NULL, "AIF1RX" }, + { "IF1 DAC1", NULL, "AIF1RX" }, + { "IF1 DAC2", NULL, "AIF1RX" }, + { "IF1 DAC3", NULL, "AIF1RX" }, + { "IF1 DAC4", NULL, "AIF1RX" }, + { "IF1 DAC5", NULL, "AIF1RX" }, + { "IF1 DAC6", NULL, "AIF1RX" }, + { "IF1 DAC7", NULL, "AIF1RX" }, + { "IF1 DAC0", NULL, "I2S1" }, + { "IF1 DAC1", NULL, "I2S1" }, + { "IF1 DAC2", NULL, "I2S1" }, + { "IF1 DAC3", NULL, "I2S1" }, + { "IF1 DAC4", NULL, "I2S1" }, + { "IF1 DAC5", NULL, "I2S1" }, + { "IF1 DAC6", NULL, "I2S1" }, + { "IF1 DAC7", NULL, "I2S1" }, + + { "IF1 DAC01", NULL, "IF1 DAC0" }, + { "IF1 DAC01", NULL, "IF1 DAC1" }, + { "IF1 DAC23", NULL, "IF1 DAC2" }, + { "IF1 DAC23", NULL, "IF1 DAC3" }, + { "IF1 DAC45", NULL, "IF1 DAC4" }, + { "IF1 DAC45", NULL, "IF1 DAC5" }, + { "IF1 DAC67", NULL, "IF1 DAC6" }, + { "IF1 DAC67", NULL, "IF1 DAC7" }, + + { "IF2 DAC0", NULL, "AIF2RX" }, + { "IF2 DAC1", NULL, "AIF2RX" }, + { "IF2 DAC2", NULL, "AIF2RX" }, + { "IF2 DAC3", NULL, "AIF2RX" }, + { "IF2 DAC4", NULL, "AIF2RX" }, + { "IF2 DAC5", NULL, "AIF2RX" }, + { "IF2 DAC6", NULL, "AIF2RX" }, + { "IF2 DAC7", NULL, "AIF2RX" }, + { "IF2 DAC0", NULL, "I2S2" }, + { "IF2 DAC1", NULL, "I2S2" }, + { "IF2 DAC2", NULL, "I2S2" }, + { "IF2 DAC3", NULL, "I2S2" }, + { "IF2 DAC4", NULL, "I2S2" }, + { "IF2 DAC5", NULL, "I2S2" }, + { "IF2 DAC6", NULL, "I2S2" }, + { "IF2 DAC7", NULL, "I2S2" }, + + { "IF2 DAC01", NULL, "IF2 DAC0" }, + { "IF2 DAC01", NULL, "IF2 DAC1" }, + { "IF2 DAC23", NULL, "IF2 DAC2" }, + { "IF2 DAC23", NULL, "IF2 DAC3" }, + { "IF2 DAC45", NULL, "IF2 DAC4" }, + { "IF2 DAC45", NULL, "IF2 DAC5" }, + { "IF2 DAC67", NULL, "IF2 DAC6" }, + { "IF2 DAC67", NULL, "IF2 DAC7" }, + + { "IF3 DAC", NULL, "AIF3RX" }, + { "IF3 DAC", NULL, "I2S3" }, + + { "IF4 DAC", NULL, "AIF4RX" }, + { "IF4 DAC", NULL, "I2S4" }, + + { "IF3 DAC L", NULL, "IF3 DAC" }, + { "IF3 DAC R", NULL, "IF3 DAC" }, + + { "IF4 DAC L", NULL, "IF4 DAC" }, + { "IF4 DAC R", NULL, "IF4 DAC" }, + + { "SLB DAC0", NULL, "SLBRX" }, + { "SLB DAC1", NULL, "SLBRX" }, + { "SLB DAC2", NULL, "SLBRX" }, + { "SLB DAC3", NULL, "SLBRX" }, + { "SLB DAC4", NULL, "SLBRX" }, + { "SLB DAC5", NULL, "SLBRX" }, + { "SLB DAC6", NULL, "SLBRX" }, + { "SLB DAC7", NULL, "SLBRX" }, + { "SLB DAC0", NULL, "SLB" }, + { "SLB DAC1", NULL, "SLB" }, + { "SLB DAC2", NULL, "SLB" }, + { "SLB DAC3", NULL, "SLB" }, + { "SLB DAC4", NULL, "SLB" }, + { "SLB DAC5", NULL, "SLB" }, + { "SLB DAC6", NULL, "SLB" }, + { "SLB DAC7", NULL, "SLB" }, + + { "SLB DAC01", NULL, "SLB DAC0" }, + { "SLB DAC01", NULL, "SLB DAC1" }, + { "SLB DAC23", NULL, "SLB DAC2" }, + { "SLB DAC23", NULL, "SLB DAC3" }, + { "SLB DAC45", NULL, "SLB DAC4" }, + { "SLB DAC45", NULL, "SLB DAC5" }, + { "SLB DAC67", NULL, "SLB DAC6" }, + { "SLB DAC67", NULL, "SLB DAC7" }, + + { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, + { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, + { "ADDA1 Mux", "OB 67", "OB67" }, + + { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, + { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, + { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, + { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, + { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, + { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, + + { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, + { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, + { "DAC1 MIXL", NULL, "dac stereo1 filter" }, + { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, + { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, + { "DAC1 MIXR", NULL, "dac stereo1 filter" }, + + { "DAC1 FS", NULL, "DAC1 MIXL" }, + { "DAC1 FS", NULL, "DAC1 MIXR" }, + + { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" }, + { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" }, + { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, + { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, + { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, + { "DAC2 L Mux", "OB 2", "OutBound2" }, + + { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" }, + { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" }, + { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, + { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, + { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, + { "DAC2 R Mux", "OB 3", "OutBound3" }, + { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, + { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, + + { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" }, + { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" }, + { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, + { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, + { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, + { "DAC3 L Mux", "OB 4", "OutBound4" }, + + { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" }, + { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" }, + { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, + { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, + { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, + { "DAC3 R Mux", "OB 5", "OutBound5" }, + + { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" }, + { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" }, + { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, + { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, + { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, + { "DAC4 L Mux", "OB 6", "OutBound6" }, + + { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" }, + { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" }, + { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, + { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, + { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, + { "DAC4 R Mux", "OB 7", "OutBound7" }, + + { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, + { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, + { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, + { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, + { "Sidetone Mux", "ADC1", "ADC 1" }, + { "Sidetone Mux", "ADC2", "ADC 2" }, + + { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, + { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, + { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, + { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, + { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, + { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, + { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, + { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, + { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, + { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, + + { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, + { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, + { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, + { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, + { "Mono DAC MIXL", NULL, "dac mono left filter" }, + { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, + { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, + { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, + { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, + { "Mono DAC MIXR", NULL, "dac mono right filter" }, + + { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, + { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, + { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, + { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, + { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, + { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, + { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, + { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, + + { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, + { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, + { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, + { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, + { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, + { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, + { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, + { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, + + { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, + { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, + { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, + { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, + { "DD1 MIX", NULL, "DD1 MIXL" }, + { "DD1 MIX", NULL, "DD1 MIXR" }, + { "DD2 MIX", NULL, "DD2 MIXL" }, + { "DD2 MIX", NULL, "DD2 MIXR" }, + + { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, + { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, + { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, + { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, + + { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, + { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, + { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, + { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, + + { "DAC 1", NULL, "DAC12 SRC Mux" }, + { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll }, + { "DAC 2", NULL, "DAC12 SRC Mux" }, + { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll }, + { "DAC 3", NULL, "DAC3 SRC Mux" }, + { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll }, + + { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, + { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, + { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, + { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, + { "PDM1 L Mux", NULL, "PDM1 Power" }, + { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, + { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, + { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, + { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, + { "PDM1 R Mux", NULL, "PDM1 Power" }, + { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, + { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, + { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, + { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, + { "PDM2 L Mux", NULL, "PDM2 Power" }, + { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, + { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, + { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, + { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, + { "PDM2 R Mux", NULL, "PDM2 Power" }, + + { "LOUT1 amp", NULL, "DAC 1" }, + { "LOUT2 amp", NULL, "DAC 2" }, + { "LOUT3 amp", NULL, "DAC 3" }, + + { "LOUT1", NULL, "LOUT1 amp" }, + { "LOUT2", NULL, "LOUT2 amp" }, + { "LOUT3", NULL, "LOUT3 amp" }, + + { "PDM1L", NULL, "PDM1 L Mux" }, + { "PDM1R", NULL, "PDM1 R Mux" }, + { "PDM2L", NULL, "PDM2 L Mux" }, + { "PDM2R", NULL, "PDM2 R Mux" }, +}; + +static int get_clk_info(int sclk, int rate) +{ + int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16}; + + if (sclk <= 0 || rate <= 0) + return -EINVAL; + + rate = rate << 8; + for (i = 0; i < ARRAY_SIZE(pd); i++) + if (sclk == rate * pd[i]) + return i; + + return -EINVAL; +} + +static int rt5677_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + unsigned int val_len = 0, val_clk, mask_clk; + int pre_div, bclk_ms, frame_size; + + rt5677->lrck[dai->id] = params_rate(params); + pre_div = get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); + if (pre_div < 0) { + dev_err(codec->dev, "Unsupported clock setting\n"); + return -EINVAL; + } + frame_size = snd_soc_params_to_frame_size(params); + if (frame_size < 0) { + dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); + return -EINVAL; + } + bclk_ms = frame_size > 32; + rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); + + dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", + rt5677->bclk[dai->id], rt5677->lrck[dai->id]); + dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", + bclk_ms, pre_div, dai->id); + + switch (params_width(params)) { + case 16: + break; + case 20: + val_len |= RT5677_I2S_DL_20; + break; + case 24: + val_len |= RT5677_I2S_DL_24; + break; + case 8: + val_len |= RT5677_I2S_DL_8; + break; + default: + return -EINVAL; + } + + switch (dai->id) { + case RT5677_AIF1: + mask_clk = RT5677_I2S_PD1_MASK; + val_clk = pre_div << RT5677_I2S_PD1_SFT; + regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, + RT5677_I2S_DL_MASK, val_len); + regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, + mask_clk, val_clk); + break; + case RT5677_AIF2: + mask_clk = RT5677_I2S_PD2_MASK; + val_clk = pre_div << RT5677_I2S_PD2_SFT; + regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, + RT5677_I2S_DL_MASK, val_len); + regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, + mask_clk, val_clk); + break; + case RT5677_AIF3: + mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; + val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | + pre_div << RT5677_I2S_PD3_SFT; + regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, + RT5677_I2S_DL_MASK, val_len); + regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, + mask_clk, val_clk); + break; + case RT5677_AIF4: + mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; + val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | + pre_div << RT5677_I2S_PD4_SFT; + regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, + RT5677_I2S_DL_MASK, val_len); + regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, + mask_clk, val_clk); + break; + default: + break; + } + + return 0; +} + +static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = dai->codec; + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + unsigned int reg_val = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + rt5677->master[dai->id] = 1; + break; + case SND_SOC_DAIFMT_CBS_CFS: + reg_val |= RT5677_I2S_MS_S; + rt5677->master[dai->id] = 0; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_NF: + reg_val |= RT5677_I2S_BP_INV; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + break; + case SND_SOC_DAIFMT_LEFT_J: + reg_val |= RT5677_I2S_DF_LEFT; + break; + case SND_SOC_DAIFMT_DSP_A: + reg_val |= RT5677_I2S_DF_PCM_A; + break; + case SND_SOC_DAIFMT_DSP_B: + reg_val |= RT5677_I2S_DF_PCM_B; + break; + default: + return -EINVAL; + } + + switch (dai->id) { + case RT5677_AIF1: + regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, + RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | + RT5677_I2S_DF_MASK, reg_val); + break; + case RT5677_AIF2: + regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, + RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | + RT5677_I2S_DF_MASK, reg_val); + break; + case RT5677_AIF3: + regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, + RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | + RT5677_I2S_DF_MASK, reg_val); + break; + case RT5677_AIF4: + regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, + RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | + RT5677_I2S_DF_MASK, reg_val); + break; + default: + break; + } + + + return 0; +} + +static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + unsigned int reg_val = 0; + + if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) + return 0; + + switch (clk_id) { + case RT5677_SCLK_S_MCLK: + reg_val |= RT5677_SCLK_SRC_MCLK; + break; + case RT5677_SCLK_S_PLL1: + reg_val |= RT5677_SCLK_SRC_PLL1; + break; + case RT5677_SCLK_S_RCCLK: + reg_val |= RT5677_SCLK_SRC_RCCLK; + break; + default: + dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); + return -EINVAL; + } + regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, + RT5677_SCLK_SRC_MASK, reg_val); + rt5677->sysclk = freq; + rt5677->sysclk_src = clk_id; + + dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); + + return 0; +} + +/** + * rt5677_pll_calc - Calcualte PLL M/N/K code. + * @freq_in: external clock provided to codec. + * @freq_out: target clock which codec works on. + * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. + * + * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. + * + * Returns 0 for success or negative error code. + */ +static int rt5677_pll_calc(const unsigned int freq_in, + const unsigned int freq_out, struct rt5677_pll_code *pll_code) +{ + int max_n = RT5677_PLL_N_MAX, max_m = RT5677_PLL_M_MAX; + int k, red, n_t, pll_out, in_t; + int n = 0, m = 0, m_t = 0; + int out_t, red_t = abs(freq_out - freq_in); + bool m_bp = false, k_bp = false; + + if (RT5677_PLL_INP_MAX < freq_in || RT5677_PLL_INP_MIN > freq_in) + return -EINVAL; + + k = 100000000 / freq_out - 2; + if (k > RT5677_PLL_K_MAX) + k = RT5677_PLL_K_MAX; + for (n_t = 0; n_t <= max_n; n_t++) { + in_t = freq_in / (k + 2); + pll_out = freq_out / (n_t + 2); + if (in_t < 0) + continue; + if (in_t == pll_out) { + m_bp = true; + n = n_t; + goto code_find; + } + red = abs(in_t - pll_out); + if (red < red_t) { + m_bp = true; + n = n_t; + m = m_t; + if (red == 0) + goto code_find; + red_t = red; + } + for (m_t = 0; m_t <= max_m; m_t++) { + out_t = in_t / (m_t + 2); + red = abs(out_t - pll_out); + if (red < red_t) { + m_bp = false; + n = n_t; + m = m_t; + if (red == 0) + goto code_find; + red_t = red; + } + } + } + pr_debug("Only get approximation about PLL\n"); + +code_find: + + pll_code->m_bp = m_bp; + pll_code->k_bp = k_bp; + pll_code->m_code = m; + pll_code->n_code = n; + pll_code->k_code = k; + return 0; +} + +static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, + unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_codec *codec = dai->codec; + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + struct rt5677_pll_code pll_code; + int ret; + + if (source == rt5677->pll_src && freq_in == rt5677->pll_in && + freq_out == rt5677->pll_out) + return 0; + + if (!freq_in || !freq_out) { + dev_dbg(codec->dev, "PLL disabled\n"); + + rt5677->pll_in = 0; + rt5677->pll_out = 0; + regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, + RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); + return 0; + } + + switch (source) { + case RT5677_PLL1_S_MCLK: + regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, + RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); + break; + case RT5677_PLL1_S_BCLK1: + case RT5677_PLL1_S_BCLK2: + case RT5677_PLL1_S_BCLK3: + case RT5677_PLL1_S_BCLK4: + switch (dai->id) { + case RT5677_AIF1: + regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, + RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); + break; + case RT5677_AIF2: + regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, + RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); + break; + case RT5677_AIF3: + regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, + RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); + break; + case RT5677_AIF4: + regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, + RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); + break; + default: + break; + } + break; + default: + dev_err(codec->dev, "Unknown PLL source %d\n", source); + return -EINVAL; + } + + ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); + if (ret < 0) { + dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); + return ret; + } + + dev_dbg(codec->dev, "m_bypass=%d k_bypass=%d m=%d n=%d k=%d\n", + pll_code.m_bp, pll_code.k_bp, + (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code, + (pll_code.k_bp ? 0 : pll_code.k_code)); + + regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, + pll_code.n_code << RT5677_PLL_N_SFT | + pll_code.k_bp << RT5677_PLL_K_BP_SFT | + (pll_code.k_bp ? 0 : pll_code.k_code)); + regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, + (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT | + pll_code.m_bp << RT5677_PLL_M_BP_SFT); + + rt5677->pll_in = freq_in; + rt5677->pll_out = freq_out; + rt5677->pll_src = source; + + return 0; +} + +static int rt5677_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + + switch (level) { + case SND_SOC_BIAS_ON: + break; + + case SND_SOC_BIAS_PREPARE: + if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, + RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, + 0x0055); + regmap_update_bits(rt5677->regmap, + RT5677_PR_BASE + RT5677_BIAS_CUR4, + 0x0f00, 0x0f00); + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, + RT5677_PWR_VREF1 | RT5677_PWR_MB | + RT5677_PWR_BG | RT5677_PWR_VREF2, + RT5677_PWR_VREF1 | RT5677_PWR_MB | + RT5677_PWR_BG | RT5677_PWR_VREF2); + mdelay(20); + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, + RT5677_PWR_FV1 | RT5677_PWR_FV2, + RT5677_PWR_FV1 | RT5677_PWR_FV2); + regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, + RT5677_PWR_CORE, RT5677_PWR_CORE); + regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, + 0x1, 0x1); + } + break; + + case SND_SOC_BIAS_STANDBY: + break; + + case SND_SOC_BIAS_OFF: + regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); + regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); + regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000); + regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0000); + regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); + regmap_update_bits(rt5677->regmap, + RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); + break; + + default: + break; + } + codec->dapm.bias_level = level; + + return 0; +} + +static int rt5677_probe(struct snd_soc_codec *codec) +{ + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + + rt5677->codec = codec; + + rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF); + + regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020); + regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00); + + return 0; +} + +static int rt5677_remove(struct snd_soc_codec *codec) +{ + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + + regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); + + return 0; +} + +#ifdef CONFIG_PM +static int rt5677_suspend(struct snd_soc_codec *codec) +{ + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + + regcache_cache_only(rt5677->regmap, true); + regcache_mark_dirty(rt5677->regmap); + + return 0; +} + +static int rt5677_resume(struct snd_soc_codec *codec) +{ + struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); + + regcache_cache_only(rt5677->regmap, false); + regcache_sync(rt5677->regmap); + + return 0; +} +#else +#define rt5677_suspend NULL +#define rt5677_resume NULL +#endif + +#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 +#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) + +static struct snd_soc_dai_ops rt5677_aif_dai_ops = { + .hw_params = rt5677_hw_params, + .set_fmt = rt5677_set_dai_fmt, + .set_sysclk = rt5677_set_dai_sysclk, + .set_pll = rt5677_set_dai_pll, +}; + +static struct snd_soc_dai_driver rt5677_dai[] = { + { + .name = "rt5677-aif1", + .id = RT5677_AIF1, + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT5677_STEREO_RATES, + .formats = RT5677_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT5677_STEREO_RATES, + .formats = RT5677_FORMATS, + }, + .ops = &rt5677_aif_dai_ops, + }, + { + .name = "rt5677-aif2", + .id = RT5677_AIF2, + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT5677_STEREO_RATES, + .formats = RT5677_FORMATS, + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT5677_STEREO_RATES, + .formats = RT5677_FORMATS, + }, + .ops = &rt5677_aif_dai_ops, + }, + { + .name = "rt5677-aif3", + .id = RT5677_AIF3, + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT5677_STEREO_RATES, + .formats = RT5677_FORMATS, + }, + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT5677_STEREO_RATES, + .formats = RT5677_FORMATS, + }, + .ops = &rt5677_aif_dai_ops, + }, + { + .name = "rt5677-aif4", + .id = RT5677_AIF4, + .playback = { + .stream_name = "AIF4 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT5677_STEREO_RATES, + .formats = RT5677_FORMATS, + }, + .capture = { + .stream_name = "AIF4 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT5677_STEREO_RATES, + .formats = RT5677_FORMATS, + }, + .ops = &rt5677_aif_dai_ops, + }, + { + .name = "rt5677-slimbus", + .id = RT5677_AIF5, + .playback = { + .stream_name = "SLIMBus Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT5677_STEREO_RATES, + .formats = RT5677_FORMATS, + }, + .capture = { + .stream_name = "SLIMBus Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT5677_STEREO_RATES, + .formats = RT5677_FORMATS, + }, + .ops = &rt5677_aif_dai_ops, + }, +}; + +static struct snd_soc_codec_driver soc_codec_dev_rt5677 = { + .probe = rt5677_probe, + .remove = rt5677_remove, + .suspend = rt5677_suspend, + .resume = rt5677_resume, + .set_bias_level = rt5677_set_bias_level, + .idle_bias_off = true, + .controls = rt5677_snd_controls, + .num_controls = ARRAY_SIZE(rt5677_snd_controls), + .dapm_widgets = rt5677_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), + .dapm_routes = rt5677_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), +}; + +static const struct regmap_config rt5677_regmap = { + .reg_bits = 8, + .val_bits = 16, + + .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * + RT5677_PR_SPACING), + + .volatile_reg = rt5677_volatile_register, + .readable_reg = rt5677_readable_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = rt5677_reg, + .num_reg_defaults = ARRAY_SIZE(rt5677_reg), + .ranges = rt5677_ranges, + .num_ranges = ARRAY_SIZE(rt5677_ranges), +}; + +static const struct i2c_device_id rt5677_i2c_id[] = { + { "rt5677", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id); + +static int rt5677_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev); + struct rt5677_priv *rt5677; + int ret; + unsigned int val; + + rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), + GFP_KERNEL); + if (rt5677 == NULL) + return -ENOMEM; + + i2c_set_clientdata(i2c, rt5677); + + if (pdata) + rt5677->pdata = *pdata; + + rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap); + if (IS_ERR(rt5677->regmap)) { + ret = PTR_ERR(rt5677->regmap); + dev_err(&i2c->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); + if (val != RT5677_DEVICE_ID) { + dev_err(&i2c->dev, + "Device with ID register %x is not rt5677\n", val); + return -ENODEV; + } + + regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); + + ret = regmap_register_patch(rt5677->regmap, init_list, + ARRAY_SIZE(init_list)); + if (ret != 0) + dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); + + if (rt5677->pdata.in1_diff) + regmap_update_bits(rt5677->regmap, RT5677_IN1, + RT5677_IN_DF1, RT5677_IN_DF1); + + if (rt5677->pdata.in2_diff) + regmap_update_bits(rt5677->regmap, RT5677_IN1, + RT5677_IN_DF2, RT5677_IN_DF2); + + ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677, + rt5677_dai, ARRAY_SIZE(rt5677_dai)); + if (ret < 0) + goto err; + + return 0; +err: + return ret; +} + +static int rt5677_i2c_remove(struct i2c_client *i2c) +{ + snd_soc_unregister_codec(&i2c->dev); + + return 0; +} + +static struct i2c_driver rt5677_i2c_driver = { + .driver = { + .name = "rt5677", + .owner = THIS_MODULE, + }, + .probe = rt5677_i2c_probe, + .remove = rt5677_i2c_remove, + .id_table = rt5677_i2c_id, +}; + +static int __init rt5677_modinit(void) +{ + return i2c_add_driver(&rt5677_i2c_driver); +} +module_init(rt5677_modinit); + +static void __exit rt5677_modexit(void) +{ + i2c_del_driver(&rt5677_i2c_driver); +} +module_exit(rt5677_modexit); + +MODULE_DESCRIPTION("ASoC RT5677 driver"); +MODULE_AUTHOR("Oder Chiou <oder_chiou(a)realtek.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h new file mode 100644 index 0000000..af4e9c7 --- /dev/null +++ b/sound/soc/codecs/rt5677.h @@ -0,0 +1,1451 @@ +/* + * rt5677.h -- RT5677 ALSA SoC audio driver + * + * Copyright 2013 Realtek Semiconductor Corp. + * Author: Oder Chiou <oder_chiou(a)realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __RT5677_H__ +#define __RT5677_H__ + +#include <sound/rt5677.h> + +/* Info */ +#define RT5677_RESET 0x00 +#define RT5677_VENDOR_ID 0xfd +#define RT5677_VENDOR_ID1 0xfe +#define RT5677_VENDOR_ID2 0xff +/* I/O - Output */ +#define RT5677_LOUT1 0x01 +/* I/O - Input */ +#define RT5677_IN1 0x03 +#define RT5677_MICBIAS 0x04 +/* I/O - SLIMBus */ +#define RT5677_SLIMBUS_PARAM 0x07 +#define RT5677_SLIMBUS_RX 0x08 +#define RT5677_SLIMBUS_CTRL 0x09 +/* I/O */ +#define RT5677_SIDETONE_CTRL 0x13 +/* I/O - ADC/DAC */ +#define RT5677_ANA_DAC1_2_3_SRC 0x15 +#define RT5677_IF_DSP_DAC3_4_MIXER 0x16 +#define RT5677_DAC4_DIG_VOL 0x17 +#define RT5677_DAC3_DIG_VOL 0x18 +#define RT5677_DAC1_DIG_VOL 0x19 +#define RT5677_DAC2_DIG_VOL 0x1a +#define RT5677_IF_DSP_DAC2_MIXER 0x1b +#define RT5677_STO1_ADC_DIG_VOL 0x1c +#define RT5677_MONO_ADC_DIG_VOL 0x1d +#define RT5677_STO1_2_ADC_BST 0x1e +#define RT5677_STO2_ADC_DIG_VOL 0x1f +/* Mixer - D-D */ +#define RT5677_ADC_BST_CTRL2 0x20 +#define RT5677_STO3_4_ADC_BST 0x21 +#define RT5677_STO3_ADC_DIG_VOL 0x22 +#define RT5677_STO4_ADC_DIG_VOL 0x23 +#define RT5677_STO4_ADC_MIXER 0x24 +#define RT5677_STO3_ADC_MIXER 0x25 +#define RT5677_STO2_ADC_MIXER 0x26 +#define RT5677_STO1_ADC_MIXER 0x27 +#define RT5677_MONO_ADC_MIXER 0x28 +#define RT5677_ADC_IF_DSP_DAC1_MIXER 0x29 +#define RT5677_STO1_DAC_MIXER 0x2a +#define RT5677_MONO_DAC_MIXER 0x2b +#define RT5677_DD1_MIXER 0x2c +#define RT5677_DD2_MIXER 0x2d +#define RT5677_IF3_DATA 0x2f +#define RT5677_IF4_DATA 0x30 +/* Mixer - PDM */ +#define RT5677_PDM_OUT_CTRL 0x31 +#define RT5677_PDM_DATA_CTRL1 0x32 +#define RT5677_PDM_DATA_CTRL2 0x33 +#define RT5677_PDM1_DATA_CTRL2 0x34 +#define RT5677_PDM1_DATA_CTRL3 0x35 +#define RT5677_PDM1_DATA_CTRL4 0x36 +#define RT5677_PDM2_DATA_CTRL2 0x37 +#define RT5677_PDM2_DATA_CTRL3 0x38 +#define RT5677_PDM2_DATA_CTRL4 0x39 +/* TDM */ +#define RT5677_TDM1_CTRL1 0x3b +#define RT5677_TDM1_CTRL2 0x3c +#define RT5677_TDM1_CTRL3 0x3d +#define RT5677_TDM1_CTRL4 0x3e +#define RT5677_TDM1_CTRL5 0x3f +#define RT5677_TDM2_CTRL1 0x40 +#define RT5677_TDM2_CTRL2 0x41 +#define RT5677_TDM2_CTRL3 0x42 +#define RT5677_TDM2_CTRL4 0x43 +#define RT5677_TDM2_CTRL5 0x44 +/* I2C_MASTER_CTRL */ +#define RT5677_I2C_MASTER_CTRL1 0x47 +#define RT5677_I2C_MASTER_CTRL2 0x48 +#define RT5677_I2C_MASTER_CTRL3 0x49 +#define RT5677_I2C_MASTER_CTRL4 0x4a +#define RT5677_I2C_MASTER_CTRL5 0x4b +#define RT5677_I2C_MASTER_CTRL6 0x4c +#define RT5677_I2C_MASTER_CTRL7 0x4d +#define RT5677_I2C_MASTER_CTRL8 0x4e +/* DMIC */ +#define RT5677_DMIC_CTRL1 0x50 +#define RT5677_DMIC_CTRL2 0x51 +/* Haptic Generator */ +#define RT5677_HAP_GENE_CTRL1 0x56 +#define RT5677_HAP_GENE_CTRL2 0x57 +#define RT5677_HAP_GENE_CTRL3 0x58 +#define RT5677_HAP_GENE_CTRL4 0x59 +#define RT5677_HAP_GENE_CTRL5 0x5a +#define RT5677_HAP_GENE_CTRL6 0x5b +#define RT5677_HAP_GENE_CTRL7 0x5c +#define RT5677_HAP_GENE_CTRL8 0x5d +#define RT5677_HAP_GENE_CTRL9 0x5e +#define RT5677_HAP_GENE_CTRL10 0x5f +/* Power */ +#define RT5677_PWR_DIG1 0x61 +#define RT5677_PWR_DIG2 0x62 +#define RT5677_PWR_ANLG1 0x63 +#define RT5677_PWR_ANLG2 0x64 +#define RT5677_PWR_DSP1 0x65 +#define RT5677_PWR_DSP_ST 0x66 +#define RT5677_PWR_DSP2 0x67 +#define RT5677_ADC_DAC_HPF_CTRL1 0x68 +/* Private Register Control */ +#define RT5677_PRIV_INDEX 0x6a +#define RT5677_PRIV_DATA 0x6c +/* Format - ADC/DAC */ +#define RT5677_I2S4_SDP 0x6f +#define RT5677_I2S1_SDP 0x70 +#define RT5677_I2S2_SDP 0x71 +#define RT5677_I2S3_SDP 0x72 +#define RT5677_CLK_TREE_CTRL1 0x73 +#define RT5677_CLK_TREE_CTRL2 0x74 +#define RT5677_CLK_TREE_CTRL3 0x75 +/* Function - Analog */ +#define RT5677_PLL1_CTRL1 0x7a +#define RT5677_PLL1_CTRL2 0x7b +#define RT5677_PLL2_CTRL1 0x7c +#define RT5677_PLL2_CTRL2 0x7d +#define RT5677_GLB_CLK1 0x80 +#define RT5677_GLB_CLK2 0x81 +#define RT5677_ASRC_1 0x83 +#define RT5677_ASRC_2 0x84 +#define RT5677_ASRC_3 0x85 +#define RT5677_ASRC_4 0x86 +#define RT5677_ASRC_5 0x87 +#define RT5677_ASRC_6 0x88 +#define RT5677_ASRC_7 0x89 +#define RT5677_ASRC_8 0x8a +#define RT5677_ASRC_9 0x8b +#define RT5677_ASRC_10 0x8c +#define RT5677_ASRC_11 0x8d +#define RT5677_ASRC_12 0x8e +#define RT5677_ASRC_13 0x8f +#define RT5677_ASRC_14 0x90 +#define RT5677_ASRC_15 0x91 +#define RT5677_ASRC_16 0x92 +#define RT5677_ASRC_17 0x93 +#define RT5677_ASRC_18 0x94 +#define RT5677_ASRC_19 0x95 +#define RT5677_ASRC_20 0x97 +#define RT5677_ASRC_21 0x98 +#define RT5677_ASRC_22 0x99 +#define RT5677_ASRC_23 0x9a +#define RT5677_VAD_CTRL1 0x9c +#define RT5677_VAD_CTRL2 0x9d +#define RT5677_VAD_CTRL3 0x9e +#define RT5677_VAD_CTRL4 0x9f +#define RT5677_VAD_CTRL5 0xa0 +/* Function - Digital */ +#define RT5677_DSP_INB_CTRL1 0xa3 +#define RT5677_DSP_INB_CTRL2 0xa4 +#define RT5677_DSP_IN_OUTB_CTRL 0xa5 +#define RT5677_DSP_OUTB0_1_DIG_VOL 0xa6 +#define RT5677_DSP_OUTB2_3_DIG_VOL 0xa7 +#define RT5677_DSP_OUTB4_5_DIG_VOL 0xa8 +#define RT5677_DSP_OUTB6_7_DIG_VOL 0xa9 +#define RT5677_ADC_EQ_CTRL1 0xae +#define RT5677_ADC_EQ_CTRL2 0xaf +#define RT5677_EQ_CTRL1 0xb0 +#define RT5677_EQ_CTRL2 0xb1 +#define RT5677_EQ_CTRL3 0xb2 +#define RT5677_SOFT_VOL_ZERO_CROSS1 0xb3 +#define RT5677_JD_CTRL1 0xb5 +#define RT5677_JD_CTRL2 0xb6 +#define RT5677_JD_CTRL3 0xb8 +#define RT5677_IRQ_CTRL1 0xbd +#define RT5677_IRQ_CTRL2 0xbe +#define RT5677_GPIO_ST 0xbf +#define RT5677_GPIO_CTRL1 0xc0 +#define RT5677_GPIO_CTRL2 0xc1 +#define RT5677_GPIO_CTRL3 0xc2 +#define RT5677_STO1_ADC_HI_FILTER1 0xc5 +#define RT5677_STO1_ADC_HI_FILTER2 0xc6 +#define RT5677_MONO_ADC_HI_FILTER1 0xc7 +#define RT5677_MONO_ADC_HI_FILTER2 0xc8 +#define RT5677_STO2_ADC_HI_FILTER1 0xc9 +#define RT5677_STO2_ADC_HI_FILTER2 0xca +#define RT5677_STO3_ADC_HI_FILTER1 0xcb +#define RT5677_STO3_ADC_HI_FILTER2 0xcc +#define RT5677_STO4_ADC_HI_FILTER1 0xcd +#define RT5677_STO4_ADC_HI_FILTER2 0xce +#define RT5677_MB_DRC_CTRL1 0xd0 +#define RT5677_DRC1_CTRL1 0xd2 +#define RT5677_DRC1_CTRL2 0xd3 +#define RT5677_DRC1_CTRL3 0xd4 +#define RT5677_DRC1_CTRL4 0xd5 +#define RT5677_DRC1_CTRL5 0xd6 +#define RT5677_DRC1_CTRL6 0xd7 +#define RT5677_DRC2_CTRL1 0xd8 +#define RT5677_DRC2_CTRL2 0xd9 +#define RT5677_DRC2_CTRL3 0xda +#define RT5677_DRC2_CTRL4 0xdb +#define RT5677_DRC2_CTRL5 0xdc +#define RT5677_DRC2_CTRL6 0xdd +#define RT5677_DRC1_HL_CTRL1 0xde +#define RT5677_DRC1_HL_CTRL2 0xdf +#define RT5677_DRC2_HL_CTRL1 0xe0 +#define RT5677_DRC2_HL_CTRL2 0xe1 +#define RT5677_DSP_INB1_SRC_CTRL1 0xe3 +#define RT5677_DSP_INB1_SRC_CTRL2 0xe4 +#define RT5677_DSP_INB1_SRC_CTRL3 0xe5 +#define RT5677_DSP_INB1_SRC_CTRL4 0xe6 +#define RT5677_DSP_INB2_SRC_CTRL1 0xe7 +#define RT5677_DSP_INB2_SRC_CTRL2 0xe8 +#define RT5677_DSP_INB2_SRC_CTRL3 0xe9 +#define RT5677_DSP_INB2_SRC_CTRL4 0xea +#define RT5677_DSP_INB3_SRC_CTRL1 0xeb +#define RT5677_DSP_INB3_SRC_CTRL2 0xec +#define RT5677_DSP_INB3_SRC_CTRL3 0xed +#define RT5677_DSP_INB3_SRC_CTRL4 0xee +#define RT5677_DSP_OUTB1_SRC_CTRL1 0xef +#define RT5677_DSP_OUTB1_SRC_CTRL2 0xf0 +#define RT5677_DSP_OUTB1_SRC_CTRL3 0xf1 +#define RT5677_DSP_OUTB1_SRC_CTRL4 0xf2 +#define RT5677_DSP_OUTB2_SRC_CTRL1 0xf3 +#define RT5677_DSP_OUTB2_SRC_CTRL2 0xf4 +#define RT5677_DSP_OUTB2_SRC_CTRL3 0xf5 +#define RT5677_DSP_OUTB2_SRC_CTRL4 0xf6 + +/* Virtual DSP Mixer Control */ +#define RT5677_DSP_OUTB_0123_MIXER_CTRL 0xf7 +#define RT5677_DSP_OUTB_45_MIXER_CTRL 0xf8 +#define RT5677_DSP_OUTB_67_MIXER_CTRL 0xf9 + +/* General Control */ +#define RT5677_DIG_MISC 0xfa +#define RT5677_GEN_CTRL1 0xfb +#define RT5677_GEN_CTRL2 0xfc + +/* DSP Mode I2C Control*/ +#define RT5677_DSP_I2C_OP_CODE 0x00 +#define RT5677_DSP_I2C_ADDR_LSB 0x01 +#define RT5677_DSP_I2C_ADDR_MSB 0x02 +#define RT5677_DSP_I2C_DATA_LSB 0x03 +#define RT5677_DSP_I2C_DATA_MSB 0x04 + +/* Index of Codec Private Register definition */ +#define RT5677_PR_DRC1_CTRL_1 0x01 +#define RT5677_PR_DRC1_CTRL_2 0x02 +#define RT5677_PR_DRC1_CTRL_3 0x03 +#define RT5677_PR_DRC1_CTRL_4 0x04 +#define RT5677_PR_DRC1_CTRL_5 0x05 +#define RT5677_PR_DRC1_CTRL_6 0x06 +#define RT5677_PR_DRC1_CTRL_7 0x07 +#define RT5677_PR_DRC2_CTRL_1 0x08 +#define RT5677_PR_DRC2_CTRL_2 0x09 +#define RT5677_PR_DRC2_CTRL_3 0x0a +#define RT5677_PR_DRC2_CTRL_4 0x0b +#define RT5677_PR_DRC2_CTRL_5 0x0c +#define RT5677_PR_DRC2_CTRL_6 0x0d +#define RT5677_PR_DRC2_CTRL_7 0x0e +#define RT5677_BIAS_CUR1 0x10 +#define RT5677_BIAS_CUR2 0x12 +#define RT5677_BIAS_CUR3 0x13 +#define RT5677_BIAS_CUR4 0x14 +#define RT5677_BIAS_CUR5 0x15 +#define RT5677_VREF_LOUT_CTRL 0x17 +#define RT5677_DIG_VOL_CTRL1 0x1a +#define RT5677_DIG_VOL_CTRL2 0x1b +#define RT5677_ANA_ADC_GAIN_CTRL 0x1e +#define RT5677_VAD_SRAM_TEST1 0x20 +#define RT5677_VAD_SRAM_TEST2 0x21 +#define RT5677_VAD_SRAM_TEST3 0x22 +#define RT5677_VAD_SRAM_TEST4 0x23 +#define RT5677_PAD_DRV_CTRL 0x26 +#define RT5677_DIG_IN_PIN_ST_CTRL1 0x29 +#define RT5677_DIG_IN_PIN_ST_CTRL2 0x2a +#define RT5677_DIG_IN_PIN_ST_CTRL3 0x2b +#define RT5677_PLL1_INT 0x38 +#define RT5677_PLL2_INT 0x39 +#define RT5677_TEST_CTRL1 0x3a +#define RT5677_TEST_CTRL2 0x3b +#define RT5677_TEST_CTRL3 0x3c +#define RT5677_CHOP_DAC_ADC 0x3d +#define RT5677_SOFT_DEPOP_DAC_CLK_CTRL 0x3e +#define RT5677_CROSS_OVER_FILTER1 0x90 +#define RT5677_CROSS_OVER_FILTER2 0x91 +#define RT5677_CROSS_OVER_FILTER3 0x92 +#define RT5677_CROSS_OVER_FILTER4 0x93 +#define RT5677_CROSS_OVER_FILTER5 0x94 +#define RT5677_CROSS_OVER_FILTER6 0x95 +#define RT5677_CROSS_OVER_FILTER7 0x96 +#define RT5677_CROSS_OVER_FILTER8 0x97 +#define RT5677_CROSS_OVER_FILTER9 0x98 +#define RT5677_CROSS_OVER_FILTER10 0x99 + +/* global definition */ +#define RT5677_L_MUTE (0x1 << 15) +#define RT5677_L_MUTE_SFT 15 +#define RT5677_VOL_L_MUTE (0x1 << 14) +#define RT5677_VOL_L_SFT 14 +#define RT5677_R_MUTE (0x1 << 7) +#define RT5677_R_MUTE_SFT 7 +#define RT5677_VOL_R_MUTE (0x1 << 6) +#define RT5677_VOL_R_SFT 6 +#define RT5677_L_VOL_MASK (0x3f << 8) +#define RT5677_L_VOL_SFT 8 +#define RT5677_R_VOL_MASK (0x3f) +#define RT5677_R_VOL_SFT 0 + +/* LOUT1 Control (0x01) */ +#define RT5677_LOUT1_L_MUTE (0x1 << 15) +#define RT5677_LOUT1_L_MUTE_SFT (15) +#define RT5677_LOUT1_L_DF (0x1 << 14) +#define RT5677_LOUT1_L_DF_SFT (14) +#define RT5677_LOUT2_L_MUTE (0x1 << 13) +#define RT5677_LOUT2_L_MUTE_SFT (13) +#define RT5677_LOUT2_L_DF (0x1 << 12) +#define RT5677_LOUT2_L_DF_SFT (12) +#define RT5677_LOUT3_L_MUTE (0x1 << 11) +#define RT5677_LOUT3_L_MUTE_SFT (11) +#define RT5677_LOUT3_L_DF (0x1 << 10) +#define RT5677_LOUT3_L_DF_SFT (10) +#define RT5677_LOUT1_ENH_DRV (0x1 << 9) +#define RT5677_LOUT1_ENH_DRV_SFT (9) +#define RT5677_LOUT2_ENH_DRV (0x1 << 8) +#define RT5677_LOUT2_ENH_DRV_SFT (8) +#define RT5677_LOUT3_ENH_DRV (0x1 << 7) +#define RT5677_LOUT3_ENH_DRV_SFT (7) + +/* IN1 Control (0x03) */ +#define RT5677_BST_MASK1 (0xf << 12) +#define RT5677_BST_SFT1 12 +#define RT5677_BST_MASK2 (0xf << 8) +#define RT5677_BST_SFT2 8 +#define RT5677_IN_DF1 (0x1 << 7) +#define RT5677_IN_DF1_SFT 7 +#define RT5677_IN_DF2 (0x1 << 6) +#define RT5677_IN_DF2_SFT 6 + +/* Micbias Control (0x04) */ +#define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15) +#define RT5677_MICBIAS1_OUTVOLT_SFT (15) +#define RT5677_MICBIAS1_OUTVOLT_2_7V (0x0 << 15) +#define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15) +#define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14) +#define RT5677_MICBIAS1_CTRL_VDD_SFT (14) +#define RT5677_MICBIAS1_CTRL_VDD_1_8V (0x0 << 14) +#define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14) +#define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11) +#define RT5677_MICBIAS1_OVCD_SHIFT (11) +#define RT5677_MICBIAS1_OVCD_DIS (0x0 << 11) +#define RT5677_MICBIAS1_OVCD_EN (0x1 << 11) +#define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9) +#define RT5677_MICBIAS1_OVTH_SFT 9 +#define RT5677_MICBIAS1_OVTH_640UA (0x0 << 9) +#define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9) +#define RT5677_MICBIAS1_OVTH_1920UA (0x2 << 9) + +/* SLIMbus Parameter (0x07) */ + +/* SLIMbus Rx (0x08) */ +#define RT5677_SLB_ADC4_MASK (0x3 << 6) +#define RT5677_SLB_ADC4_SFT 6 +#define RT5677_SLB_ADC3_MASK (0x3 << 4) +#define RT5677_SLB_ADC3_SFT 4 +#define RT5677_SLB_ADC2_MASK (0x3 << 2) +#define RT5677_SLB_ADC2_SFT 2 +#define RT5677_SLB_ADC1_MASK (0x3 << 0) +#define RT5677_SLB_ADC1_SFT 0 + +/* SLIMBus control (0x09) */ + +/* Sidetone Control (0x13) */ +#define RT5677_ST_HPF_SEL_MASK (0x7 << 13) +#define RT5677_ST_HPF_SEL_SFT 13 +#define RT5677_ST_HPF_PATH (0x1 << 12) +#define RT5677_ST_HPF_PATH_SFT 12 +#define RT5677_ST_SEL_MASK (0x7 << 9) +#define RT5677_ST_SEL_SFT 9 +#define RT5677_ST_EN (0x1 << 6) +#define RT5677_ST_EN_SFT 6 + +/* Analog DAC1/2/3 Source Control (0x15) */ +#define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4) +#define RT5677_ANA_DAC3_SRC_SEL_SFT 4 +#define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0) +#define RT5677_ANA_DAC1_2_SRC_SEL_SFT 0 + +/* IF/DSP to DAC3/4 Mixer Control (0x16) */ +#define RT5677_M_DAC4_L_VOL (0x1 << 15) +#define RT5677_M_DAC4_L_VOL_SFT 15 +#define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12) +#define RT5677_SEL_DAC4_L_SRC_SFT 12 +#define RT5677_M_DAC4_R_VOL (0x1 << 11) +#define RT5677_M_DAC4_R_VOL_SFT 11 +#define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8) +#define RT5677_SEL_DAC4_R_SRC_SFT 8 +#define RT5677_M_DAC3_L_VOL (0x1 << 7) +#define RT5677_M_DAC3_L_VOL_SFT 7 +#define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4) +#define RT5677_SEL_DAC3_L_SRC_SFT 4 +#define RT5677_M_DAC3_R_VOL (0x1 << 3) +#define RT5677_M_DAC3_R_VOL_SFT 3 +#define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0) +#define RT5677_SEL_DAC3_R_SRC_SFT 0 + +/* DAC4 Digital Volume (0x17) */ +#define RT5677_DAC4_L_VOL_MASK (0xff << 8) +#define RT5677_DAC4_L_VOL_SFT 8 +#define RT5677_DAC4_R_VOL_MASK (0xff) +#define RT5677_DAC4_R_VOL_SFT 0 + +/* DAC3 Digital Volume (0x18) */ +#define RT5677_DAC3_L_VOL_MASK (0xff << 8) +#define RT5677_DAC3_L_VOL_SFT 8 +#define RT5677_DAC3_R_VOL_MASK (0xff) +#define RT5677_DAC3_R_VOL_SFT 0 + +/* DAC3 Digital Volume (0x19) */ +#define RT5677_DAC1_L_VOL_MASK (0xff << 8) +#define RT5677_DAC1_L_VOL_SFT 8 +#define RT5677_DAC1_R_VOL_MASK (0xff) +#define RT5677_DAC1_R_VOL_SFT 0 + +/* DAC2 Digital Volume (0x1a) */ +#define RT5677_DAC2_L_VOL_MASK (0xff << 8) +#define RT5677_DAC2_L_VOL_SFT 8 +#define RT5677_DAC2_R_VOL_MASK (0xff) +#define RT5677_DAC2_R_VOL_SFT 0 + +/* IF/DSP to DAC2 Mixer Control (0x1b) */ +#define RT5677_M_DAC2_L_VOL (0x1 << 7) +#define RT5677_M_DAC2_L_VOL_SFT 7 +#define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4) +#define RT5677_SEL_DAC2_L_SRC_SFT 4 +#define RT5677_M_DAC2_R_VOL (0x1 << 3) +#define RT5677_M_DAC2_R_VOL_SFT 3 +#define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0) +#define RT5677_SEL_DAC2_R_SRC_SFT 0 + +/* Stereo1 ADC Digital Volume Control (0x1c) */ +#define RT5677_STO1_ADC_L_VOL_MASK (0x7f << 8) +#define RT5677_STO1_ADC_L_VOL_SFT 8 +#define RT5677_STO1_ADC_R_VOL_MASK (0x7f) +#define RT5677_STO1_ADC_R_VOL_SFT 0 + +/* Mono ADC Digital Volume Control (0x1d) */ +#define RT5677_MONO_ADC_L_VOL_MASK (0x7f << 8) +#define RT5677_MONO_ADC_L_VOL_SFT 8 +#define RT5677_MONO_ADC_R_VOL_MASK (0x7f) +#define RT5677_MONO_ADC_R_VOL_SFT 0 + +/* Stereo 1/2 ADC Boost Gain Control (0x1e) */ +#define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14) +#define RT5677_STO1_ADC_L_BST_SFT 14 +#define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12) +#define RT5677_STO1_ADC_R_BST_SFT 12 +#define RT5677_STO1_ADC_COMP_MASK (0x3 << 10) +#define RT5677_STO1_ADC_COMP_SFT 10 +#define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8) +#define RT5677_STO2_ADC_L_BST_SFT 8 +#define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6) +#define RT5677_STO2_ADC_R_BST_SFT 6 +#define RT5677_STO2_ADC_COMP_MASK (0x3 << 4) +#define RT5677_STO2_ADC_COMP_SFT 4 + +/* Stereo2 ADC Digital Volume Control (0x1f) */ +#define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8) +#define RT5677_STO2_ADC_L_VOL_SFT 8 +#define RT5677_STO2_ADC_R_VOL_MASK (0x7f) +#define RT5677_STO2_ADC_R_VOL_SFT 0 + +/* ADC Boost Gain Control 2 (0x20) */ +#define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14) +#define RT5677_MONO_ADC_L_BST_SFT 14 +#define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12) +#define RT5677_MONO_ADC_R_BST_SFT 12 +#define RT5677_MONO_ADC_COMP_MASK (0x3 << 10) +#define RT5677_MONO_ADC_COMP_SFT 10 + +/* Stereo 3/4 ADC Boost Gain Control (0x21) */ +#define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14) +#define RT5677_STO3_ADC_L_BST_SFT 14 +#define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12) +#define RT5677_STO3_ADC_R_BST_SFT 12 +#define RT5677_STO3_ADC_COMP_MASK (0x3 << 10) +#define RT5677_STO3_ADC_COMP_SFT 10 +#define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8) +#define RT5677_STO4_ADC_L_BST_SFT 8 +#define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6) +#define RT5677_STO4_ADC_R_BST_SFT 6 +#define RT5677_STO4_ADC_COMP_MASK (0x3 << 4) +#define RT5677_STO4_ADC_COMP_SFT 4 + +/* Stereo3 ADC Digital Volume Control (0x22) */ +#define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8) +#define RT5677_STO3_ADC_L_VOL_SFT 8 +#define RT5677_STO3_ADC_R_VOL_MASK (0x7f) +#define RT5677_STO3_ADC_R_VOL_SFT 0 + +/* Stereo4 ADC Digital Volume Control (0x23) */ +#define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8) +#define RT5677_STO4_ADC_L_VOL_SFT 8 +#define RT5677_STO4_ADC_R_VOL_MASK (0x7f) +#define RT5677_STO4_ADC_R_VOL_SFT 0 + +/* Stereo4 ADC Mixer control (0x24) */ +#define RT5677_M_STO4_ADC_L2 (0x1 << 15) +#define RT5677_M_STO4_ADC_L2_SFT 15 +#define RT5677_M_STO4_ADC_L1 (0x1 << 14) +#define RT5677_M_STO4_ADC_L1_SFT 14 +#define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12) +#define RT5677_SEL_STO4_ADC1_SFT 12 +#define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10) +#define RT5677_SEL_STO4_ADC2_SFT 10 +#define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8) +#define RT5677_SEL_STO4_DMIC_SFT 8 +#define RT5677_M_STO4_ADC_R1 (0x1 << 7) +#define RT5677_M_STO4_ADC_R1_SFT 7 +#define RT5677_M_STO4_ADC_R2 (0x1 << 6) +#define RT5677_M_STO4_ADC_R2_SFT 6 + +/* Stereo3 ADC Mixer control (0x25) */ +#define RT5677_M_STO3_ADC_L2 (0x1 << 15) +#define RT5677_M_STO3_ADC_L2_SFT 15 +#define RT5677_M_STO3_ADC_L1 (0x1 << 14) +#define RT5677_M_STO3_ADC_L1_SFT 14 +#define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12) +#define RT5677_SEL_STO3_ADC1_SFT 12 +#define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10) +#define RT5677_SEL_STO3_ADC2_SFT 10 +#define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8) +#define RT5677_SEL_STO3_DMIC_SFT 8 +#define RT5677_M_STO3_ADC_R1 (0x1 << 7) +#define RT5677_M_STO3_ADC_R1_SFT 7 +#define RT5677_M_STO3_ADC_R2 (0x1 << 6) +#define RT5677_M_STO3_ADC_R2_SFT 6 + +/* Stereo2 ADC Mixer Control (0x26) */ +#define RT5677_M_STO2_ADC_L2 (0x1 << 15) +#define RT5677_M_STO2_ADC_L2_SFT 15 +#define RT5677_M_STO2_ADC_L1 (0x1 << 14) +#define RT5677_M_STO2_ADC_L1_SFT 14 +#define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12) +#define RT5677_SEL_STO2_ADC1_SFT 12 +#define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10) +#define RT5677_SEL_STO2_ADC2_SFT 10 +#define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8) +#define RT5677_SEL_STO2_DMIC_SFT 8 +#define RT5677_M_STO2_ADC_R1 (0x1 << 7) +#define RT5677_M_STO2_ADC_R1_SFT 7 +#define RT5677_M_STO2_ADC_R2 (0x1 << 6) +#define RT5677_M_STO2_ADC_R2_SFT 6 +#define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0) +#define RT5677_SEL_STO2_LR_MIX_SFT 0 +#define RT5677_SEL_STO2_LR_MIX_L (0x0 << 0) +#define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0) + +/* Stereo1 ADC Mixer control (0x27) */ +#define RT5677_M_STO1_ADC_L2 (0x1 << 15) +#define RT5677_M_STO1_ADC_L2_SFT 15 +#define RT5677_M_STO1_ADC_L1 (0x1 << 14) +#define RT5677_M_STO1_ADC_L1_SFT 14 +#define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12) +#define RT5677_SEL_STO1_ADC1_SFT 12 +#define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10) +#define RT5677_SEL_STO1_ADC2_SFT 10 +#define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8) +#define RT5677_SEL_STO1_DMIC_SFT 8 +#define RT5677_M_STO1_ADC_R1 (0x1 << 7) +#define RT5677_M_STO1_ADC_R1_SFT 7 +#define RT5677_M_STO1_ADC_R2 (0x1 << 6) +#define RT5677_M_STO1_ADC_R2_SFT 6 + +/* Mono ADC Mixer control (0x28) */ +#define RT5677_M_MONO_ADC_L2 (0x1 << 15) +#define RT5677_M_MONO_ADC_L2_SFT 15 +#define RT5677_M_MONO_ADC_L1 (0x1 << 14) +#define RT5677_M_MONO_ADC_L1_SFT 14 +#define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12) +#define RT5677_SEL_MONO_ADC_L1_SFT 12 +#define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10) +#define RT5677_SEL_MONO_ADC_L2_SFT 10 +#define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8) +#define RT5677_SEL_MONO_DMIC_L_SFT 8 +#define RT5677_M_MONO_ADC_R1 (0x1 << 7) +#define RT5677_M_MONO_ADC_R1_SFT 7 +#define RT5677_M_MONO_ADC_R2 (0x1 << 6) +#define RT5677_M_MONO_ADC_R2_SFT 6 +#define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4) +#define RT5677_SEL_MONO_ADC_R1_SFT 4 +#define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2) +#define RT5677_SEL_MONO_ADC_R2_SFT 2 +#define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0) +#define RT5677_SEL_MONO_DMIC_R_SFT 0 + +/* ADC/IF/DSP to DAC1 Mixer control (0x29) */ +#define RT5677_M_ADDA_MIXER1_L (0x1 << 15) +#define RT5677_M_ADDA_MIXER1_L_SFT 15 +#define RT5677_M_DAC1_L (0x1 << 14) +#define RT5677_M_DAC1_L_SFT 14 +#define RT5677_DAC1_L_SEL_MASK (0x7 << 8) +#define RT5677_DAC1_L_SEL_SFT 8 +#define RT5677_M_ADDA_MIXER1_R (0x1 << 7) +#define RT5677_M_ADDA_MIXER1_R_SFT 7 +#define RT5677_M_DAC1_R (0x1 << 6) +#define RT5677_M_DAC1_R_SFT 6 +#define RT5677_ADDA1_SEL_MASK (0x3 << 0) +#define RT5677_ADDA1_SEL_SFT 0 + +/* Stereo1 DAC Mixer L/R Control (0x2a) */ +#define RT5677_M_ST_DAC1_L (0x1 << 15) +#define RT5677_M_ST_DAC1_L_SFT 15 +#define RT5677_M_DAC1_L_STO_L (0x1 << 13) +#define RT5677_M_DAC1_L_STO_L_SFT 13 +#define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12) +#define RT5677_DAC1_L_STO_L_VOL_SFT 12 +#define RT5677_M_DAC2_L_STO_L (0x1 << 11) +#define RT5677_M_DAC2_L_STO_L_SFT 11 +#define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10) +#define RT5677_DAC2_L_STO_L_VOL_SFT 10 +#define RT5677_M_DAC1_R_STO_L (0x1 << 9) +#define RT5677_M_DAC1_R_STO_L_SFT 9 +#define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8) +#define RT5677_DAC1_R_STO_L_VOL_SFT 8 +#define RT5677_M_ST_DAC1_R (0x1 << 7) +#define RT5677_M_ST_DAC1_R_SFT 7 +#define RT5677_M_DAC1_R_STO_R (0x1 << 5) +#define RT5677_M_DAC1_R_STO_R_SFT 5 +#define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4) +#define RT5677_DAC1_R_STO_R_VOL_SFT 4 +#define RT5677_M_DAC2_R_STO_R (0x1 << 3) +#define RT5677_M_DAC2_R_STO_R_SFT 3 +#define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2) +#define RT5677_DAC2_R_STO_R_VOL_SFT 2 +#define RT5677_M_DAC1_L_STO_R (0x1 << 1) +#define RT5677_M_DAC1_L_STO_R_SFT 1 +#define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0) +#define RT5677_DAC1_L_STO_R_VOL_SFT 0 + +/* Mono DAC Mixer L/R Control (0x2b) */ +#define RT5677_M_ST_DAC2_L (0x1 << 15) +#define RT5677_M_ST_DAC2_L_SFT 15 +#define RT5677_M_DAC2_L_MONO_L (0x1 << 13) +#define RT5677_M_DAC2_L_MONO_L_SFT 13 +#define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12) +#define RT5677_DAC2_L_MONO_L_VOL_SFT 12 +#define RT5677_M_DAC2_R_MONO_L (0x1 << 11) +#define RT5677_M_DAC2_R_MONO_L_SFT 11 +#define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10) +#define RT5677_DAC2_R_MONO_L_VOL_SFT 10 +#define RT5677_M_DAC1_L_MONO_L (0x1 << 9) +#define RT5677_M_DAC1_L_MONO_L_SFT 9 +#define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8) +#define RT5677_DAC1_L_MONO_L_VOL_SFT 8 +#define RT5677_M_ST_DAC2_R (0x1 << 7) +#define RT5677_M_ST_DAC2_R_SFT 7 +#define RT5677_M_DAC2_R_MONO_R (0x1 << 5) +#define RT5677_M_DAC2_R_MONO_R_SFT 5 +#define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4) +#define RT5677_DAC2_R_MONO_R_VOL_SFT 4 +#define RT5677_M_DAC1_R_MONO_R (0x1 << 3) +#define RT5677_M_DAC1_R_MONO_R_SFT 3 +#define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2) +#define RT5677_DAC1_R_MONO_R_VOL_SFT 2 +#define RT5677_M_DAC2_L_MONO_R (0x1 << 1) +#define RT5677_M_DAC2_L_MONO_R_SFT 1 +#define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0) +#define RT5677_DAC2_L_MONO_R_VOL_SFT 0 + +/* DD Mixer 1 Control (0x2c) */ +#define RT5677_M_STO_L_DD1_L (0x1 << 15) +#define RT5677_M_STO_L_DD1_L_SFT 15 +#define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14) +#define RT5677_STO_L_DD1_L_VOL_SFT 14 +#define RT5677_M_MONO_L_DD1_L (0x1 << 13) +#define RT5677_M_MONO_L_DD1_L_SFT 13 +#define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12) +#define RT5677_MONO_L_DD1_L_VOL_SFT 12 +#define RT5677_M_DAC3_L_DD1_L (0x1 << 11) +#define RT5677_M_DAC3_L_DD1_L_SFT 11 +#define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10) +#define RT5677_DAC3_L_DD1_L_VOL_SFT 10 +#define RT5677_M_DAC3_R_DD1_L (0x1 << 9) +#define RT5677_M_DAC3_R_DD1_L_SFT 9 +#define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8) +#define RT5677_DAC3_R_DD1_L_VOL_SFT 8 +#define RT5677_M_STO_R_DD1_R (0x1 << 7) +#define RT5677_M_STO_R_DD1_R_SFT 7 +#define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6) +#define RT5677_STO_R_DD1_R_VOL_SFT 6 +#define RT5677_M_MONO_R_DD1_R (0x1 << 5) +#define RT5677_M_MONO_R_DD1_R_SFT 5 +#define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4) +#define RT5677_MONO_R_DD1_R_VOL_SFT 4 +#define RT5677_M_DAC3_R_DD1_R (0x1 << 3) +#define RT5677_M_DAC3_R_DD1_R_SFT 3 +#define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2) +#define RT5677_DAC3_R_DD1_R_VOL_SFT 2 +#define RT5677_M_DAC3_L_DD1_R (0x1 << 1) +#define RT5677_M_DAC3_L_DD1_R_SFT 1 +#define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0) +#define RT5677_DAC3_L_DD1_R_VOL_SFT 0 + +/* DD Mixer 2 Control (0x2d) */ +#define RT5677_M_STO_L_DD2_L (0x1 << 15) +#define RT5677_M_STO_L_DD2_L_SFT 15 +#define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14) +#define RT5677_STO_L_DD2_L_VOL_SFT 14 +#define RT5677_M_MONO_L_DD2_L (0x1 << 13) +#define RT5677_M_MONO_L_DD2_L_SFT 13 +#define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12) +#define RT5677_MONO_L_DD2_L_VOL_SFT 12 +#define RT5677_M_DAC4_L_DD2_L (0x1 << 11) +#define RT5677_M_DAC4_L_DD2_L_SFT 11 +#define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10) +#define RT5677_DAC4_L_DD2_L_VOL_SFT 10 +#define RT5677_M_DAC4_R_DD2_L (0x1 << 9) +#define RT5677_M_DAC4_R_DD2_L_SFT 9 +#define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8) +#define RT5677_DAC4_R_DD2_L_VOL_SFT 8 +#define RT5677_M_STO_R_DD2_R (0x1 << 7) +#define RT5677_M_STO_R_DD2_R_SFT 7 +#define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6) +#define RT5677_STO_R_DD2_R_VOL_SFT 6 +#define RT5677_M_MONO_R_DD2_R (0x1 << 5) +#define RT5677_M_MONO_R_DD2_R_SFT 5 +#define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4) +#define RT5677_MONO_R_DD2_R_VOL_SFT 4 +#define RT5677_M_DAC4_R_DD2_R (0x1 << 3) +#define RT5677_M_DAC4_R_DD2_R_SFT 3 +#define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2) +#define RT5677_DAC4_R_DD2_R_VOL_SFT 2 +#define RT5677_M_DAC4_L_DD2_R (0x1 << 1) +#define RT5677_M_DAC4_L_DD2_R_SFT 1 +#define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0) +#define RT5677_DAC4_L_DD2_R_VOL_SFT 0 + +/* IF3 data control (0x2f) */ +#define RT5677_IF3_DAC_SEL_MASK (0x3 << 6) +#define RT5677_IF3_DAC_SEL_SFT 6 +#define RT5677_IF3_ADC_SEL_MASK (0x3 << 4) +#define RT5677_IF3_ADC_SEL_SFT 4 +#define RT5677_IF3_ADC_IN_MASK (0xf << 0) +#define RT5677_IF3_ADC_IN_SFT 0 + +/* IF4 data control (0x30) */ +#define RT5677_IF4_ADC_IN_MASK (0xf << 4) +#define RT5677_IF4_ADC_IN_SFT 4 +#define RT5677_IF4_DAC_SEL_MASK (0x3 << 2) +#define RT5677_IF4_DAC_SEL_SFT 2 +#define RT5677_IF4_ADC_SEL_MASK (0x3 << 0) +#define RT5677_IF4_ADC_SEL_SFT 0 + +/* PDM Output Control (0x31) */ +#define RT5677_M_PDM1_L (0x1 << 15) +#define RT5677_M_PDM1_L_SFT 15 +#define RT5677_SEL_PDM1_L_MASK (0x3 << 12) +#define RT5677_SEL_PDM1_L_SFT 12 +#define RT5677_M_PDM1_R (0x1 << 11) +#define RT5677_M_PDM1_R_SFT 11 +#define RT5677_SEL_PDM1_R_MASK (0x3 << 8) +#define RT5677_SEL_PDM1_R_SFT 8 +#define RT5677_M_PDM2_L (0x1 << 7) +#define RT5677_M_PDM2_L_SFT 7 +#define RT5677_SEL_PDM2_L_MASK (0x3 << 4) +#define RT5677_SEL_PDM2_L_SFT 4 +#define RT5677_M_PDM2_R (0x1 << 3) +#define RT5677_M_PDM2_R_SFT 3 +#define RT5677_SEL_PDM2_R_MASK (0x3 << 0) +#define RT5677_SEL_PDM2_R_SFT 0 + +/* PDM I2C / Data Control 1 (0x32) */ +#define RT5677_PDM2_PW_DOWN (0x1 << 7) +#define RT5677_PDM1_PW_DOWN (0x1 << 6) +#define RT5677_PDM2_BUSY (0x1 << 5) +#define RT5677_PDM1_BUSY (0x1 << 4) +#define RT5677_PDM_PATTERN (0x1 << 3) +#define RT5677_PDM_GAIN (0x1 << 2) +#define RT5677_PDM_DIV_MASK (0x3 << 0) + +/* PDM I2C / Data Control 2 (0x33) */ +#define RT5677_PDM1_I2C_ID (0xf << 12) +#define RT5677_PDM1_EXE (0x1 << 11) +#define RT5677_PDM1_I2C_CMD (0x1 << 10) +#define RT5677_PDM1_I2C_EXE (0x1 << 9) +#define RT5677_PDM1_I2C_BUSY (0x1 << 8) +#define RT5677_PDM2_I2C_ID (0xf << 4) +#define RT5677_PDM2_EXE (0x1 << 3) +#define RT5677_PDM2_I2C_CMD (0x1 << 2) +#define RT5677_PDM2_I2C_EXE (0x1 << 1) +#define RT5677_PDM2_I2C_BUSY (0x1 << 0) + +/* MX3C TDM1 control 1 (0x3c) */ +#define RT5677_IF1_ADC4_MASK (0x3 << 10) +#define RT5677_IF1_ADC4_SFT 10 +#define RT5677_IF1_ADC3_MASK (0x3 << 8) +#define RT5677_IF1_ADC3_SFT 8 +#define RT5677_IF1_ADC2_MASK (0x3 << 6) +#define RT5677_IF1_ADC2_SFT 6 +#define RT5677_IF1_ADC1_MASK (0x3 << 4) +#define RT5677_IF1_ADC1_SFT 4 + +/* MX41 TDM2 control 1 (0x41) */ +#define RT5677_IF2_ADC4_MASK (0x3 << 10) +#define RT5677_IF2_ADC4_SFT 10 +#define RT5677_IF2_ADC3_MASK (0x3 << 8) +#define RT5677_IF2_ADC3_SFT 8 +#define RT5677_IF2_ADC2_MASK (0x3 << 6) +#define RT5677_IF2_ADC2_SFT 6 +#define RT5677_IF2_ADC1_MASK (0x3 << 4) +#define RT5677_IF2_ADC1_SFT 4 + +/* Digital Microphone Control 1 (0x50) */ +#define RT5677_DMIC_1_EN_MASK (0x1 << 15) +#define RT5677_DMIC_1_EN_SFT 15 +#define RT5677_DMIC_1_DIS (0x0 << 15) +#define RT5677_DMIC_1_EN (0x1 << 15) +#define RT5677_DMIC_2_EN_MASK (0x1 << 14) +#define RT5677_DMIC_2_EN_SFT 14 +#define RT5677_DMIC_2_DIS (0x0 << 14) +#define RT5677_DMIC_2_EN (0x1 << 14) +#define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13) +#define RT5677_DMIC_L_STO1_LH_SFT 13 +#define RT5677_DMIC_L_STO1_LH_FALLING (0x0 << 13) +#define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13) +#define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12) +#define RT5677_DMIC_R_STO1_LH_SFT 12 +#define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12) +#define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12) +#define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11) +#define RT5677_DMIC_L_STO3_LH_SFT 11 +#define RT5677_DMIC_L_STO3_LH_FALLING (0x0 << 11) +#define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11) +#define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10) +#define RT5677_DMIC_R_STO3_LH_SFT 10 +#define RT5677_DMIC_R_STO3_LH_FALLING (0x0 << 10) +#define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10) +#define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9) +#define RT5677_DMIC_L_STO2_LH_SFT 9 +#define RT5677_DMIC_L_STO2_LH_FALLING (0x0 << 9) +#define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9) +#define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8) +#define RT5677_DMIC_R_STO2_LH_SFT 8 +#define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8) +#define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8) +#define RT5677_DMIC_CLK_MASK (0x7 << 5) +#define RT5677_DMIC_CLK_SFT 5 +#define RT5677_DMIC_3_EN_MASK (0x1 << 4) +#define RT5677_DMIC_3_EN_SFT 4 +#define RT5677_DMIC_3_DIS (0x0 << 4) +#define RT5677_DMIC_3_EN (0x1 << 4) +#define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2) +#define RT5677_DMIC_R_MONO_LH_SFT 2 +#define RT5677_DMIC_R_MONO_LH_FALLING (0x0 << 2) +#define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2) +#define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1) +#define RT5677_DMIC_L_STO4_LH_SFT 1 +#define RT5677_DMIC_L_STO4_LH_FALLING (0x0 << 1) +#define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1) +#define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0) +#define RT5677_DMIC_R_STO4_LH_SFT 0 +#define RT5677_DMIC_R_STO4_LH_FALLING (0x0 << 0) +#define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0) + +/* Digital Microphone Control 2 (0x51) */ +#define RT5677_DMIC_4_EN_MASK (0x1 << 15) +#define RT5677_DMIC_4_EN_SFT 15 +#define RT5677_DMIC_4_DIS (0x0 << 15) +#define RT5677_DMIC_4_EN (0x1 << 15) +#define RT5677_DMIC_4L_LH_MASK (0x1 << 7) +#define RT5677_DMIC_4L_LH_SFT 7 +#define RT5677_DMIC_4L_LH_FALLING (0x0 << 7) +#define RT5677_DMIC_4L_LH_RISING (0x1 << 7) +#define RT5677_DMIC_4R_LH_MASK (0x1 << 6) +#define RT5677_DMIC_4R_LH_SFT 6 +#define RT5677_DMIC_4R_LH_FALLING (0x0 << 6) +#define RT5677_DMIC_4R_LH_RISING (0x1 << 6) +#define RT5677_DMIC_3L_LH_MASK (0x1 << 5) +#define RT5677_DMIC_3L_LH_SFT 5 +#define RT5677_DMIC_3L_LH_FALLING (0x0 << 5) +#define RT5677_DMIC_3L_LH_RISING (0x1 << 5) +#define RT5677_DMIC_3R_LH_MASK (0x1 << 4) +#define RT5677_DMIC_3R_LH_SFT 4 +#define RT5677_DMIC_3R_LH_FALLING (0x0 << 4) +#define RT5677_DMIC_3R_LH_RISING (0x1 << 4) +#define RT5677_DMIC_2L_LH_MASK (0x1 << 3) +#define RT5677_DMIC_2L_LH_SFT 3 +#define RT5677_DMIC_2L_LH_FALLING (0x0 << 3) +#define RT5677_DMIC_2L_LH_RISING (0x1 << 3) +#define RT5677_DMIC_2R_LH_MASK (0x1 << 2) +#define RT5677_DMIC_2R_LH_SFT 2 +#define RT5677_DMIC_2R_LH_FALLING (0x0 << 2) +#define RT5677_DMIC_2R_LH_RISING (0x1 << 2) +#define RT5677_DMIC_1L_LH_MASK (0x1 << 1) +#define RT5677_DMIC_1L_LH_SFT 1 +#define RT5677_DMIC_1L_LH_FALLING (0x0 << 1) +#define RT5677_DMIC_1L_LH_RISING (0x1 << 1) +#define RT5677_DMIC_1R_LH_MASK (0x1 << 0) +#define RT5677_DMIC_1R_LH_SFT 0 +#define RT5677_DMIC_1R_LH_FALLING (0x0 << 0) +#define RT5677_DMIC_1R_LH_RISING (0x1 << 0) + +/* Power Management for Digital 1 (0x61) */ +#define RT5677_PWR_I2S1 (0x1 << 15) +#define RT5677_PWR_I2S1_BIT 15 +#define RT5677_PWR_I2S2 (0x1 << 14) +#define RT5677_PWR_I2S2_BIT 14 +#define RT5677_PWR_I2S3 (0x1 << 13) +#define RT5677_PWR_I2S3_BIT 13 +#define RT5677_PWR_DAC1 (0x1 << 12) +#define RT5677_PWR_DAC1_BIT 12 +#define RT5677_PWR_DAC2 (0x1 << 11) +#define RT5677_PWR_DAC2_BIT 11 +#define RT5677_PWR_I2S4 (0x1 << 10) +#define RT5677_PWR_I2S4_BIT 10 +#define RT5677_PWR_SLB (0x1 << 9) +#define RT5677_PWR_SLB_BIT 9 +#define RT5677_PWR_DAC3 (0x1 << 7) +#define RT5677_PWR_DAC3_BIT 7 +#define RT5677_PWR_ADCFED2 (0x1 << 4) +#define RT5677_PWR_ADCFED2_BIT 4 +#define RT5677_PWR_ADCFED1 (0x1 << 3) +#define RT5677_PWR_ADCFED1_BIT 3 +#define RT5677_PWR_ADC_L (0x1 << 2) +#define RT5677_PWR_ADC_L_BIT 2 +#define RT5677_PWR_ADC_R (0x1 << 1) +#define RT5677_PWR_ADC_R_BIT 1 +#define RT5677_PWR_I2C_MASTER (0x1 << 0) +#define RT5677_PWR_I2C_MASTER_BIT 0 + +/* Power Management for Digital 2 (0x62) */ +#define RT5677_PWR_ADC_S1F (0x1 << 15) +#define RT5677_PWR_ADC_S1F_BIT 15 +#define RT5677_PWR_ADC_MF_L (0x1 << 14) +#define RT5677_PWR_ADC_MF_L_BIT 14 +#define RT5677_PWR_ADC_MF_R (0x1 << 13) +#define RT5677_PWR_ADC_MF_R_BIT 13 +#define RT5677_PWR_DAC_S1F (0x1 << 12) +#define RT5677_PWR_DAC_S1F_BIT 12 +#define RT5677_PWR_DAC_M2F_L (0x1 << 11) +#define RT5677_PWR_DAC_M2F_L_BIT 11 +#define RT5677_PWR_DAC_M2F_R (0x1 << 10) +#define RT5677_PWR_DAC_M2F_R_BIT 10 +#define RT5677_PWR_DAC_M3F_L (0x1 << 9) +#define RT5677_PWR_DAC_M3F_L_BIT 9 +#define RT5677_PWR_DAC_M3F_R (0x1 << 8) +#define RT5677_PWR_DAC_M3F_R_BIT 8 +#define RT5677_PWR_DAC_M4F_L (0x1 << 7) +#define RT5677_PWR_DAC_M4F_L_BIT 7 +#define RT5677_PWR_DAC_M4F_R (0x1 << 6) +#define RT5677_PWR_DAC_M4F_R_BIT 6 +#define RT5677_PWR_ADC_S2F (0x1 << 5) +#define RT5677_PWR_ADC_S2F_BIT 5 +#define RT5677_PWR_ADC_S3F (0x1 << 4) +#define RT5677_PWR_ADC_S3F_BIT 4 +#define RT5677_PWR_ADC_S4F (0x1 << 3) +#define RT5677_PWR_ADC_S4F_BIT 3 +#define RT5677_PWR_PDM1 (0x1 << 2) +#define RT5677_PWR_PDM1_BIT 2 +#define RT5677_PWR_PDM2 (0x1 << 1) +#define RT5677_PWR_PDM2_BIT 1 + +/* Power Management for Analog 1 (0x63) */ +#define RT5677_PWR_VREF1 (0x1 << 15) +#define RT5677_PWR_VREF1_BIT 15 +#define RT5677_PWR_FV1 (0x1 << 14) +#define RT5677_PWR_FV1_BIT 14 +#define RT5677_PWR_MB (0x1 << 13) +#define RT5677_PWR_MB_BIT 13 +#define RT5677_PWR_LO1 (0x1 << 12) +#define RT5677_PWR_LO1_BIT 12 +#define RT5677_PWR_BG (0x1 << 11) +#define RT5677_PWR_BG_BIT 11 +#define RT5677_PWR_LO2 (0x1 << 10) +#define RT5677_PWR_LO2_BIT 10 +#define RT5677_PWR_LO3 (0x1 << 9) +#define RT5677_PWR_LO3_BIT 9 +#define RT5677_PWR_VREF2 (0x1 << 8) +#define RT5677_PWR_VREF2_BIT 8 +#define RT5677_PWR_FV2 (0x1 << 7) +#define RT5677_PWR_FV2_BIT 7 +#define RT5677_LDO2_SEL_MASK (0x7 << 4) +#define RT5677_LDO2_SEL_SFT 4 +#define RT5677_LDO1_SEL_MASK (0x7 << 0) +#define RT5677_LDO1_SEL_SFT 0 + +/* Power Management for Analog 2 (0x64) */ +#define RT5677_PWR_BST1 (0x1 << 15) +#define RT5677_PWR_BST1_BIT 15 +#define RT5677_PWR_BST2 (0x1 << 14) +#define RT5677_PWR_BST2_BIT 14 +#define RT5677_PWR_CLK_MB1 (0x1 << 13) +#define RT5677_PWR_CLK_MB1_BIT 13 +#define RT5677_PWR_SLIM (0x1 << 12) +#define RT5677_PWR_SLIM_BIT 12 +#define RT5677_PWR_MB1 (0x1 << 11) +#define RT5677_PWR_MB1_BIT 11 +#define RT5677_PWR_PP_MB1 (0x1 << 10) +#define RT5677_PWR_PP_MB1_BIT 10 +#define RT5677_PWR_PLL1 (0x1 << 9) +#define RT5677_PWR_PLL1_BIT 9 +#define RT5677_PWR_PLL2 (0x1 << 8) +#define RT5677_PWR_PLL2_BIT 8 +#define RT5677_PWR_CORE (0x1 << 7) +#define RT5677_PWR_CORE_BIT 7 +#define RT5677_PWR_CLK_MB (0x1 << 6) +#define RT5677_PWR_CLK_MB_BIT 6 +#define RT5677_PWR_BST1_P (0x1 << 5) +#define RT5677_PWR_BST1_P_BIT 5 +#define RT5677_PWR_BST2_P (0x1 << 4) +#define RT5677_PWR_BST2_P_BIT 4 +#define RT5677_PWR_IPTV (0x1 << 3) +#define RT5677_PWR_IPTV_BIT 3 +#define RT5677_PWR_25M_CLK (0x1 << 1) +#define RT5677_PWR_25M_CLK_BIT 1 +#define RT5677_PWR_LDO1 (0x1 << 0) +#define RT5677_PWR_LDO1_BIT 0 + +/* Power Management for DSP (0x65) */ +#define RT5677_PWR_SR7 (0x1 << 10) +#define RT5677_PWR_SR7_BIT 10 +#define RT5677_PWR_SR6 (0x1 << 9) +#define RT5677_PWR_SR6_BIT 9 +#define RT5677_PWR_SR5 (0x1 << 8) +#define RT5677_PWR_SR5_BIT 8 +#define RT5677_PWR_SR4 (0x1 << 7) +#define RT5677_PWR_SR4_BIT 7 +#define RT5677_PWR_SR3 (0x1 << 6) +#define RT5677_PWR_SR3_BIT 6 +#define RT5677_PWR_SR2 (0x1 << 5) +#define RT5677_PWR_SR2_BIT 5 +#define RT5677_PWR_SR1 (0x1 << 4) +#define RT5677_PWR_SR1_BIT 4 +#define RT5677_PWR_SR0 (0x1 << 3) +#define RT5677_PWR_SR0_BIT 3 +#define RT5677_PWR_MLT (0x1 << 2) +#define RT5677_PWR_MLT_BIT 2 +#define RT5677_PWR_DSP (0x1 << 1) +#define RT5677_PWR_DSP_BIT 1 +#define RT5677_PWR_DSP_CPU (0x1 << 0) +#define RT5677_PWR_DSP_CPU_BIT 0 + +/* Power Status for DSP (0x66) */ +#define RT5677_PWR_SR7_RDY (0x1 << 9) +#define RT5677_PWR_SR7_RDY_BIT 9 +#define RT5677_PWR_SR6_RDY (0x1 << 8) +#define RT5677_PWR_SR6_RDY_BIT 8 +#define RT5677_PWR_SR5_RDY (0x1 << 7) +#define RT5677_PWR_SR5_RDY_BIT 7 +#define RT5677_PWR_SR4_RDY (0x1 << 6) +#define RT5677_PWR_SR4_RDY_BIT 6 +#define RT5677_PWR_SR3_RDY (0x1 << 5) +#define RT5677_PWR_SR3_RDY_BIT 5 +#define RT5677_PWR_SR2_RDY (0x1 << 4) +#define RT5677_PWR_SR2_RDY_BIT 4 +#define RT5677_PWR_SR1_RDY (0x1 << 3) +#define RT5677_PWR_SR1_RDY_BIT 3 +#define RT5677_PWR_SR0_RDY (0x1 << 2) +#define RT5677_PWR_SR0_RDY_BIT 2 +#define RT5677_PWR_MLT_RDY (0x1 << 1) +#define RT5677_PWR_MLT_RDY_BIT 1 +#define RT5677_PWR_DSP_RDY (0x1 << 0) +#define RT5677_PWR_DSP_RDY_BIT 0 + +/* Power Management for DSP (0x67) */ +#define RT5677_PWR_SLIM_ISO (0x1 << 11) +#define RT5677_PWR_SLIM_ISO_BIT 11 +#define RT5677_PWR_CORE_ISO (0x1 << 10) +#define RT5677_PWR_CORE_ISO_BIT 10 +#define RT5677_PWR_DSP_ISO (0x1 << 9) +#define RT5677_PWR_DSP_ISO_BIT 9 +#define RT5677_PWR_SR7_ISO (0x1 << 8) +#define RT5677_PWR_SR7_ISO_BIT 8 +#define RT5677_PWR_SR6_ISO (0x1 << 7) +#define RT5677_PWR_SR6_ISO_BIT 7 +#define RT5677_PWR_SR5_ISO (0x1 << 6) +#define RT5677_PWR_SR5_ISO_BIT 6 +#define RT5677_PWR_SR4_ISO (0x1 << 5) +#define RT5677_PWR_SR4_ISO_BIT 5 +#define RT5677_PWR_SR3_ISO (0x1 << 4) +#define RT5677_PWR_SR3_ISO_BIT 4 +#define RT5677_PWR_SR2_ISO (0x1 << 3) +#define RT5677_PWR_SR2_ISO_BIT 3 +#define RT5677_PWR_SR1_ISO (0x1 << 2) +#define RT5677_PWR_SR1_ISO_BIT 2 +#define RT5677_PWR_SR0_ISO (0x1 << 1) +#define RT5677_PWR_SR0_ISO_BIT 1 +#define RT5677_PWR_MLT_ISO (0x1 << 0) +#define RT5677_PWR_MLT_ISO_BIT 0 + +/* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */ +#define RT5677_I2S_MS_MASK (0x1 << 15) +#define RT5677_I2S_MS_SFT 15 +#define RT5677_I2S_MS_M (0x0 << 15) +#define RT5677_I2S_MS_S (0x1 << 15) +#define RT5677_I2S_O_CP_MASK (0x3 << 10) +#define RT5677_I2S_O_CP_SFT 10 +#define RT5677_I2S_O_CP_OFF (0x0 << 10) +#define RT5677_I2S_O_CP_U_LAW (0x1 << 10) +#define RT5677_I2S_O_CP_A_LAW (0x2 << 10) +#define RT5677_I2S_I_CP_MASK (0x3 << 8) +#define RT5677_I2S_I_CP_SFT 8 +#define RT5677_I2S_I_CP_OFF (0x0 << 8) +#define RT5677_I2S_I_CP_U_LAW (0x1 << 8) +#define RT5677_I2S_I_CP_A_LAW (0x2 << 8) +#define RT5677_I2S_BP_MASK (0x1 << 7) +#define RT5677_I2S_BP_SFT 7 +#define RT5677_I2S_BP_NOR (0x0 << 7) +#define RT5677_I2S_BP_INV (0x1 << 7) +#define RT5677_I2S_DL_MASK (0x3 << 2) +#define RT5677_I2S_DL_SFT 2 +#define RT5677_I2S_DL_16 (0x0 << 2) +#define RT5677_I2S_DL_20 (0x1 << 2) +#define RT5677_I2S_DL_24 (0x2 << 2) +#define RT5677_I2S_DL_8 (0x3 << 2) +#define RT5677_I2S_DF_MASK (0x3 << 0) +#define RT5677_I2S_DF_SFT 0 +#define RT5677_I2S_DF_I2S (0x0 << 0) +#define RT5677_I2S_DF_LEFT (0x1 << 0) +#define RT5677_I2S_DF_PCM_A (0x2 << 0) +#define RT5677_I2S_DF_PCM_B (0x3 << 0) + +/* Clock Tree Control 1 (0x73) */ +#define RT5677_I2S_PD1_MASK (0x7 << 12) +#define RT5677_I2S_PD1_SFT 12 +#define RT5677_I2S_PD1_1 (0x0 << 12) +#define RT5677_I2S_PD1_2 (0x1 << 12) +#define RT5677_I2S_PD1_3 (0x2 << 12) +#define RT5677_I2S_PD1_4 (0x3 << 12) +#define RT5677_I2S_PD1_6 (0x4 << 12) +#define RT5677_I2S_PD1_8 (0x5 << 12) +#define RT5677_I2S_PD1_12 (0x6 << 12) +#define RT5677_I2S_PD1_16 (0x7 << 12) +#define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11) +#define RT5677_I2S_BCLK_MS2_SFT 11 +#define RT5677_I2S_BCLK_MS2_32 (0x0 << 11) +#define RT5677_I2S_BCLK_MS2_64 (0x1 << 11) +#define RT5677_I2S_PD2_MASK (0x7 << 8) +#define RT5677_I2S_PD2_SFT 8 +#define RT5677_I2S_PD2_1 (0x0 << 8) +#define RT5677_I2S_PD2_2 (0x1 << 8) +#define RT5677_I2S_PD2_3 (0x2 << 8) +#define RT5677_I2S_PD2_4 (0x3 << 8) +#define RT5677_I2S_PD2_6 (0x4 << 8) +#define RT5677_I2S_PD2_8 (0x5 << 8) +#define RT5677_I2S_PD2_12 (0x6 << 8) +#define RT5677_I2S_PD2_16 (0x7 << 8) +#define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7) +#define RT5677_I2S_BCLK_MS3_SFT 7 +#define RT5677_I2S_BCLK_MS3_32 (0x0 << 7) +#define RT5677_I2S_BCLK_MS3_64 (0x1 << 7) +#define RT5677_I2S_PD3_MASK (0x7 << 4) +#define RT5677_I2S_PD3_SFT 4 +#define RT5677_I2S_PD3_1 (0x0 << 4) +#define RT5677_I2S_PD3_2 (0x1 << 4) +#define RT5677_I2S_PD3_3 (0x2 << 4) +#define RT5677_I2S_PD3_4 (0x3 << 4) +#define RT5677_I2S_PD3_6 (0x4 << 4) +#define RT5677_I2S_PD3_8 (0x5 << 4) +#define RT5677_I2S_PD3_12 (0x6 << 4) +#define RT5677_I2S_PD3_16 (0x7 << 4) +#define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3) +#define RT5677_I2S_BCLK_MS4_SFT 3 +#define RT5677_I2S_BCLK_MS4_32 (0x0 << 3) +#define RT5677_I2S_BCLK_MS4_64 (0x1 << 3) +#define RT5677_I2S_PD4_MASK (0x7 << 0) +#define RT5677_I2S_PD4_SFT 0 +#define RT5677_I2S_PD4_1 (0x0 << 0) +#define RT5677_I2S_PD4_2 (0x1 << 0) +#define RT5677_I2S_PD4_3 (0x2 << 0) +#define RT5677_I2S_PD4_4 (0x3 << 0) +#define RT5677_I2S_PD4_6 (0x4 << 0) +#define RT5677_I2S_PD4_8 (0x5 << 0) +#define RT5677_I2S_PD4_12 (0x6 << 0) +#define RT5677_I2S_PD4_16 (0x7 << 0) + +/* Clock Tree Control 2 (0x74) */ +#define RT5677_I2S_PD5_MASK (0x7 << 12) +#define RT5677_I2S_PD5_SFT 12 +#define RT5677_I2S_PD5_1 (0x0 << 12) +#define RT5677_I2S_PD5_2 (0x1 << 12) +#define RT5677_I2S_PD5_3 (0x2 << 12) +#define RT5677_I2S_PD5_4 (0x3 << 12) +#define RT5677_I2S_PD5_6 (0x4 << 12) +#define RT5677_I2S_PD5_8 (0x5 << 12) +#define RT5677_I2S_PD5_12 (0x6 << 12) +#define RT5677_I2S_PD5_16 (0x7 << 12) +#define RT5677_I2S_PD6_MASK (0x7 << 8) +#define RT5677_I2S_PD6_SFT 8 +#define RT5677_I2S_PD6_1 (0x0 << 8) +#define RT5677_I2S_PD6_2 (0x1 << 8) +#define RT5677_I2S_PD6_3 (0x2 << 8) +#define RT5677_I2S_PD6_4 (0x3 << 8) +#define RT5677_I2S_PD6_6 (0x4 << 8) +#define RT5677_I2S_PD6_8 (0x5 << 8) +#define RT5677_I2S_PD6_12 (0x6 << 8) +#define RT5677_I2S_PD6_16 (0x7 << 8) +#define RT5677_I2S_PD7_MASK (0x7 << 4) +#define RT5677_I2S_PD7_SFT 4 +#define RT5677_I2S_PD7_1 (0x0 << 4) +#define RT5677_I2S_PD7_2 (0x1 << 4) +#define RT5677_I2S_PD7_3 (0x2 << 4) +#define RT5677_I2S_PD7_4 (0x3 << 4) +#define RT5677_I2S_PD7_6 (0x4 << 4) +#define RT5677_I2S_PD7_8 (0x5 << 4) +#define RT5677_I2S_PD7_12 (0x6 << 4) +#define RT5677_I2S_PD7_16 (0x7 << 4) +#define RT5677_I2S_PD8_MASK (0x7 << 0) +#define RT5677_I2S_PD8_SFT 0 +#define RT5677_I2S_PD8_1 (0x0 << 0) +#define RT5677_I2S_PD8_2 (0x1 << 0) +#define RT5677_I2S_PD8_3 (0x2 << 0) +#define RT5677_I2S_PD8_4 (0x3 << 0) +#define RT5677_I2S_PD8_6 (0x4 << 0) +#define RT5677_I2S_PD8_8 (0x5 << 0) +#define RT5677_I2S_PD8_12 (0x6 << 0) +#define RT5677_I2S_PD8_16 (0x7 << 0) + +/* Clock Tree Control 3 (0x75) */ +#define RT5677_DSP_ASRC_O_MASK (0x3 << 6) +#define RT5677_DSP_ASRC_O_SFT 6 +#define RT5677_DSP_ASRC_O_1_0 (0x0 << 6) +#define RT5677_DSP_ASRC_O_1_5 (0x1 << 6) +#define RT5677_DSP_ASRC_O_2_0 (0x2 << 6) +#define RT5677_DSP_ASRC_O_3_0 (0x3 << 6) +#define RT5677_DSP_ASRC_I_MASK (0x3 << 4) +#define RT5677_DSP_ASRC_I_SFT 4 +#define RT5677_DSP_ASRC_I_1_0 (0x0 << 4) +#define RT5677_DSP_ASRC_I_1_5 (0x1 << 4) +#define RT5677_DSP_ASRC_I_2_0 (0x2 << 4) +#define RT5677_DSP_ASRC_I_3_0 (0x3 << 4) +#define RT5677_DSP_BUS_PD_MASK (0x7 << 0) +#define RT5677_DSP_BUS_PD_SFT 0 +#define RT5677_DSP_BUS_PD_1 (0x0 << 0) +#define RT5677_DSP_BUS_PD_2 (0x1 << 0) +#define RT5677_DSP_BUS_PD_3 (0x2 << 0) +#define RT5677_DSP_BUS_PD_4 (0x3 << 0) +#define RT5677_DSP_BUS_PD_6 (0x4 << 0) +#define RT5677_DSP_BUS_PD_8 (0x5 << 0) +#define RT5677_DSP_BUS_PD_12 (0x6 << 0) +#define RT5677_DSP_BUS_PD_16 (0x7 << 0) + +#define RT5677_PLL_INP_MAX 40000000 +#define RT5677_PLL_INP_MIN 2048000 +/* PLL M/N/K Code Control 1 (0x7a 0x7c) */ +#define RT5677_PLL_N_MAX 0x1ff +#define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7) +#define RT5677_PLL_N_SFT 7 +#define RT5677_PLL_K_BP (0x1 << 5) +#define RT5677_PLL_K_BP_SFT 5 +#define RT5677_PLL_K_MAX 0x1f +#define RT5677_PLL_K_MASK (RT5677_PLL_K_MAX) +#define RT5677_PLL_K_SFT 0 + +/* PLL M/N/K Code Control 2 (0x7b 0x7d) */ +#define RT5677_PLL_M_MAX 0xf +#define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12) +#define RT5677_PLL_M_SFT 12 +#define RT5677_PLL_M_BP (0x1 << 11) +#define RT5677_PLL_M_BP_SFT 11 + +/* Global Clock Control 1 (0x80) */ +#define RT5677_SCLK_SRC_MASK (0x3 << 14) +#define RT5677_SCLK_SRC_SFT 14 +#define RT5677_SCLK_SRC_MCLK (0x0 << 14) +#define RT5677_SCLK_SRC_PLL1 (0x1 << 14) +#define RT5677_SCLK_SRC_RCCLK (0x2 << 14) /* 25MHz */ +#define RT5677_SCLK_SRC_SLIM (0x3 << 14) +#define RT5677_PLL1_SRC_MASK (0x7 << 11) +#define RT5677_PLL1_SRC_SFT 11 +#define RT5677_PLL1_SRC_MCLK (0x0 << 11) +#define RT5677_PLL1_SRC_BCLK1 (0x1 << 11) +#define RT5677_PLL1_SRC_BCLK2 (0x2 << 11) +#define RT5677_PLL1_SRC_BCLK3 (0x3 << 11) +#define RT5677_PLL1_SRC_BCLK4 (0x4 << 11) +#define RT5677_PLL1_SRC_RCCLK (0x5 << 11) +#define RT5677_PLL1_SRC_SLIM (0x6 << 11) +#define RT5677_MCLK_SRC_MASK (0x1 << 10) +#define RT5677_MCLK_SRC_SFT 10 +#define RT5677_MCLK1_SRC (0x0 << 10) +#define RT5677_MCLK2_SRC (0x1 << 10) +#define RT5677_PLL1_PD_MASK (0x1 << 8) +#define RT5677_PLL1_PD_SFT 8 +#define RT5677_PLL1_PD_1 (0x0 << 8) +#define RT5677_PLL1_PD_2 (0x1 << 8) +#define RT5671_DAC_OSR_MASK (0x3 << 6) +#define RT5671_DAC_OSR_SFT 6 +#define RT5671_DAC_OSR_128 (0x0 << 6) +#define RT5671_DAC_OSR_64 (0x1 << 6) +#define RT5671_DAC_OSR_32 (0x2 << 6) +#define RT5671_ADC_OSR_MASK (0x3 << 4) +#define RT5671_ADC_OSR_SFT 4 +#define RT5671_ADC_OSR_128 (0x0 << 4) +#define RT5671_ADC_OSR_64 (0x1 << 4) +#define RT5671_ADC_OSR_32 (0x2 << 4) + +/* Global Clock Control 2 (0x81) */ +#define RT5677_PLL2_PR_SRC_MASK (0x1 << 15) +#define RT5677_PLL2_PR_SRC_SFT 15 +#define RT5677_PLL2_PR_SRC_MCLK1 (0x0 << 15) +#define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15) +#define RT5677_PLL2_SRC_MASK (0x7 << 12) +#define RT5677_PLL2_SRC_SFT 12 +#define RT5677_PLL2_SRC_MCLK (0x0 << 12) +#define RT5677_PLL2_SRC_BCLK1 (0x1 << 12) +#define RT5677_PLL2_SRC_BCLK2 (0x2 << 12) +#define RT5677_PLL2_SRC_BCLK3 (0x3 << 12) +#define RT5677_PLL2_SRC_BCLK4 (0x4 << 12) +#define RT5677_PLL2_SRC_RCCLK (0x5 << 12) +#define RT5677_PLL2_SRC_SLIM (0x6 << 12) +#define RT5671_DSP_ASRC_O_SRC (0x3 << 10) +#define RT5671_DSP_ASRC_O_SRC_SFT 10 +#define RT5671_DSP_ASRC_O_MCLK (0x0 << 10) +#define RT5671_DSP_ASRC_O_PLL1 (0x1 << 10) +#define RT5671_DSP_ASRC_O_SLIM (0x2 << 10) +#define RT5671_DSP_ASRC_O_RCCLK (0x3 << 10) +#define RT5671_DSP_ASRC_I_SRC (0x3 << 8) +#define RT5671_DSP_ASRC_I_SRC_SFT 8 +#define RT5671_DSP_ASRC_I_MCLK (0x0 << 8) +#define RT5671_DSP_ASRC_I_PLL1 (0x1 << 8) +#define RT5671_DSP_ASRC_I_SLIM (0x2 << 8) +#define RT5671_DSP_ASRC_I_RCCLK (0x3 << 8) +#define RT5677_DSP_CLK_SRC_MASK (0x1 << 7) +#define RT5677_DSP_CLK_SRC_SFT 7 +#define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7) +#define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7) + +/* VAD Function Control 4 (0x9f) */ +#define RT5677_VAD_SRC_MASK (0x7 << 8) +#define RT5677_VAD_SRC_SFT 8 + +/* DSP InBound Control (0xa3) */ +#define RT5677_IB01_SRC_MASK (0x7 << 12) +#define RT5677_IB01_SRC_SFT 12 +#define RT5677_IB23_SRC_MASK (0x7 << 8) +#define RT5677_IB23_SRC_SFT 8 +#define RT5677_IB45_SRC_MASK (0x7 << 4) +#define RT5677_IB45_SRC_SFT 4 +#define RT5677_IB6_SRC_MASK (0x7 << 0) +#define RT5677_IB6_SRC_SFT 0 + +/* DSP InBound Control (0xa4) */ +#define RT5677_IB7_SRC_MASK (0x7 << 12) +#define RT5677_IB7_SRC_SFT 12 +#define RT5677_IB8_SRC_MASK (0x7 << 8) +#define RT5677_IB8_SRC_SFT 8 +#define RT5677_IB9_SRC_MASK (0x7 << 4) +#define RT5677_IB9_SRC_SFT 4 + +/* DSP In/OutBound Control (0xa5) */ +#define RT5677_SEL_SRC_OB23 (0x1 << 4) +#define RT5677_SEL_SRC_OB23_SFT 4 +#define RT5677_SEL_SRC_OB01 (0x1 << 3) +#define RT5677_SEL_SRC_OB01_SFT 3 +#define RT5677_SEL_SRC_IB45 (0x1 << 2) +#define RT5677_SEL_SRC_IB45_SFT 2 +#define RT5677_SEL_SRC_IB23 (0x1 << 1) +#define RT5677_SEL_SRC_IB23_SFT 1 +#define RT5677_SEL_SRC_IB01 (0x1 << 0) +#define RT5677_SEL_SRC_IB01_SFT 0 + +/* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */ +#define RT5677_DSP_IB_01_H (0x1 << 15) +#define RT5677_DSP_IB_01_H_SFT 15 +#define RT5677_DSP_IB_23_H (0x1 << 14) +#define RT5677_DSP_IB_23_H_SFT 14 +#define RT5677_DSP_IB_45_H (0x1 << 13) +#define RT5677_DSP_IB_45_H_SFT 13 +#define RT5677_DSP_IB_6_H (0x1 << 12) +#define RT5677_DSP_IB_6_H_SFT 12 +#define RT5677_DSP_IB_7_H (0x1 << 11) +#define RT5677_DSP_IB_7_H_SFT 11 +#define RT5677_DSP_IB_8_H (0x1 << 10) +#define RT5677_DSP_IB_8_H_SFT 10 +#define RT5677_DSP_IB_9_H (0x1 << 9) +#define RT5677_DSP_IB_9_H_SFT 9 +#define RT5677_DSP_IB_01_L (0x1 << 7) +#define RT5677_DSP_IB_01_L_SFT 7 +#define RT5677_DSP_IB_23_L (0x1 << 6) +#define RT5677_DSP_IB_23_L_SFT 6 +#define RT5677_DSP_IB_45_L (0x1 << 5) +#define RT5677_DSP_IB_45_L_SFT 5 +#define RT5677_DSP_IB_6_L (0x1 << 4) +#define RT5677_DSP_IB_6_L_SFT 4 +#define RT5677_DSP_IB_7_L (0x1 << 3) +#define RT5677_DSP_IB_7_L_SFT 3 +#define RT5677_DSP_IB_8_L (0x1 << 2) +#define RT5677_DSP_IB_8_L_SFT 2 +#define RT5677_DSP_IB_9_L (0x1 << 1) +#define RT5677_DSP_IB_9_L_SFT 1 + +/* Debug String Length */ +#define RT5677_REG_DISP_LEN 23 + +#define RT5677_NO_JACK BIT(0) +#define RT5677_HEADSET_DET BIT(1) +#define RT5677_HEADPHO_DET BIT(2) + +/* System Clock Source */ +enum { + RT5677_SCLK_S_MCLK, + RT5677_SCLK_S_PLL1, + RT5677_SCLK_S_RCCLK, +}; + +/* PLL1 Source */ +enum { + RT5677_PLL1_S_MCLK, + RT5677_PLL1_S_BCLK1, + RT5677_PLL1_S_BCLK2, + RT5677_PLL1_S_BCLK3, + RT5677_PLL1_S_BCLK4, +}; + +enum { + RT5677_AIF1, + RT5677_AIF2, + RT5677_AIF3, + RT5677_AIF4, + RT5677_AIF5, + RT5677_AIFS, +}; + +struct rt5677_pll_code { + bool m_bp; /* Indicates bypass m code or not. */ + bool k_bp; /* Indicates bypass k code or not. */ + int m_code; + int n_code; + int k_code; +}; + +struct rt5677_priv { + struct snd_soc_codec *codec; + struct rt5677_platform_data pdata; + struct regmap *regmap; + + int sysclk; + int sysclk_src; + int lrck[RT5677_AIFS]; + int bclk[RT5677_AIFS]; + int master[RT5677_AIFS]; + int pll_src; + int pll_in; + int pll_out; +}; + +#endif /* __RT5677_H__ */ -- 1.8.1.1.439.g50a6b54

2 2

[alsa-devel] [PATCH v2 1/2] ASoC: export dapm_kcontrol_set/get_value functions
by Vinod Koul 06 Jun '14

06 Jun '14

The DSPs like Intel ones use the DPCM to represent the DSP toplogy. So when DAPM triggers the widget, the DSP needs to know the kcontrol values and pass on to DSP firmware, so export these for driver use Signed-off-by: Vinod Koul <vinod.koul(a)intel.com> --- include/sound/soc-dapm.h | 3 +++ sound/soc/soc-dapm.c | 6 ++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h index 75020f5..abda467 100644 --- a/include/sound/soc-dapm.h +++ b/include/sound/soc-dapm.h @@ -368,6 +368,9 @@ int dapm_regulator_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); int dapm_clock_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); +bool dapm_kcontrol_set_value(const struct snd_kcontrol *kcontrol, + unsigned int value); +unsigned int dapm_kcontrol_get_value(const struct snd_kcontrol *kcontrol); /* dapm controls */ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c index 98c1dc6..d831e73 100644 --- a/sound/soc/soc-dapm.c +++ b/sound/soc/soc-dapm.c @@ -327,14 +327,15 @@ static struct list_head *dapm_kcontrol_get_path_list( list_for_each_entry(path, dapm_kcontrol_get_path_list(kcontrol), \ list_kcontrol) -static unsigned int dapm_kcontrol_get_value(const struct snd_kcontrol *kcontrol) +unsigned int dapm_kcontrol_get_value(const struct snd_kcontrol *kcontrol) { struct dapm_kcontrol_data *data = snd_kcontrol_chip(kcontrol); return data->value; } +EXPORT_SYMBOL_GPL(dapm_kcontrol_get_value); -static bool dapm_kcontrol_set_value(const struct snd_kcontrol *kcontrol, +bool dapm_kcontrol_set_value(const struct snd_kcontrol *kcontrol, unsigned int value) { struct dapm_kcontrol_data *data = snd_kcontrol_chip(kcontrol); @@ -349,6 +350,7 @@ static bool dapm_kcontrol_set_value(const struct snd_kcontrol *kcontrol, return true; } +EXPORT_SYMBOL_GPL(dapm_kcontrol_set_value); /** * snd_soc_dapm_kcontrol_codec() - Returns the codec associated to a kcontrol -- 1.7.0.4

3 12

[alsa-devel] [PATCH 00/11] ASoC: Add support for DAPM at the component level
by Lars-Peter Clausen 06 Jun '14

06 Jun '14

Hi, This series is the next step in componentization. It moves the DAPM support to the component level. This will allow any component to have DAPM widgets and routes, which was previously only possible for CODECs, and will allow any component to have DAPM widgets with controls (i.e. Mixers and MUXs), which was previously only possible for CODECs. At the end of this patchset the DAPM code will have (almost) no dependency on snd_soc_codec or snd_soc_platform and the dependency on snd_soc_component is confined to 4 small helper functions. The only reason why there is still snd_soc_codec/snd_soc_platform dependent code is because there are still a lot of drivers which use widget->codec/platform and dapm->codec/platform. So those still need to be initialized. This will be cleaned up in a separate series and once that's done the codec and platform fields will be removed from the widget and DAPM context struct. One of the major problems of moving DAPM to the component level is that the DAPM context is directly embedded in the snd_soc_codec and snd_soc_platform structs and there are many drivers directly accessing that embedded field. This means it is not possible to move the field without causing a bit of code churn in the drivers. The patch series solves this by adding two fields to the component struct. One pointer to a DAPM context, which points to the DAPM context that is used by the component. And one DAPM context, which is used as the default if no other DAPM context was provided. Neither of the fields is accessed directly, instead a inline helper function is added that returns the DAPM context for a component. This will make it possible to eventually seamlessly switch over once all direct references to CODEC and platform DAPM contexts have been eliminated. Depends on topic/component, topic/core, topic/dapm and topic/dt - Lars Lars-Peter Clausen (11): ASoC: Move name_prefix from CODEC to component ASoC: Move name and id from CODEC/platform to component ASoC: Split component registration into two steps ASoC: Auto disconnect pins from all DAPM contexts ASoC: Add helper functions to cast from DAPM context to CODEC/platform ASoC: Add a set_bias_level() callback to the DAPM context struct ASoC: Add DAPM support at the component level ASoC: Use component DAPM context for platforms ASoC: Add component level stream_event() and seq_notifier() support ASoC: Add component level set_bias_level() support ASoC: dapm: Remove DAI DAPM context include/sound/soc-dai.h | 1 - include/sound/soc-dapm.h | 6 +- include/sound/soc.h | 78 ++++++++-- include/trace/events/asoc.h | 6 +- sound/soc/codecs/tlv320dac33.c | 2 +- sound/soc/soc-cache.c | 7 +- sound/soc/soc-compress.c | 8 +- sound/soc/soc-core.c | 328 ++++++++++++++++++++++------------------- sound/soc/soc-dapm.c | 180 ++++++++++++---------- sound/soc/soc-pcm.c | 4 +- 10 files changed, 365 insertions(+), 255 deletions(-) -- 1.8.0

3 15

[alsa-devel] [PATCH v6] ASoC: add RT286 CODEC driver
by bardliao＠realtek.com 04 Jun '14

04 Jun '14

From: Bard Liao <bardliao(a)realtek.com> ALC286 is a dual mode codec, which can run as HD-A or I2S mode. It is controlled by HD-A verb commands via I2C protocol. The following is the I/O difference between ALC286 and general I2S codecs. 1. A HD-A verb command contains three parts, NID, VID, and PID. And an I2S command contains only two parts: address and data. 2. Not only the register address is written, but the read command also includes the entire write command. 3. rt286 uses different registers for read and write the same bits. As a result, regmap is difficult to be used on ALC286. We don't request a standard I/O by snd_soc_codec_set_cache_io anymore. Now we have specific write and read functions for ALC286's I/O. A verb command contains three part: NID, VID, and PID. We combine NID and VID as reg address, and PID as reg value. And do corresponding change in rt286_hw_read to get the data properly. Signed-off-by: Bard Liao <bardliao(a)realtek.com> Signed-off-by: Gustaw Lewandowski <gustaw.lewandowski(a)intel.com> --- The jack detection function is done by Lewandowski Gustaw. So I add Gustaw's Signed-off-by line in this patch The difference between this version and previous version is listed below. * Implement specific read/write functions rather than use regmap. * Use dapm widget to control power bit instead of setting it in _event * Add device ID check Verb command use two bit to set power state(D0, D1, D2, D3). But dapm widget use only one bit to set power up/down. So we use dapm widget to switch each node between D0 and D1 power state. And will set audio group to D3 when bias level = STANDBY. --- include/sound/rt286.h | 19 + sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/rt286.c | 1054 +++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/rt286.h | 186 ++++++++ 5 files changed, 1265 insertions(+) create mode 100644 include/sound/rt286.h create mode 100644 sound/soc/codecs/rt286.c create mode 100644 sound/soc/codecs/rt286.h diff --git a/include/sound/rt286.h b/include/sound/rt286.h new file mode 100644 index 0000000..eb773d1 --- /dev/null +++ b/include/sound/rt286.h @@ -0,0 +1,19 @@ +/* + * linux/sound/rt286.h -- Platform data for RT286 + * + * Copyright 2013 Realtek Microelectronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_SND_RT286_H +#define __LINUX_SND_RT286_H + +struct rt286_platform_data { + bool cbj_en; /*combo jack enable*/ + bool gpio2_en; /*GPIO2 enable*/ +}; + +#endif diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index f0e8401..5818391 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -69,6 +69,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_PCM3008 select SND_SOC_PCM512x_I2C if I2C select SND_SOC_PCM512x_SPI if SPI_MASTER + select SND_SOC_RT286 if I2C select SND_SOC_RT5631 if I2C select SND_SOC_RT5640 if I2C select SND_SOC_SGTL5000 if I2C @@ -390,6 +391,9 @@ config SND_SOC_PCM512x_SPI select SND_SOC_PCM512x select REGMAP_SPI +config SND_SOC_RT286 + tristate + config SND_SOC_RT5631 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 3c4d275..5ef8adc 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -58,6 +58,7 @@ snd-soc-pcm3008-objs := pcm3008.o snd-soc-pcm512x-objs := pcm512x.o snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o snd-soc-pcm512x-spi-objs := pcm512x-spi.o +snd-soc-rt286-objs := rt286.o snd-soc-rt5631-objs := rt5631.o snd-soc-rt5640-objs := rt5640.o snd-soc-sgtl5000-objs := sgtl5000.o @@ -209,6 +210,7 @@ obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o +obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o diff --git a/sound/soc/codecs/rt286.c b/sound/soc/codecs/rt286.c new file mode 100644 index 0000000..a88b3500 --- /dev/null +++ b/sound/soc/codecs/rt286.c @@ -0,0 +1,1054 @@ +/* + * rt286.c -- RT286 ALSA SoC audio codec driver + * + * Copyright 2013 Realtek Semiconductor Corp. + * Author: Bard Liao <bardliao(a)realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <linux/spi/spi.h> +#include <linux/acpi.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <sound/jack.h> +#include <linux/workqueue.h> +#include <sound/rt286.h> +#include <sound/hda_verbs.h> + +#include "rt286.h" + +#define RT286_VENDOR_ID 0x10ec0286 + +#define RT286_INDEX_REG_BASE 0x100 +#define RT286_INDEX_REG_RANGE 0xff +#define RT286_INDEX_REG_MAX (RT286_INDEX_REG_BASE + RT286_INDEX_REG_RANGE) + +struct rt286_priv { + struct snd_soc_codec *codec; + struct rt286_platform_data pdata; + struct i2c_client *i2c; + struct snd_soc_jack *jack; + struct delayed_work jack_detect_work; + int sys_clk; +}; + +static unsigned int rt286_hw_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); + struct i2c_client *client = rt286->i2c; + struct i2c_msg xfer[2]; + int ret; + __be32 be_reg; + unsigned int index, vid, buf = 0x0; + + /*index registers*/ + if (reg >= RT286_INDEX_REG_BASE && reg < RT286_INDEX_REG_MAX) { + ret = snd_soc_write(codec, + VERB_CMD(AC_VERB_SET_COEF_INDEX, + RT286_VENDOR_REGISTERS, 0), + reg - RT286_INDEX_REG_BASE); + + if (ret < 0) { + dev_err(codec->dev, + "Failed to set private addr: %d\n", ret); + return ret; + } + + reg = VERB_CMD(AC_VERB_GET_PROC_COEF, + RT286_VENDOR_REGISTERS, 0); + } + reg = reg | 0x80000; + vid = (reg >> 8) & 0xfff; + + if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) { + index = (reg >> 8) & 0xf; + reg = (reg & ~0xf0f) | index; + } + be_reg = cpu_to_be32(reg); + + /* Write register */ + xfer[0].addr = client->addr; + xfer[0].flags = 0; + xfer[0].len = 4; + xfer[0].buf = (u8 *)&be_reg; + + /* Read data */ + xfer[1].addr = client->addr; + xfer[1].flags = I2C_M_RD; + xfer[1].len = 4; + xfer[1].buf = (u8 *)&buf; + + ret = i2c_transfer(client->adapter, xfer, 2); + if (ret < 0) + return ret; + else if (ret != 2) + return -EIO; + + return be32_to_cpu(buf); +} + +static int rt286_hw_write(struct snd_soc_codec *codec, + unsigned int reg, unsigned int value) +{ + struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); + struct i2c_client *client = rt286->i2c; + u8 data[4]; + int ret; + + /*index registers*/ + if (reg >= RT286_INDEX_REG_BASE && reg < RT286_INDEX_REG_MAX) { + ret = snd_soc_write(codec, + VERB_CMD(AC_VERB_SET_COEF_INDEX, + RT286_VENDOR_REGISTERS, 0), + reg - RT286_INDEX_REG_BASE); + if (ret < 0) { + dev_err(codec->dev, + "Failed to set private addr: %d\n", ret); + return -EIO; + } + reg = VERB_CMD(AC_VERB_SET_PROC_COEF, + RT286_VENDOR_REGISTERS, 0); + } + + data[0] = (reg >> 24) & 0xff; + data[1] = (reg >> 16) & 0xff; + /* + * 4 bit VID: reg should be 0 + * 12 bit VID: value should be 0 + * So we use an OR operator to handle it rather than use if condition. + */ + data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff); + data[3] = value & 0xff; + + ret = i2c_master_send(client, data, 4); + if (ret == 4) + return 0; + if (ret < 0) + return ret; + else + return -EIO; +} + +static int rt286_support_power_controls[] = { + RT286_DAC_OUT1, + RT286_DAC_OUT2, + RT286_ADC_IN1, + RT286_ADC_IN2, + RT286_MIC1, + RT286_DMIC1, + RT286_DMIC2, + RT286_SPK_OUT, + RT286_HP_OUT, +}; +#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls) + +static int rt286_jack_detect(struct snd_soc_codec *codec, bool *hp, bool *mic) +{ + struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); + unsigned int val, buf; + int i; + + *hp = false; + *mic = false; + + if (rt286->pdata.cbj_en) { + buf = snd_soc_read(codec, RT286_GET_HP_SENSE); + *hp = buf & 0x80000000; + if (*hp) { + /* power on HV,VERF */ + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_POWER_CTRL1, 0x1001, 0x0); + /* power LDO1 */ + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_POWER_CTRL2, 0x4, 0x4); + snd_soc_write(codec, RT286_SET_MIC1, 0x24); + val = snd_soc_read(codec, RT286_INDEX_REG_BASE + + RT286_CBJ_CTRL2); + + msleep(200); + i = 40; + while (((val & 0x0800) == 0) && (i > 0)) { + val = snd_soc_read(codec, + RT286_INDEX_REG_BASE + + RT286_CBJ_CTRL2); + i--; + msleep(20); + } + + if (0x0400 == (val & 0x0700)) { + *mic = false; + + snd_soc_write(codec, + RT286_SET_MIC1, 0x20); + /* power off HV,VERF */ + snd_soc_update_bits(codec, + RT286_INDEX_REG_BASE + + RT286_POWER_CTRL1, 0x1001, 0x1001); + snd_soc_update_bits(codec, + RT286_INDEX_REG_BASE + + RT286_A_BIAS_CTRL3, 0xc000, 0x0000); + snd_soc_update_bits(codec, + RT286_INDEX_REG_BASE + + RT286_CBJ_CTRL1, 0x0030, 0x0000); + snd_soc_update_bits(codec, + RT286_INDEX_REG_BASE + + RT286_A_BIAS_CTRL2, 0xc000, 0x0000); + } else if ((0x0200 == (val & 0x0700)) || + (0x0100 == (val & 0x0700))) { + *mic = true; + snd_soc_update_bits(codec, + RT286_INDEX_REG_BASE + + RT286_A_BIAS_CTRL3, 0xc000, 0x8000); + snd_soc_update_bits(codec, + RT286_INDEX_REG_BASE + + RT286_CBJ_CTRL1, 0x0030, 0x0020); + snd_soc_update_bits(codec, + RT286_INDEX_REG_BASE + + RT286_A_BIAS_CTRL2, 0xc000, 0x8000); + } else { + *mic = false; + } + + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_MISC_CTRL1, + 0x0060, 0x0000); + } else { + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_MISC_CTRL1, + 0x0060, 0x0020); + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_A_BIAS_CTRL3, + 0xc000, 0x8000); + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_CBJ_CTRL1, + 0x0030, 0x0020); + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_A_BIAS_CTRL2, + 0xc000, 0x8000); + + *mic = false; + } + } else { + buf = snd_soc_read(codec, RT286_GET_HP_SENSE); + *hp = buf & 0x80000000; + buf = snd_soc_read(codec, RT286_GET_MIC1_SENSE); + *mic = buf & 0x80000000; + } + + return 0; +} + +static void rt286_jack_detect_work(struct work_struct *work) +{ + struct rt286_priv *rt286 = + container_of(work, struct rt286_priv, jack_detect_work.work); + int status = 0; + + bool hp = false; + bool mic = false; + + rt286_jack_detect(rt286->codec, &hp, &mic); + + if (hp == true) + status |= SND_JACK_HEADPHONE; + + if (mic == true) + status |= SND_JACK_MICROPHONE; + + snd_soc_jack_report(rt286->jack, status, + SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); +} + +int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) +{ + struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); + rt286->jack = jack; + + /* Send an initial empty report */ + snd_soc_jack_report(rt286->jack, 0, + SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); + + return 0; +} +EXPORT_SYMBOL_GPL(rt286_mic_detect); + +static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); +static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); + + + +static const struct snd_kcontrol_new rt286_snd_controls[] = { + SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN, + RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv), + SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN, + RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), + SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN, + 0, 0x3, 0, mic_vol_tlv), + SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN, + RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1), +}; + +/* Digital Mixer */ +static const struct snd_kcontrol_new rt286_front_mix[] = { + SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH, + RT286_MUTE_SFT, 1, 1), + SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH, + RT286_MUTE_SFT, 1, 1), +}; + +/* Analog Input Mixer */ +static const struct snd_kcontrol_new rt286_rec_mix[] = { + SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH, + RT286_MUTE_SFT, 1, 1), + SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH, + RT286_MUTE_SFT, 1, 1), + SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH, + RT286_MUTE_SFT, 1, 1), + SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH, + RT286_MUTE_SFT, 1, 1), +}; + +static const struct snd_kcontrol_new spo_enable_control = + SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK, + RT286_SET_PIN_SFT, 1, 0); + +static const struct snd_kcontrol_new hpol_enable_control = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN, + RT286_MUTE_SFT, 1, 1); + +static const struct snd_kcontrol_new hpor_enable_control = + SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN, + RT286_MUTE_SFT, 1, 1); + +/* ADC0 source */ +static const char * const rt286_adc_src[] = { + "Mic", "RECMIX", "Dmic" +}; + +static const int rt286_adc_values[] = { + 0, 4, 5, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL( + rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT, + RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); + +static const struct snd_kcontrol_new rt286_adc0_mux = + SOC_DAPM_VALUE_ENUM("ADC 0 source", rt286_adc0_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL( + rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT, + RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); + +static const struct snd_kcontrol_new rt286_adc1_mux = + SOC_DAPM_VALUE_ENUM("ADC 1 source", rt286_adc1_enum); + +static const char * const rt286_dac_src[] = { + "Front", "Surround" +}; +/* HP-OUT source */ +static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX, + 0, rt286_dac_src); + +static const struct snd_kcontrol_new rt286_hpo_mux = +SOC_DAPM_ENUM("HPO source", rt286_hpo_enum); + +/* SPK-OUT source */ +static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX, + 0, rt286_dac_src); + +static const struct snd_kcontrol_new rt286_spo_mux = +SOC_DAPM_ENUM("SPO source", rt286_spo_enum); + +static int rt286_spk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + snd_soc_write(codec, + RT286_SPK_EAPD, RT286_SET_EAPD_HIGH); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_write(codec, + RT286_SPK_EAPD, RT286_SET_EAPD_LOW); + break; + + default: + return 0; + } + + return 0; +} + +static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0); + break; + default: + return 0; + } + + return 0; +} + +static int rt286_adc_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + unsigned int nid; + + nid = (w->reg >> 20) & 0xff; + switch (event) { + case SND_SOC_DAPM_POST_PMU: + snd_soc_update_bits(codec, + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), + 0x7080, 0x7000); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_update_bits(codec, + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), + 0x7080, 0x7080); + break; + default: + return 0; + } + + return 0; +} + +static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = { + /* Input Lines */ + SND_SOC_DAPM_INPUT("DMIC1 Pin"), + SND_SOC_DAPM_INPUT("DMIC2 Pin"), + SND_SOC_DAPM_INPUT("MIC1"), + SND_SOC_DAPM_INPUT("LINE1"), + SND_SOC_DAPM_INPUT("Beep"), + + /* DMIC */ + SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1, + NULL, 0, rt286_set_dmic1_event, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1, + NULL, 0), + SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM, + 0, 0, NULL, 0), + + /* REC Mixer */ + SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0, + rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)), + + /* ADCs */ + SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0), + + /* ADC Mux */ + SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1, + &rt286_adc0_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD | + SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1, + &rt286_adc1_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD | + SND_SOC_DAPM_POST_PMU), + + /* Audio Interface */ + SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), + + /* Output Side */ + /* DACs */ + SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0), + + /* Output Mux */ + SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux), + SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux), + + SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO, + RT286_SET_PIN_SFT, 0, NULL, 0), + + /* Output Mixer */ + SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1, + rt286_front_mix, ARRAY_SIZE(rt286_front_mix)), + SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1, + NULL, 0), + + /* Output Pga */ + SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0, + &spo_enable_control, rt286_spk_event, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, + &hpol_enable_control), + SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, + &hpor_enable_control), + + /* Output Lines */ + SND_SOC_DAPM_OUTPUT("SPOL"), + SND_SOC_DAPM_OUTPUT("SPOR"), + SND_SOC_DAPM_OUTPUT("HPO Pin"), + SND_SOC_DAPM_OUTPUT("SPDIF"), +}; + +static const struct snd_soc_dapm_route rt286_dapm_routes[] = { + {"DMIC1", NULL, "DMIC1 Pin"}, + {"DMIC2", NULL, "DMIC2 Pin"}, + {"DMIC1", NULL, "DMIC Receiver"}, + {"DMIC2", NULL, "DMIC Receiver"}, + + {"RECMIX", "Beep Switch", "Beep"}, + {"RECMIX", "Line1 Switch", "LINE1"}, + {"RECMIX", "Mic1 Switch", "MIC1"}, + + {"ADC 0 Mux", "Dmic", "DMIC1"}, + {"ADC 0 Mux", "RECMIX", "RECMIX"}, + {"ADC 0 Mux", "Mic", "MIC1"}, + {"ADC 1 Mux", "Dmic", "DMIC2"}, + {"ADC 1 Mux", "RECMIX", "RECMIX"}, + {"ADC 1 Mux", "Mic", "MIC1"}, + + {"ADC 0", NULL, "ADC 0 Mux"}, + {"ADC 1", NULL, "ADC 1 Mux"}, + + {"AIF1TX", NULL, "ADC 0"}, + {"AIF2TX", NULL, "ADC 1"}, + + {"DAC 0", NULL, "AIF1RX"}, + {"DAC 1", NULL, "AIF2RX"}, + + {"Front", "DAC Switch", "DAC 0"}, + {"Front", "RECMIX Switch", "RECMIX"}, + + {"Surround", NULL, "DAC 1"}, + + {"SPK Mux", "Front", "Front"}, + {"SPK Mux", "Surround", "Surround"}, + + {"HPO Mux", "Front", "Front"}, + {"HPO Mux", "Surround", "Surround"}, + + {"SPO", "Switch", "SPK Mux"}, + {"HPO L", "Switch", "HPO Mux"}, + {"HPO R", "Switch", "HPO Mux"}, + {"HPO L", NULL, "HP Power"}, + {"HPO R", NULL, "HP Power"}, + + {"SPOL", NULL, "SPO"}, + {"SPOR", NULL, "SPO"}, + {"HPO Pin", NULL, "HPO L"}, + {"HPO Pin", NULL, "HPO R"}, +}; + +static int rt286_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); + unsigned int val = 0; + int d_len_code; + + switch (params_rate(params)) { + /* bit 14 0:48K 1:44.1K */ + case 44100: + val |= 0x4000; + break; + case 48000: + break; + default: + dev_err(codec->dev, "Unsupported sample rate %d\n", + params_rate(params)); + return -EINVAL; + } + switch (rt286->sys_clk) { + case 12288000: + case 24576000: + if (params_rate(params) != 48000) { + dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", + params_rate(params), rt286->sys_clk); + return -EINVAL; + } + break; + case 11289600: + case 22579200: + if (params_rate(params) != 44100) { + dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", + params_rate(params), rt286->sys_clk); + return -EINVAL; + } + break; + } + + if (params_channels(params) <= 16) { + /* bit 3:0 Number of Channel */ + val |= (params_channels(params) - 1); + } else { + dev_err(codec->dev, "Unsupported channels %d\n", + params_channels(params)); + return -EINVAL; + } + + d_len_code = 0; + switch (params_format(params)) { + /* bit 6:4 Bits per Sample */ + case SNDRV_PCM_FORMAT_S16_LE: + d_len_code = 0; + val |= (0x1 << 4); + break; + case SNDRV_PCM_FORMAT_S32_LE: + d_len_code = 2; + val |= (0x4 << 4); + break; + case SNDRV_PCM_FORMAT_S20_3LE: + d_len_code = 1; + val |= (0x2 << 4); + break; + case SNDRV_PCM_FORMAT_S24_LE: + d_len_code = 2; + val |= (0x3 << 4); + break; + case SNDRV_PCM_FORMAT_S8: + break; + default: + return -EINVAL; + } + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL1, 0x0018, d_len_code << 3); + dev_dbg(codec->dev, "format val = 0x%x\n", val); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val); + else + snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val); + + return 0; +} + +static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = dai->codec; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL1, 0x800, 0x800); + break; + case SND_SOC_DAIFMT_CBS_CFS: + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL1, 0x800, 0x0); + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL1, 0x300, 0x0); + break; + case SND_SOC_DAIFMT_LEFT_J: + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL1, 0x300, 0x1 << 8); + break; + case SND_SOC_DAIFMT_DSP_A: + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL1, 0x300, 0x2 << 8); + break; + case SND_SOC_DAIFMT_DSP_B: + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL1, 0x300, 0x3 << 8); + break; + default: + return -EINVAL; + } + /* bit 15 Stream Type 0:PCM 1:Non-PCM */ + snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0); + snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0); + + return 0; +} + +static int rt286_set_dai_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq); + + if (RT286_SCLK_S_MCLK == clk_id) { + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL2, 0x0100, 0x0); + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_PLL_CTRL1, 0x20, 0x20); + } else { + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL2, 0x0100, 0x0100); + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_PLL_CTRL, 0x4, 0x4); + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_PLL_CTRL1, 0x20, 0x0); + } + + switch (freq) { + case 19200000: + if (RT286_SCLK_S_MCLK == clk_id) { + dev_err(codec->dev, "Should not use MCLK\n"); + return -EINVAL; + } + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL2, 0x40, 0x40); + break; + case 24000000: + if (RT286_SCLK_S_MCLK == clk_id) { + dev_err(codec->dev, "Should not use MCLK\n"); + return -EINVAL; + } + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL2, 0x40, 0x0); + break; + case 12288000: + case 11289600: + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL2, 0x8, 0x0); + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_CLK_DIV, 0xfc1e, 0x0004); + break; + case 24576000: + case 22579200: + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL2, 0x8, 0x8); + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_CLK_DIV, 0xfc1e, 0x5406); + break; + default: + dev_err(codec->dev, "Unsupported system clock\n"); + return -EINVAL; + } + + rt286->sys_clk = freq; + + return 0; +} + +static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) +{ + struct snd_soc_codec *codec = dai->codec; + + dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio); + if (50 == ratio) + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL1, 0x1000, 0x1000); + else + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_I2S_CTRL1, 0x1000, 0x0); + + + return 0; +} + +static int rt286_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + switch (level) { + case SND_SOC_BIAS_PREPARE: + if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) + snd_soc_write(codec, + RT286_SET_AUDIO_POWER, AC_PWRST_D0); + break; + + case SND_SOC_BIAS_STANDBY: + snd_soc_write(codec, + RT286_SET_AUDIO_POWER, AC_PWRST_D3); + break; + + default: + break; + } + codec->dapm.bias_level = level; + + return 0; +} + +static irqreturn_t rt286_irq(int irq, void *data) +{ + struct rt286_priv *rt286 = data; + bool hp = false; + bool mic = false; + int status = 0; + + rt286_jack_detect(rt286->codec, &hp, &mic); + + /* Clear IRQ */ + snd_soc_update_bits(rt286->codec, RT286_INDEX_REG_BASE + + RT286_IRQ_CTRL, 0x1, 0x1); + + if (hp == true) + status |= SND_JACK_HEADPHONE; + + if (mic == true) + status |= SND_JACK_MICROPHONE; + + snd_soc_jack_report(rt286->jack, status, + SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); + + pm_wakeup_event(&rt286->i2c->dev, 300); + + return IRQ_HANDLED; +} + +static int rt286_probe(struct snd_soc_codec *codec) +{ + struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); + int i, ret; + + ret = snd_soc_read(codec, + RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID)); + if (ret != RT286_VENDOR_ID) { + dev_err(codec->dev, + "Device with ID register %x is not rt286\n", ret); + return -ENODEV; + } + + snd_soc_write(codec, RT286_SET_AUDIO_POWER, AC_PWRST_D3); + + for (i = 0; i < RT286_POWER_REG_LEN; i++) + snd_soc_write(codec, + RT286_SET_POWER(rt286_support_power_controls[i]), + AC_PWRST_D1); + + if (!rt286->pdata.cbj_en) { + snd_soc_write(codec, RT286_INDEX_REG_BASE + + RT286_CBJ_CTRL2, 0x0000); + snd_soc_write(codec, RT286_INDEX_REG_BASE + + RT286_MIC1_DET_CTRL, 0x0816); + snd_soc_write(codec, RT286_INDEX_REG_BASE + + RT286_MISC_CTRL1, 0x0000); + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_CBJ_CTRL1, 0xf000, 0xb000); + } else { + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_CBJ_CTRL1, 0xf000, 0x5000); + } + + mdelay(10); + + if (!rt286->pdata.gpio2_en) + snd_soc_write(codec, RT286_SET_DMIC2_DEFAULT, 0x4000); + else + snd_soc_write(codec, RT286_SET_DMIC2_DEFAULT, 0); + + mdelay(10); + + /*Power down LDO2*/ + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_POWER_CTRL2, 0x8, 0x0); + + codec->dapm.bias_level = SND_SOC_BIAS_OFF; + rt286->codec = codec; + + if (rt286->i2c->irq) { + snd_soc_update_bits(codec, RT286_INDEX_REG_BASE + + RT286_IRQ_CTRL, 0x2, 0x2); + + INIT_DELAYED_WORK(&rt286->jack_detect_work, + rt286_jack_detect_work); + schedule_delayed_work(&rt286->jack_detect_work, + msecs_to_jiffies(1250)); + + ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286); + if (ret != 0) { + dev_err(codec->dev, + "Failed to reguest IRQ: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int rt286_remove(struct snd_soc_codec *codec) +{ + struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); + cancel_delayed_work_sync(&rt286->jack_detect_work); + + return 0; +} + +#define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) +#define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) + +static const struct snd_soc_dai_ops rt286_aif_dai_ops = { + .hw_params = rt286_hw_params, + .set_fmt = rt286_set_dai_fmt, + .set_sysclk = rt286_set_dai_sysclk, + .set_bclk_ratio = rt286_set_bclk_ratio, +}; + +static struct snd_soc_dai_driver rt286_dai[] = { + { + .name = "rt286-aif1", + .id = RT286_AIF1, + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT286_STEREO_RATES, + .formats = RT286_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT286_STEREO_RATES, + .formats = RT286_FORMATS, + }, + .ops = &rt286_aif_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "rt286-aif2", + .id = RT286_AIF2, + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = RT286_STEREO_RATES, + .formats = RT286_FORMATS, + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = RT286_STEREO_RATES, + .formats = RT286_FORMATS, + }, + .ops = &rt286_aif_dai_ops, + .symmetric_rates = 1, + }, + +}; + +static struct snd_soc_codec_driver soc_codec_dev_rt286 = { + .probe = rt286_probe, + .remove = rt286_remove, + .set_bias_level = rt286_set_bias_level, + .idle_bias_off = true, + .write = rt286_hw_write, + .read = rt286_hw_read, + .controls = rt286_snd_controls, + .num_controls = ARRAY_SIZE(rt286_snd_controls), + .dapm_widgets = rt286_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets), + .dapm_routes = rt286_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes), +}; + +static const struct i2c_device_id rt286_i2c_id[] = { + {"rt286", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, rt286_i2c_id); + +static const struct acpi_device_id rt286_acpi_match[] = { + { "INT343A", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, rt286_acpi_match); + +static int rt286_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev); + struct rt286_priv *rt286; + int ret; + + rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286), + GFP_KERNEL); + if (NULL == rt286) + return -ENOMEM; + + rt286->i2c = i2c; + i2c_set_clientdata(i2c, rt286); + + if (pdata) + rt286->pdata = *pdata; + + ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286, + rt286_dai, ARRAY_SIZE(rt286_dai)); + + return ret; +} + +static int rt286_i2c_remove(struct i2c_client *i2c) +{ + struct rt286_priv *rt286 = i2c_get_clientdata(i2c); + + if (i2c->irq) + free_irq(i2c->irq, rt286); + snd_soc_unregister_codec(&i2c->dev); + + return 0; +} + + +struct i2c_driver rt286_i2c_driver = { + .driver = { + .name = "rt286", + .owner = THIS_MODULE, + .acpi_match_table = ACPI_PTR(rt286_acpi_match), + }, + .probe = rt286_i2c_probe, + .remove = rt286_i2c_remove, + .id_table = rt286_i2c_id, +}; + +module_i2c_driver(rt286_i2c_driver); + +MODULE_DESCRIPTION("ASoC RT286 driver"); +MODULE_AUTHOR("Bard Liao <bardliao(a)realtek.com>"); +MODULE_LICENSE("GPL"); + +/* + * ALC286 is a dual mode codec, which can run as HD-A or I2S mode. + * It is controlled by HD-A verb commands via I2C protocol. + * The following is the I/O difference between ALC286 and general I2S codecs. + * 1. A HD-A verb command contains three parts, NID, VID, and PID. + * And an I2S command contains only two parts: address and data. + * 2. Not only the register address is written, but the read command also + includes the entire write command. + * 3. rt286 uses different registers for read and write the same bits. + * As a result, regmap is difficult to be used on ALC286. + * We don't request a standard I/O by snd_soc_codec_set_cache_io anymore. + * Now we have specific write and read functions for ALC286's I/O. + * A verb command contains three part: NID, VID, and PID. + * We combine NID and VID as reg address, and PID as reg value. + * And do corresponding change in rt286_hw_read to get the data properly. + */ diff --git a/sound/soc/codecs/rt286.h b/sound/soc/codecs/rt286.h new file mode 100644 index 0000000..eaa093f --- /dev/null +++ b/sound/soc/codecs/rt286.h @@ -0,0 +1,186 @@ +/* + * rt286.h -- RT286 ALSA SoC audio driver + * + * Copyright 2011 Realtek Microelectronics + * Author: Johnny Hsu <johnnyhsu(a)realtek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __RT286_H__ +#define __RT286_H__ + +#define VERB_CMD(V, N, D) ((N << 20) | (V << 8) | D) + +#define RT286_AUDIO_FUNCTION_GROUP 0x01 +#define RT286_DAC_OUT1 0x02 +#define RT286_DAC_OUT2 0x03 +#define RT286_ADC_IN1 0x09 +#define RT286_ADC_IN2 0x08 +#define RT286_MIXER_IN 0x0b +#define RT286_MIXER_OUT1 0x0c +#define RT286_MIXER_OUT2 0x0d +#define RT286_DMIC1 0x12 +#define RT286_DMIC2 0x13 +#define RT286_SPK_OUT 0x14 +#define RT286_MIC1 0x18 +#define RT286_LINE1 0x1a +#define RT286_BEEP 0x1d +#define RT286_SPDIF 0x1e +#define RT286_VENDOR_REGISTERS 0x20 +#define RT286_HP_OUT 0x21 +#define RT286_MIXER_IN1 0x22 +#define RT286_MIXER_IN2 0x23 + +#define RT286_SET_PIN_SFT 6 +#define RT286_SET_PIN_ENABLE 0x40 +#define RT286_SET_PIN_DISABLE 0 +#define RT286_SET_EAPD_HIGH 0x2 +#define RT286_SET_EAPD_LOW 0 + +#define RT286_MUTE_SFT 7 + +/* Verb commands */ +#define RT286_GET_PARAM(NID, PARAM) VERB_CMD(AC_VERB_PARAMETERS, NID, PARAM) +#define RT286_SET_POWER(NID) VERB_CMD(AC_VERB_SET_POWER_STATE, NID, 0) +#define RT286_SET_AUDIO_POWER RT286_SET_POWER(RT286_AUDIO_FUNCTION_GROUP) +#define RT286_SET_HPO_POWER RT286_SET_POWER(RT286_HP_OUT) +#define RT286_SET_SPK_POWER RT286_SET_POWER(RT286_SPK_OUT) +#define RT286_SET_DMIC1_POWER RT286_SET_POWER(RT286_DMIC1) +#define RT286_SPK_MUX\ + VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT286_SPK_OUT, 0) +#define RT286_HPO_MUX\ + VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT286_HP_OUT, 0) +#define RT286_ADC0_MUX\ + VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT286_MIXER_IN1, 0) +#define RT286_ADC1_MUX\ + VERB_CMD(AC_VERB_SET_CONNECT_SEL, RT286_MIXER_IN2, 0) +#define RT286_SET_MIC1\ + VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT286_MIC1, 0) +#define RT286_SET_PIN_HPO\ + VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT286_HP_OUT, 0) +#define RT286_SET_PIN_SPK\ + VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT286_SPK_OUT, 0) +#define RT286_SET_PIN_DMIC1\ + VERB_CMD(AC_VERB_SET_PIN_WIDGET_CONTROL, RT286_DMIC1, 0) +#define RT286_SPK_EAPD\ + VERB_CMD(AC_VERB_SET_EAPD_BTLENABLE, RT286_SPK_OUT, 0) +#define RT286_SET_AMP_GAIN_HPO\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_HP_OUT, 0) +#define RT286_GET_HP_SENSE\ + VERB_CMD(AC_VERB_GET_PIN_SENSE, RT286_HP_OUT, 0) +#define RT286_GET_MIC1_SENSE\ + VERB_CMD(AC_VERB_GET_PIN_SENSE, RT286_MIC1, 0) +#define RT286_SET_DMIC2_DEFAULT\ + VERB_CMD(AC_VERB_SET_CONFIG_DEFAULT_BYTES_3, RT286_DMIC2, 0) +#define RT286_DACL_GAIN\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_DAC_OUT1, 0xa000) +#define RT286_DACR_GAIN\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_DAC_OUT1, 0x9000) +#define RT286_ADCL_GAIN\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_ADC_IN1, 0x6000) +#define RT286_ADCR_GAIN\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_ADC_IN1, 0x5000) +#define RT286_MIC_GAIN\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_MIC1, 0x7000) +#define RT286_SPOL_GAIN\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_SPK_OUT, 0xa000) +#define RT286_SPOR_GAIN\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_SPK_OUT, 0x9000) +#define RT286_HPOL_GAIN\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_HP_OUT, 0xa000) +#define RT286_HPOR_GAIN\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_HP_OUT, 0x9000) +#define RT286_F_DAC_SWITCH\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_MIXER_OUT1, 0x7000) +#define RT286_F_RECMIX_SWITCH\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_MIXER_OUT1, 0x7100) +#define RT286_REC_MIC_SWITCH\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_MIXER_IN, 0x7000) +#define RT286_REC_I2S_SWITCH\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_MIXER_IN, 0x7100) +#define RT286_REC_LINE_SWITCH\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_MIXER_IN, 0x7200) +#define RT286_REC_BEEP_SWITCH\ + VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, RT286_MIXER_IN, 0x7300) +#define RT286_DAC_FORMAT\ + VERB_CMD(AC_VERB_SET_STREAM_FORMAT, RT286_DAC_OUT1, 0) +#define RT286_ADC_FORMAT\ + VERB_CMD(AC_VERB_SET_STREAM_FORMAT, RT286_ADC_IN1, 0) + + +/* Index registers */ +#define RT286_A_BIAS_CTRL1 0x01 +#define RT286_A_BIAS_CTRL2 0x02 +#define RT286_POWER_CTRL1 0x03 +#define RT286_A_BIAS_CTRL3 0x04 +#define RT286_POWER_CTRL2 0x08 +#define RT286_I2S_CTRL1 0x09 +#define RT286_I2S_CTRL2 0x0a +#define RT286_CLK_DIV 0x0b +#define RT286_POWER_CTRL3 0x0f +#define RT286_MIC1_DET_CTRL 0x19 +#define RT286_MISC_CTRL1 0x20 +#define RT286_IRQ_CTRL 0x33 +#define RT286_PLL_CTRL1 0x49 +#define RT286_CBJ_CTRL1 0x4f +#define RT286_CBJ_CTRL2 0x50 +#define RT286_PLL_CTRL 0x63 + +/* SPDIF (0x06) */ +#define RT286_SPDIF_SEL_SFT 0 +#define RT286_SPDIF_SEL_PCM0 0 +#define RT286_SPDIF_SEL_PCM1 1 +#define RT286_SPDIF_SEL_SPOUT 2 +#define RT286_SPDIF_SEL_PP 3 + +/* RECMIX (0x0b) */ +#define RT286_M_REC_BEEP_SFT 0 +#define RT286_M_REC_LINE1_SFT 1 +#define RT286_M_REC_MIC1_SFT 2 +#define RT286_M_REC_I2S_SFT 3 + +/* Front (0x0c) */ +#define RT286_M_FRONT_DAC_SFT 0 +#define RT286_M_FRONT_REC_SFT 1 + +/* SPK-OUT (0x14) */ +#define RT286_M_SPK_MUX_SFT 14 +#define RT286_SPK_SEL_MASK 0x1 +#define RT286_SPK_SEL_SFT 0 +#define RT286_SPK_SEL_F 0 +#define RT286_SPK_SEL_S 1 + +/* HP-OUT (0x21) */ +#define RT286_M_HP_MUX_SFT 14 +#define RT286_HP_SEL_MASK 0x1 +#define RT286_HP_SEL_SFT 0 +#define RT286_HP_SEL_F 0 +#define RT286_HP_SEL_S 1 + +/* ADC (0x22) (0x23) */ +#define RT286_ADC_SEL_MASK 0x7 +#define RT286_ADC_SEL_SFT 0 +#define RT286_ADC_SEL_SURR 0 +#define RT286_ADC_SEL_FRONT 1 +#define RT286_ADC_SEL_DMIC 2 +#define RT286_ADC_SEL_BEEP 4 +#define RT286_ADC_SEL_LINE1 5 +#define RT286_ADC_SEL_I2S 6 +#define RT286_ADC_SEL_MIC1 7 + +#define RT286_SCLK_S_MCLK 0 +#define RT286_SCLK_S_PLL 1 + +enum { + RT286_AIF1, + RT286_AIF2, + RT286_AIFS, +}; + +int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack); + +#endif /* __RT286_H__ */ + -- 1.8.1.1.439.g50a6b54

5 19

[alsa-devel] [PATCH] ASoC: free jack GPIOs before the sound card is freed
by Stephen Warren 03 Jun '14

03 Jun '14

From: Stephen Warren <swarren(a)nvidia.com> This is the same change as commit fb6b8e71448a "ASoC: tegra: free jack GPIOs before the sound card is freed", but applied to all other ASoC machine drivers where code inspection indicates the same problem exists. That commit's description is: ========== snd_soc_jack_add_gpios() schedules a work queue item to poll the GPIO to generate an initial jack status report. If sound card initialization fails, that work item needs to be cancelled, so it doesn't run after the card has been freed. Specifically, freeing the card calls snd_jack_dev_free() which calls snd_jack_dev_disconnect() which sets jack->input_dev = NULL, and input_dev is used by snd_jack_report(), which is called from the work queue item. snd_soc_jack_free_gpios() cancels the work item. The Tegra ASoC machine drivers do call this function in the platform driver remove() callback. However, this happens after the sound card is freed, at least when the card is freed due to errors late during snd_soc_instantiate_card(). This leaves a window where the work item can execute after the card is freed. In next-20140522, sound card initialization does fail for unrelated reasons, and hits the problem described above. To solve this, fix the Tegra ASoC machine drivers to clean up the Jack GPIOs during the snd_soc_card's .remove() callback, which is executed before the overall card object is freed. also, guard the cleanup call based on whether we actually setup up the GPIOs in the first place. Ideally, we'd do the cleanup in a struct snd_soc_dai_link .fini/remove function to match where the GPIOs get set up. However, there is no such callback. ========== Note that I have not even compile-tested this in most cases, since most of the drivers rely on specific mach-* support I don't have enabled, and don't support COMPILE_TEST. Testing by the relevant board maintainers would be useful. Cc: Peter Ujfalusi <peter.ujfalusi(a)ti.com> (maintainer:OMAP AUDIO SUPPORT) Cc: Jarkko Nikula <jarkko.nikula(a)bitmer.com> (maintainer:OMAP AUDIO SUPPORT) Cc: Philipp Zabel <philipp.zabel(a)gmail.com> (maintainer:ARM/H4700 (HP IPA...) Cc: Paul Parsons <lost.distance(a)yahoo.com> (maintainer:ARM/H4700 (HP IPA...) Cc: Eric Miao <eric.y.miao(a)gmail.com> (maintainer:PXA2xx/PXA3xx SUP...) Cc: Russell King <linux(a)arm.linux.org.uk> (maintainer:PXA2xx/PXA3xx SUP...) Cc: Haojian Zhuang <haojian.zhuang(a)gmail.com> (maintainer:PXA2xx/PXA3xx SUP...) Cc: Ben Dooks <ben-linux(a)fluff.org> (maintainer:ARM/SAMSUNG ARM A...) Cc: Kukjin Kim <kgene.kim(a)samsung.com> (maintainer:ARM/SAMSUNG ARM A...) Cc: Sangbeom Kim <sbkim73(a)samsung.com> (supporter:SAMSUNG AUDIO (AS...) Cc: linux-omap(a)vger.kernel.org (open list:OMAP AUDIO SUPPORT) Cc: linux-samsung-soc(a)vger.kernel.org (moderated list:ARM/SAMSUNG ARM A...) Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- Mark, do you need this patch split up by architecture for topic branches? I assume not if you've already sent your pull requests. This applies fine on top of tag asoc-v3.16. --- sound/soc/omap/ams-delta.c | 14 ++++++++++---- sound/soc/omap/omap-twl4030.c | 28 ++++++++++++++-------------- sound/soc/omap/rx51.c | 18 +++++++++--------- sound/soc/pxa/hx4700.c | 9 ++++++++- sound/soc/samsung/h1940_uda1380.c | 11 +++++++++-- sound/soc/samsung/rx1950_uda1380.c | 12 ++++++++++-- sound/soc/samsung/smartq_wm8987.c | 11 +++++++++-- 7 files changed, 69 insertions(+), 34 deletions(-) diff --git a/sound/soc/omap/ams-delta.c b/sound/soc/omap/ams-delta.c index bb243c663e6b..1f41951d8b7f 100644 --- a/sound/soc/omap/ams-delta.c +++ b/sound/soc/omap/ams-delta.c @@ -527,6 +527,15 @@ static int ams_delta_cx20442_init(struct snd_soc_pcm_runtime *rtd) return 0; } +static int ams_delta_card_remove(struct snd_soc_pcm_runtime *rtd) +{ + snd_soc_jack_free_gpios(&ams_delta_hook_switch, + ARRAY_SIZE(ams_delta_hook_switch_gpios), + ams_delta_hook_switch_gpios); + + return 0; +} + /* DAI glue - connects codec <--> CPU */ static struct snd_soc_dai_link ams_delta_dai_link = { .name = "CX20442", @@ -543,6 +552,7 @@ static struct snd_soc_dai_link ams_delta_dai_link = { static struct snd_soc_card ams_delta_audio_card = { .name = "AMS_DELTA", .owner = THIS_MODULE, + .remove = ams_delta_card_remove, .dai_link = &ams_delta_dai_link, .num_links = 1, @@ -579,10 +589,6 @@ static int ams_delta_remove(struct platform_device *pdev) dev_warn(&pdev->dev, "failed to unregister V253 line discipline\n"); - snd_soc_jack_free_gpios(&ams_delta_hook_switch, - ARRAY_SIZE(ams_delta_hook_switch_gpios), - ams_delta_hook_switch_gpios); - snd_soc_unregister_card(card); card->dev = NULL; return 0; diff --git a/sound/soc/omap/omap-twl4030.c b/sound/soc/omap/omap-twl4030.c index 64141db311b2..b4e282871658 100644 --- a/sound/soc/omap/omap-twl4030.c +++ b/sound/soc/omap/omap-twl4030.c @@ -231,6 +231,19 @@ static int omap_twl4030_init(struct snd_soc_pcm_runtime *rtd) return ret; } +static int omap_twl4030_card_remove(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_card *card = rtd->card; + struct omap_twl4030 *priv = snd_soc_card_get_drvdata(card); + + if (priv->jack_detect > 0) + snd_soc_jack_free_gpios(&priv->hs_jack, + ARRAY_SIZE(hs_jack_gpios), + hs_jack_gpios); + + return 0; +} + /* Digital audio interface glue - connects codec <--> CPU */ static struct snd_soc_dai_link omap_twl4030_dai_links[] = { { @@ -258,6 +271,7 @@ static struct snd_soc_dai_link omap_twl4030_dai_links[] = { /* Audio machine driver */ static struct snd_soc_card omap_twl4030_card = { .owner = THIS_MODULE, + .remove = omap_twl4030_card_remove, .dai_link = omap_twl4030_dai_links, .num_links = ARRAY_SIZE(omap_twl4030_dai_links), @@ -353,19 +367,6 @@ static int omap_twl4030_probe(struct platform_device *pdev) return 0; } -static int omap_twl4030_remove(struct platform_device *pdev) -{ - struct snd_soc_card *card = platform_get_drvdata(pdev); - struct omap_twl4030 *priv = snd_soc_card_get_drvdata(card); - - if (priv->jack_detect > 0) - snd_soc_jack_free_gpios(&priv->hs_jack, - ARRAY_SIZE(hs_jack_gpios), - hs_jack_gpios); - - return 0; -} - static const struct of_device_id omap_twl4030_of_match[] = { {.compatible = "ti,omap-twl4030", }, { }, @@ -380,7 +381,6 @@ static struct platform_driver omap_twl4030_driver = { .of_match_table = omap_twl4030_of_match, }, .probe = omap_twl4030_probe, - .remove = omap_twl4030_remove, }; module_platform_driver(omap_twl4030_driver); diff --git a/sound/soc/omap/rx51.c b/sound/soc/omap/rx51.c index 6951dc812055..47a10290535b 100644 --- a/sound/soc/omap/rx51.c +++ b/sound/soc/omap/rx51.c @@ -334,6 +334,14 @@ static int rx51_aic34_init(struct snd_soc_pcm_runtime *rtd) return err; } +static int rx51_card_remove(struct snd_soc_pcm_runtime *rtd) +{ + snd_soc_jack_free_gpios(&rx51_av_jack, ARRAY_SIZE(rx51_av_jack_gpios), + rx51_av_jack_gpios); + + return 0; +} + /* Digital audio interface glue - connects codec <--> CPU */ static struct snd_soc_dai_link rx51_dai[] = { { @@ -368,6 +376,7 @@ static struct snd_soc_codec_conf rx51_codec_conf[] = { static struct snd_soc_card rx51_sound_card = { .name = "RX-51", .owner = THIS_MODULE, + .remove = rx51_card_remove, .dai_link = rx51_dai, .num_links = ARRAY_SIZE(rx51_dai), .aux_dev = rx51_aux_dev, @@ -499,14 +508,6 @@ static int rx51_soc_probe(struct platform_device *pdev) return 0; } -static int rx51_soc_remove(struct platform_device *pdev) -{ - snd_soc_jack_free_gpios(&rx51_av_jack, ARRAY_SIZE(rx51_av_jack_gpios), - rx51_av_jack_gpios); - - return 0; -} - #if defined(CONFIG_OF) static const struct of_device_id rx51_audio_of_match[] = { { .compatible = "nokia,n900-audio", }, @@ -522,7 +523,6 @@ static struct platform_driver rx51_soc_driver = { .of_match_table = of_match_ptr(rx51_audio_of_match), }, .probe = rx51_soc_probe, - .remove = rx51_soc_remove, }; module_platform_driver(rx51_soc_driver); diff --git a/sound/soc/pxa/hx4700.c b/sound/soc/pxa/hx4700.c index dcc9b04bd92c..6b81acaffddd 100644 --- a/sound/soc/pxa/hx4700.c +++ b/sound/soc/pxa/hx4700.c @@ -152,6 +152,13 @@ static int hx4700_ak4641_init(struct snd_soc_pcm_runtime *rtd) return err; } +static int hx4700_card_remove(struct snd_soc_pcm_runtime *rtd) +{ + snd_soc_jack_free_gpios(&hs_jack, 1, &hs_jack_gpio); + + return 0; +} + /* hx4700 digital audio interface glue - connects codec <--> CPU */ static struct snd_soc_dai_link hx4700_dai = { .name = "ak4641", @@ -170,6 +177,7 @@ static struct snd_soc_dai_link hx4700_dai = { static struct snd_soc_card snd_soc_card_hx4700 = { .name = "iPAQ hx4700", .owner = THIS_MODULE, + .remove = hx4700_card_remove, .dai_link = &hx4700_dai, .num_links = 1, .dapm_widgets = hx4700_dapm_widgets, @@ -206,7 +214,6 @@ static int hx4700_audio_probe(struct platform_device *pdev) static int hx4700_audio_remove(struct platform_device *pdev) { - snd_soc_jack_free_gpios(&hs_jack, 1, &hs_jack_gpio); snd_soc_unregister_card(&snd_soc_card_hx4700); gpio_set_value(GPIO92_HX4700_HP_DRIVER, 0); diff --git a/sound/soc/samsung/h1940_uda1380.c b/sound/soc/samsung/h1940_uda1380.c index 9f2fb69dbaae..720357f11a7f 100644 --- a/sound/soc/samsung/h1940_uda1380.c +++ b/sound/soc/samsung/h1940_uda1380.c @@ -189,6 +189,14 @@ static int h1940_uda1380_init(struct snd_soc_pcm_runtime *rtd) return 0; } +static int h1940_uda1380_card_remove(struct snd_soc_pcm_runtime *rtd) +{ + snd_soc_jack_free_gpios(&hp_jack, ARRAY_SIZE(hp_jack_gpios), + hp_jack_gpios); + + return 0; +} + /* s3c24xx digital audio interface glue - connects codec <--> CPU */ static struct snd_soc_dai_link h1940_uda1380_dai[] = { { @@ -206,6 +214,7 @@ static struct snd_soc_dai_link h1940_uda1380_dai[] = { static struct snd_soc_card h1940_asoc = { .name = "h1940", .owner = THIS_MODULE, + .remove = h1940_uda1380_card_remove, .dai_link = h1940_uda1380_dai, .num_links = ARRAY_SIZE(h1940_uda1380_dai), @@ -257,8 +266,6 @@ err_out: static void __exit h1940_exit(void) { platform_device_unregister(s3c24xx_snd_device); - snd_soc_jack_free_gpios(&hp_jack, ARRAY_SIZE(hp_jack_gpios), - hp_jack_gpios); gpio_free(S3C_GPIO_END + 9); } diff --git a/sound/soc/samsung/rx1950_uda1380.c b/sound/soc/samsung/rx1950_uda1380.c index 5b3e504d3a32..192aa9fc102f 100644 --- a/sound/soc/samsung/rx1950_uda1380.c +++ b/sound/soc/samsung/rx1950_uda1380.c @@ -31,6 +31,7 @@ #include "s3c24xx-i2s.h" static int rx1950_uda1380_init(struct snd_soc_pcm_runtime *rtd); +static int rx1950_uda1380_card_remove(struct snd_soc_pcm_runtime *rtd); static int rx1950_startup(struct snd_pcm_substream *substream); static int rx1950_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params); @@ -116,6 +117,7 @@ static const struct snd_soc_dapm_route audio_map[] = { static struct snd_soc_card rx1950_asoc = { .name = "rx1950", .owner = THIS_MODULE, + .remove = rx1950_uda1380_card_remove, .dai_link = rx1950_uda1380_dai, .num_links = ARRAY_SIZE(rx1950_uda1380_dai), @@ -234,6 +236,14 @@ static int rx1950_uda1380_init(struct snd_soc_pcm_runtime *rtd) return 0; } +static int rx1950_uda1380_card_remove(struct snd_soc_pcm_runtime *rtd) +{ + snd_soc_jack_free_gpios(&hp_jack, ARRAY_SIZE(hp_jack_gpios), + hp_jack_gpios); + + return 0; +} + static int __init rx1950_init(void) { int ret; @@ -278,8 +288,6 @@ err_gpio: static void __exit rx1950_exit(void) { platform_device_unregister(s3c24xx_snd_device); - snd_soc_jack_free_gpios(&hp_jack, ARRAY_SIZE(hp_jack_gpios), - hp_jack_gpios); gpio_free(S3C2410_GPA(1)); } diff --git a/sound/soc/samsung/smartq_wm8987.c b/sound/soc/samsung/smartq_wm8987.c index df55db5d3554..271a904277a1 100644 --- a/sound/soc/samsung/smartq_wm8987.c +++ b/sound/soc/samsung/smartq_wm8987.c @@ -182,6 +182,14 @@ static int smartq_wm8987_init(struct snd_soc_pcm_runtime *rtd) return err; } +static int smartq_wm8987_card_remove(struct snd_soc_pcm_runtime *rtd) +{ + snd_soc_jack_free_gpios(&smartq_jack, ARRAY_SIZE(smartq_jack_gpios), + smartq_jack_gpios); + + return 0; +} + static struct snd_soc_dai_link smartq_dai[] = { { .name = "wm8987", @@ -198,6 +206,7 @@ static struct snd_soc_dai_link smartq_dai[] = { static struct snd_soc_card snd_soc_smartq = { .name = "SmartQ", .owner = THIS_MODULE, + .remove = smartq_wm8987_card_remove, .dai_link = smartq_dai, .num_links = ARRAY_SIZE(smartq_dai), @@ -259,8 +268,6 @@ err_unregister_device: static void __exit smartq_exit(void) { gpio_free(S3C64XX_GPK(12)); - snd_soc_jack_free_gpios(&smartq_jack, ARRAY_SIZE(smartq_jack_gpios), - smartq_jack_gpios); platform_device_unregister(smartq_snd_device); } -- 1.8.1.5

2 1

[alsa-devel] [RFC] set up an sync channel between audio and display driver (i.e. ALSA and DRM)
by Lin, Mengdong 03 Jun '14

03 Jun '14

This RFC is based on previous discussion to set up a generic communication channel between display and audio driver and an internal design of Intel MCG/VPG HDMI audio driver. It's still an initial draft and your advice would be appreciated to improve the design. The basic idea is to create a new avsink module and let both drm and alsa depend on it. This new module provides a framework and APIs for synchronization between the display and audio driver. 1. Display/Audio Client The avsink core provides APIs to create, register and lookup a display/audio client. A specific display driver (eg. i915) or audio driver (eg. HD-Audio driver) can create a client, add some resources objects (shared power wells, display outputs, and audio inputs, register ops) to the client, and then register this client to avisink core. The peer driver can look up a registered client by a name or type, or both. If a client gives a valid peer client name on registration, avsink core will bind the two clients as peer for each other. And we expect a display client and an audio client to be peers for each other in a system. int avsink_new_client ( const char *name, int type, /* client type, display or audio */ struct module *module, void *context, const char *peer_name, struct avsink_client **client_ret); int avsink_free_client (struct avsink_client *client); int avsink_register_client(struct avsink_client *client); int avisink_unregister_client(int client_handle); struct avsink_client *avsink_lookup_client(const char *name, int type); struct avsink_client { const char *name; /* client name */ int type; /* client type*/ void *context; struct module *module; /* top-level module for locking */ struct avsink_client *peer; /* peer client */ /* shared power wells */ struct avsink_power_well *power_well; int num_power_wells; /* endpoints, display outputs or audio inputs */ struct avsink_endpoint * endpoint; int num_endpints; struct avsink_registers_ops *reg_ops; /* ops to access registers of a client */ void *private_data; ... }; On system boots, the avsink module is loaded before the display and audio driver module. And the display and audio driver may be loaded on parallel. * If a specific display driver (eg. i915) supports avsink, it can create a display client, add power wells and display outputs to the client, and then register the display client to the avsink core. Then it may look up if there is any audio client registered, by name or type, and may find an audio client registered by some audio driver. * If an audio driver supports avsink, it usually should look up a registered display client by name or type at first, because it may need the shared power well in GPU and check the display outputs' name to bind the audio inputs. If the display client is not registered yet, the audio driver can choose to wait (maybe in a work queue) or return -EAGAIN for a deferred probe. After the display client is found, the audio driver can register an audio client with the display client's name as the peer name, the avsink core will bind the display and audio clients to each other. Open question: If the display or audio driver is disabled by the black list, shall we introduce a time out to avoid waiting for the other client registered endlessly? 2. Shared power wells (optional) The audio and display devices, maybe only part of them, may share a common power well (e.g. for Intel Haswell and Broadwell). If so, the driver that controls the power well should define a power well object, implement the get/put ops, and add it to its avsink client before registering the client to avsink core. Then the peer client can look up this power well by its name, and get/put this power well as a user. A client can have multiple power well objects. struct avsink_power_well { const char *name; /* name of the power well */ void *context; /* parameter of get/put ops, maybe device pointer for this power well */ struct avsink_power_well_ops *ops }; struct avsink_power_well_ops { int (*get)(void *context); int (*put)(void *context); }; API: int avsink_new_power(struct avsink_client *client, const char *power_name, void * power_context, struct avsink_power_well_ops *ops, struct avsink_power_well **power_ret); struct avsink_power_well *avisnk_lookup_power(const char *name); int avsink_get_power(struct avsink_power_well *power); /* Reqesut the power */ int avsink_put_power(struct avsink_power_well *power); /* Release the power */ For example, the i915 display driver can create a device for the shared power well in Haswell GPU, implement its PM functions, and use the device pointer as the context when creating the power well object, like below struct avsink_power_well_ops i915_power_well_ops = { .get = pm_runtime_get_sync; .put = pm_runtime_put_sync; }; ... avsink_new_power ( display_client, "i915_display_power_well", pdev, /* pointer of the power well device */ &i915_power_well_ops, ...) Power domain is not used here since a single device seems enough to represent a power well. 3. Display output and audio input endpoints A display client should register the display output endpoints and its audio peer client should register the audio input endpoints. A client can have multiple endpoints. The avsink core will bind an audio input and a display output as peer to each other. This is to allow the audio and display driver to synchronize with each other for each display pipeline. All endpoints should be added to a client before the client is registered to avsink core. Dynamic endpoints are not supported now. A display out here represents a physical HDMI/DP output port. And as long as it's usable in the system (i.e. physically connected to the HDMP/DP port on the machine board), the display output should be registered not matter the port is connected to an external display device or not. And if HW and display driver can support DP1.2 daisy chain (multiple DP display devices can be connected to a single port), multiple static displays outputs should be defined for the DP port according to the HW capability. The port & display device number can be indicated by the name (e.g. "i915_DDI_B", "i915_DDI_B_DEV0", "i915_DDI_B_DEV1", or "i915_DDI_B_DEV2"), defined by the display driver. The audio driver can check the endpoints of its peer display client and use an display endpoint's name, or a presumed display endpoint name, as peer name when registering an audio endpoint, thus the avsink core will bind the two display and audio endpoints as peers. struct avsink_endpoint { const char *name; /*name of the endpoint */ int type; /* DISPLAY_OUTPUT or AUDIO_INPUT */ void *context; /* private data, used as parameter of the ops */ struct avsink_endpoint_ops *ops; struct avsink_endpoint *peer; /* peer endpoint */ }; struct avsink_endpoint_ops { int (*get_caps) (enum had_caps_list query_element, void *capabilities, void *context); int (*set_caps) (enum had_caps_list set_element, void *capabilities, void *context); int (*event_handler) (enum avsink_event_type event_type, void *context); }; API: int avsink_new_endpoint (struct avsink_client *client, const char *name, int type, /* DISPLAY_OUTPUT or AUDIO_INPUT*/ void *context, const char *peer_name, /* can be NULL if no clue */ avsink_endpoint_ops *ops, struct avsink_endpoint **endpoint_ret); int avsink_endpoint_get_caps(struct avsink_endpoint *endpoint, enum avsink_caps_list t get_element, void *capabilities); int avsink_endpoint_set_caps(struct avsink_endpoint *endpoint, enum had_caps_list set_element, void *capabilities); int avsink_endpoint_post_event(struct avsink_endpoint *endpoint, enum avsink_event_type event_type); 4. Get/Set caps on an endpoint The display or audio driver can get or set capabilities on an endpoint. Depending on the capability ID, the avsink core will call get_caps/set_caps ops of this endpoint, or call get_caps/set_caps ops of its peer endpoint and return the result to the caller. enum avsink_caps_list { /* capabilities for display output endpoints */ AVSINK_GET_DISPLAY_ELD = 1, AVSINK_GET_DISPLAY_TYPE, /* HDMI or DisplayPort */ AVSINK_GET_DISPLAY_NAME, /* Hope to use display device name under /sys/class/drm, like "card0-DP-1", for user * space to figure out which HDMI/DP output on the drm side corresponds to which audio * stream device on the alsa side */ AVSINK_GET_DISPLAY_SAMPLING_FREQ, /* HDMI TMDS clock or DP link symbol clock, for audio driver to * program N value */ AVSINK_GET_DISPLAY_HDCP_STATUS, AVSINK_GET_DISPLAY_AUDIO_STATUS, /* Whether audio is enabled */ AVSINK_SET_DISPLAY_ENABLE_AUDIO, /* Enable audio */ AVSINK_SET_DISPLAY_DISABLE_AUDIO, /* Disable audio */ AVSINK_SET_DISPLAY_ENABLE_AUDIO_INT, /* Enable audio interrupt */ AVSINK_SET_DISPLAY_DISABLE_AUDIO_INT, /* Disable audio interrupt */ /* capabilities for audio input endpoints */ AVSINK_GET_AUDIO_IS_BUSY, /* Whether there is an active audio streaming */ OTHERS_TBD, }; For example, the audio driver can query ELD info on an audio input endpoint by using caps AVSINK_GET_DISPLAY_ELD, and avsink core will call get_caps() on the peer display output endpoint and return the ELD info to the audio driver. Some audio driver may only use part of these caps. E.g. HD-Audio driver can use bus commands instead of the ops to control the audio on gfx side, so it doesn't use caps like ENABLE/DISABLE_AUDIO or ENABLE/DISABLE_AUDIO. When the display driver want to disable a display pipeline for hot-plug, mode change or power saving, it can use caps AVSINK_GET_AUDIO_IS_BUSY to check if the audio input is busy (active streaming) on this display pipeline. And if audio is busy, the display driver can choose to wait or go ahead to disable display pipeline anyway. For the latter case, the audio input endpoint will be notified by an event and should abort audio streaming. 5. Event handling of endpoints A driver can post events on an endpoint. Depending on the event type, the avsink core will call the endpoint's event handler or pass the event to its peer endpoint and trigger the peer's event handler function if defined. int avsink_endpoint_post_event(struct avsink_endpoint *endpoint, enum avsink_event_type event_type); Now we only defined event types which should be handled by the audio input endpoints. The event types can be extended in the future. enum avsink_event_type { AVSINK_EVENT_DISPLAY_DISABLE = 1, /* The display pipeline is disabled for hot-plug, mode change or * suspend. Audio driver should stop any active streaming. */ AVSINK_EVENT_DISPLAY_ENABLE, /* The display pipeline is enabled after hot-plug, mode change or * resume. Audio driver can restore previously interrupted streaming */ AVSINK_EVENT_DISPLAY_MODE_CHANGE, /* Display mode change event. At this time, the new display mode is * configured but the display pipeline is not enabled yet. Audio driver * can do some configurations such as programing N value */ AVSINK_EVENT_DISPLAY_AUDIO_BUFFER_DONE, /* Audio Buffer done interrupts. Only for audio drivers if DMA and * interrupt are handled by GPU */ AVSINK_EVENT_DISPLAY_AUDIO_BUFFER_UNDERRUN, /* Audio Buffer under run interrupts. Only for audio drivers if * DMA and interrupt are handled by GPU */ }; So for a display driver, it can post an event on a display output endpoint and get processed by the peer audio input endpoint. Or it can also directly post an event on a peer audio input endpoint, by using the 'peer' pointer on a display output endpoint. 6. Display register operation (optional) Some audio driver needs to access GPU audio registers. The register ops are provided by the peer display client. struct avsink_registers_ops { int (*read_register) (uint32_t reg_addr, uint32_t *data, void *context); int (*write_register) (uint32_t reg_addr, uint32_t data, void *context); int (*read_modify_register) (uint32_t reg_addr, uint32_t data, uint32_t mask, void *context); int avsink_define_reg_ops (struct avsink_client *client, struct avsink_registers_ops *ops); And avsink core provides API for the audio driver to access the display registers: int avsink_read_display_register(struct avsink_client *client , uint32_t offset, uint32_t *data); int avsink_write_display_register(struct avsink_client *client , uint32_t offset, uint32_t data); int avsink_read_modify_display_register(struct avsink_client *client, uint32_t offset, uint32_t data, uint32_t mask); If the client is an audio client, the avsink core will find it peer display client and call its register ops; and if the client is a display client, the avsink core will just call its own register ops. Thanks Mengdong

10 23

[alsa-devel] [PATCH 0/6] ASoC: rsnd: tidyup for DMA support for DT
by Kuninori Morimoto 03 Jun '14

03 Jun '14

Hi Mark These patches are tidyup code and fixup for DMA support of DT #1 - #4 are cleanup code patches #5 - #6 are fixup for DMA for DT Kuninori Morimoto (6): ASoC: rsnd: DT node clean up by using the of_node_put() ASoC: rsnd: save platform_device instead of device ASoC: rsnd: remove rsnd_src_non_ops ASoC: rsnd: module name is unified ASoC: rsnd: care DMA slave channel name for DT ASoC: rsnd: add rsnd_gen_dma_addr() for DMAC addr .../devicetree/bindings/sound/renesas,rsnd.txt | 1 + sound/soc/sh/rcar/core.c | 87 ++++++++++++++++-- sound/soc/sh/rcar/dvc.c | 20 ++++- sound/soc/sh/rcar/gen.c | 95 ++++++++++++++++++++ sound/soc/sh/rcar/rsnd.h | 10 ++- sound/soc/sh/rcar/src.c | 50 +++++++---- sound/soc/sh/rcar/ssi.c | 28 ++++-- 7 files changed, 260 insertions(+), 31 deletions(-)

4 9

[alsa-devel] [PATCH] ASoC: rsnd: fixup SSI interrupts style of DeviceTree
by Kuninori Morimoto 02 Jun '14

02 Jun '14

From: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> Current SSI interrupts has been set to each port. But it is too ugly style. SSI interrupts will be listed under rcar_sound,ssi node by this patch Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> --- >> Mark There is still no DT user for this driver at this point. No conflict happens on platform. .../devicetree/bindings/sound/renesas,rsnd.txt | 50 ++++++++------------ sound/soc/sh/rcar/ssi.c | 2 +- 2 files changed, 21 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index 8346cab..1fba56b 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -53,36 +53,26 @@ rcar_sound: rcar_sound@0xffd90000 { }; rcar_sound,ssi { - ssi0: ssi@0 { - interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; - }; - ssi1: ssi@1 { - interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; - }; - ssi2: ssi@2 { - interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; - }; - ssi3: ssi@3 { - interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; - }; - ssi4: ssi@4 { - interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; - }; - ssi5: ssi@5 { - interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; - }; - ssi6: ssi@6 { - interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; - }; - ssi7: ssi@7 { - interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; - }; - ssi8: ssi@8 { - interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; - }; - ssi9: ssi@9 { - interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; - }; + interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>, + <0 371 IRQ_TYPE_LEVEL_HIGH>, + <0 372 IRQ_TYPE_LEVEL_HIGH>, + <0 373 IRQ_TYPE_LEVEL_HIGH>, + <0 374 IRQ_TYPE_LEVEL_HIGH>, + <0 375 IRQ_TYPE_LEVEL_HIGH>, + <0 376 IRQ_TYPE_LEVEL_HIGH>, + <0 377 IRQ_TYPE_LEVEL_HIGH>, + <0 378 IRQ_TYPE_LEVEL_HIGH>, + <0 379 IRQ_TYPE_LEVEL_HIGH>; + ssi0: ssi@0 { }; + ssi1: ssi@1 { }; + ssi2: ssi@2 { }; + ssi3: ssi@3 { }; + ssi4: ssi@4 { }; + ssi5: ssi@5 { }; + ssi6: ssi@6 { }; + ssi7: ssi@7 { }; + ssi8: ssi@8 { }; + ssi9: ssi@9 { }; }; rcar_sound,dai { diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c index 2df723d..b311bc6 100644 --- a/sound/soc/sh/rcar/ssi.c +++ b/sound/soc/sh/rcar/ssi.c @@ -588,7 +588,7 @@ static void rsnd_of_parse_ssi(struct platform_device *pdev, /* * irq */ - ssi_info->pio_irq = irq_of_parse_and_map(np, 0); + ssi_info->pio_irq = irq_of_parse_and_map(node, i); /* * DMA -- 1.7.9.5

4 6

[alsa-devel] Realtek Alc 883 not have eapd
by asd 02 Jun '14

02 Jun '14

Below is patch wich disable eapd.

2 1

[alsa-devel] no sound with intel audio
by Petr Maivald 01 Jun '14

01 Jun '14

[1.] One line summary of the problem: no sound [2.] Full description of the problem/report: no sound [3.] Keywords (i.e., modules, networking, kernel): [4.] Kernel version (from /proc/version): Linux version 3.15.0-031500rc7-generic (apw@gomeisa) (gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu5) ) #201405251935 SMP Sun May 25 23:36:23 UTC 2014 [5.] Output of Oops.. message (if applicable) with symbolic information resolved (see Documentation/oops-tracing.txt) [6.] A small shell script or example program which triggers the problem (if possible) [7.] Environment Description: Ubuntu 14.04 LTS Release: 14.04 [7.1.] Software (add the output of the ver_linux script here) If some fields are empty or look unusual you may have an old version. Compare to the current minimal requirements in Documentation/Changes. Linux BuildOut 3.15.0-031500rc7-generic #201405251935 SMP Sun May 25 23:36:23 UTC 2014 x86_64 x86_64 x86_64 GNU/Linux Gnu C 4.8 Gnu make 3.81 binutils 2.24 util-linux 2.20.1 mount support module-init-tools 15 e2fsprogs 1.42.9 PPP 2.4.5 Linux C Library 2.19 Dynamic linker (ldd) 2.19 Procps 3.3.9 Net-tools 1.60 Kbd 1.15.5 Sh-utils 8.21 wireless-tools 30 Modules Loaded nls_iso8859_1 dm_crypt ctr ccm rfcomm bnep intel_rapl binfmt_misc arc4 x86_pkg_temp_thermal intel_powerclamp snd_hda_codec_realtek snd_hda_codec_hdmi snd_hda_codec_generic iwlmvm coretemp kvm_intel kvm mac80211 crct10dif_pclmul crc32_pclmul ghash_clmulni_intel aesni_intel aes_x86_64 uvcvideo lrw gf128mul glue_helper ablk_helper cryptd snd_hda_intel videobuf2_vmalloc snd_hda_controller videobuf2_memops microcode snd_hda_codec i915 videobuf2_core snd_hwdep snd_pcm videodev rts5139 snd_seq_midi snd_seq_midi_event btusb snd_rawmidi snd_seq bluetooth iwlwifi drm_kms_helper dell_wmi sparse_keymap 6lowpan_iphc cfg80211 drm parport_pc dell_laptop ppdev mei_me lp snd_seq_device dcdbas snd_timer i2c_algo_bit mei parport snd soundcore lpc_ich joydev wmi serio_raw video soc_button_array mac_hid psmouse ahci libahci r8169 mii [7.2.] Processor information (from /proc/cpuinfo): processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 69 model name : Intel(R) Core(TM) i7-4500U CPU @ 1.80GHz stepping : 1 microcode : 0x17 cpu MHz : 2049.000 cache size : 4096 KB physical id : 0 siblings : 4 core id : 0 cpu cores : 2 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 fma cx16 xtpr pdcm pcid sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm ida arat epb xsaveopt pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid bogomips : 4788.80 clflush size : 64 cache_alignment : 64 address sizes : 39 bits physical, 48 bits virtual power management: processor : 1 vendor_id : GenuineIntel cpu family : 6 model : 69 model name : Intel(R) Core(TM) i7-4500U CPU @ 1.80GHz stepping : 1 microcode : 0x17 cpu MHz : 1899.000 cache size : 4096 KB physical id : 0 siblings : 4 core id : 0 cpu cores : 2 apicid : 1 initial apicid : 1 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 fma cx16 xtpr pdcm pcid sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm ida arat epb xsaveopt pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid bogomips : 4788.80 clflush size : 64 cache_alignment : 64 address sizes : 39 bits physical, 48 bits virtual power management: processor : 2 vendor_id : GenuineIntel cpu family : 6 model : 69 model name : Intel(R) Core(TM) i7-4500U CPU @ 1.80GHz stepping : 1 microcode : 0x17 cpu MHz : 1786.500 cache size : 4096 KB physical id : 0 siblings : 4 core id : 1 cpu cores : 2 apicid : 2 initial apicid : 2 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 fma cx16 xtpr pdcm pcid sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm ida arat epb xsaveopt pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid bogomips : 4788.80 clflush size : 64 cache_alignment : 64 address sizes : 39 bits physical, 48 bits virtual power management: processor : 3 vendor_id : GenuineIntel cpu family : 6 model : 69 model name : Intel(R) Core(TM) i7-4500U CPU @ 1.80GHz stepping : 1 microcode : 0x17 cpu MHz : 1974.000 cache size : 4096 KB physical id : 0 siblings : 4 core id : 1 cpu cores : 2 apicid : 3 initial apicid : 3 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 fma cx16 xtpr pdcm pcid sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm ida arat epb xsaveopt pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid bogomips : 4788.80 clflush size : 64 cache_alignment : 64 address sizes : 39 bits physical, 48 bits virtual power management: [7.3.] Module information (from /proc/modules): nls_iso8859_1 12713 0 - Live 0x0000000000000000 dm_crypt 23456 0 - Live 0x0000000000000000 ctr 13193 3 - Live 0x0000000000000000 ccm 17856 3 - Live 0x0000000000000000 rfcomm 75078 8 - Live 0x0000000000000000 bnep 19884 2 - Live 0x0000000000000000 intel_rapl 19238 0 - Live 0x0000000000000000 binfmt_misc 17508 1 - Live 0x0000000000000000 arc4 12573 2 - Live 0x0000000000000000 x86_pkg_temp_thermal 14312 0 - Live 0x0000000000000000 intel_powerclamp 19099 0 - Live 0x0000000000000000 snd_hda_codec_realtek 72529 1 - Live 0x0000000000000000 snd_hda_codec_hdmi 48229 1 - Live 0x0000000000000000 snd_hda_codec_generic 70087 1 snd_hda_codec_realtek, Live 0x0000000000000000 iwlmvm 220688 0 - Live 0x0000000000000000 coretemp 13638 0 - Live 0x0000000000000000 kvm_intel 148919 0 - Live 0x0000000000000000 kvm 463808 1 kvm_intel, Live 0x0000000000000000 mac80211 663883 1 iwlmvm, Live 0x0000000000000000 crct10dif_pclmul 14268 0 - Live 0x0000000000000000 crc32_pclmul 13180 0 - Live 0x0000000000000000 ghash_clmulni_intel 13230 0 - Live 0x0000000000000000 aesni_intel 152648 6 - Live 0x0000000000000000 aes_x86_64 17131 1 aesni_intel, Live 0x0000000000000000 uvcvideo 82299 0 - Live 0x0000000000000000 lrw 13323 1 aesni_intel, Live 0x0000000000000000 gf128mul 14951 1 lrw, Live 0x0000000000000000 glue_helper 14095 1 aesni_intel, Live 0x0000000000000000 ablk_helper 13597 1 aesni_intel, Live 0x0000000000000000 cryptd 20531 3 ghash_clmulni_intel,aesni_intel,ablk_helper, Live 0x0000000000000000 snd_hda_intel 30608 1 - Live 0x0000000000000000 videobuf2_vmalloc 13216 1 uvcvideo, Live 0x0000000000000000 snd_hda_controller 35518 1 snd_hda_intel, Live 0x0000000000000000 videobuf2_memops 13362 1 videobuf2_vmalloc, Live 0x0000000000000000 microcode 24391 0 - Live 0x0000000000000000 snd_hda_codec 144671 5 snd_hda_codec_realtek,snd_hda_codec_hdmi,snd_hda_codec_generic,snd_hda_intel,snd_hda_controller, Live 0x0000000000000000 i915 873516 4 - Live 0x0000000000000000 videobuf2_core 45435 1 uvcvideo, Live 0x0000000000000000 snd_hwdep 13613 1 snd_hda_codec, Live 0x0000000000000000 snd_pcm 113863 4 snd_hda_codec_hdmi,snd_hda_intel,snd_hda_controller,snd_hda_codec, Live 0x0000000000000000 videodev 149504 2 uvcvideo,videobuf2_core, Live 0x0000000000000000 rts5139 318308 0 - Live 0x0000000000000000 (C) snd_seq_midi 13564 0 - Live 0x0000000000000000 snd_seq_midi_event 14899 1 snd_seq_midi, Live 0x0000000000000000 btusb 32555 0 - Live 0x0000000000000000 snd_rawmidi 30865 1 snd_seq_midi, Live 0x0000000000000000 snd_seq 67636 2 snd_seq_midi,snd_seq_midi_event, Live 0x0000000000000000 bluetooth 461775 22 rfcomm,bnep,btusb, Live 0x0000000000000000 iwlwifi 185872 1 iwlmvm, Live 0x0000000000000000 drm_kms_helper 59729 1 i915, Live 0x0000000000000000 dell_wmi 12681 0 - Live 0x0000000000000000 sparse_keymap 13890 1 dell_wmi, Live 0x0000000000000000 6lowpan_iphc 18968 1 bluetooth, Live 0x0000000000000000 cfg80211 515506 3 iwlmvm,mac80211,iwlwifi, Live 0x0000000000000000 drm 310655 4 i915,drm_kms_helper, Live 0x0000000000000000 parport_pc 32906 0 - Live 0x0000000000000000 dell_laptop 18315 0 - Live 0x0000000000000000 ppdev 17711 0 - Live 0x0000000000000000 mei_me 18562 0 - Live 0x0000000000000000 lp 17799 0 - Live 0x0000000000000000 snd_seq_device 14497 3 snd_seq_midi,snd_rawmidi,snd_seq, Live 0x0000000000000000 dcdbas 15017 1 dell_laptop, Live 0x0000000000000000 snd_timer 30118 2 snd_pcm,snd_seq, Live 0x0000000000000000 i2c_algo_bit 13564 1 i915, Live 0x0000000000000000 mei 87522 1 mei_me, Live 0x0000000000000000 parport 42481 3 parport_pc,ppdev,lp, Live 0x0000000000000000 snd 74195 13 snd_hda_codec_realtek,snd_hda_codec_hdmi,snd_hda_codec_generic,snd_hda_intel,snd_hda_codec,snd_hwdep,snd_pcm,snd_rawmidi,snd_seq,snd_seq_device,snd_timer, Live 0x0000000000000000 soundcore 12680 2 snd_hda_codec,snd, Live 0x0000000000000000 lpc_ich 21176 0 - Live 0x0000000000000000 joydev 17587 0 - Live 0x0000000000000000 wmi 19379 1 dell_wmi, Live 0x0000000000000000 serio_raw 13483 0 - Live 0x0000000000000000 video 19932 1 i915, Live 0x0000000000000000 soc_button_array 12769 0 - Live 0x0000000000000000 mac_hid 13275 0 - Live 0x0000000000000000 psmouse 113320 0 - Live 0x0000000000000000 ahci 30167 1 - Live 0x0000000000000000 libahci 32191 1 ahci, Live 0x0000000000000000 r8169 73316 0 - Live 0x0000000000000000 mii 13981 1 r8169, Live 0x0000000000000000 [7.4.] Loaded driver and hardware information (/proc/ioports, /proc/iomem) 0000-0cf7 : PCI Bus 0000:00 0000-001f : dma1 0020-0021 : pic1 0040-0043 : timer0 0050-0053 : timer1 0060-0060 : keyboard 0062-0062 : EC data 0064-0064 : keyboard 0066-0066 : EC cmd 0070-0077 : rtc0 0080-008f : dma page reg 00a0-00a1 : pic2 00c0-00df : dma2 00f0-00ff : fpu 03c0-03df : vesafb 0680-069f : pnp 00:03 0cf8-0cff : PCI conf1 0d00-ffff : PCI Bus 0000:00 164e-164f : pnp 00:03 1800-1803 : ACPI PM1a_EVT_BLK 1804-1805 : ACPI PM1a_CNT_BLK 1808-180b : ACPI PM_TMR 1810-1815 : ACPI CPU throttle 1830-1833 : iTCO_wdt 1850-1850 : ACPI PM2_CNT_BLK 1854-1857 : pnp 00:05 1860-187f : iTCO_wdt 1880-189f : ACPI GPE0_BLK 3000-3fff : PCI Bus 0000:01 3000-30ff : 0000:01:00.0 3000-30ff : r8169 4000-403f : 0000:00:02.0 4040-405f : 0000:00:1f.3 4060-407f : 0000:00:1f.2 4060-407f : ahci 4080-4087 : 0000:00:1f.2 4080-4087 : ahci 4088-408f : 0000:00:1f.2 4088-408f : ahci 4090-4093 : 0000:00:1f.2 4090-4093 : ahci 4094-4097 : 0000:00:1f.2 4094-4097 : ahci fd60-fd63 : pnp 00:03 ffff-ffff : pnp 00:03 ffff-ffff : pnp 00:03 ffff-ffff : pnp 00:03 00000000-00000fff : reserved 00001000-0009d3ff : System RAM 0009d400-0009ffff : reserved 000a0000-000bffff : PCI Bus 0000:00 000c0000-000cebff : Video ROM 000cf000-000cffff : Adapter ROM 000e0000-000fffff : reserved 000f0000-000fffff : System ROM 00100000-94d5ffff : System RAM 01000000-0177cd98 : Kernel code 0177cd99-01d1ef7f : Kernel data 01e7b000-01fe0fff : Kernel bss 94d60000-95d5ffff : reserved 95d60000-9aabefff : System RAM 9aabf000-9aebefff : reserved 9aebf000-9afbefff : ACPI Non-volatile Storage 9afbf000-9affefff : ACPI Tables 9afff000-9affffff : System RAM 9b000000-9f9fffff : reserved 9ba00000-9f9fffff : Graphics Stolen Memory 9fa00000-feafffff : PCI Bus 0000:00 9fa10000-9fa1ffff : pnp 00:08 9fa22000-9fa22fff : pnp 00:08 a0000000-afffffff : 0000:00:02.0 b0000000-b03fffff : 0000:00:02.0 b0400000-b04fffff : PCI Bus 0000:01 b0400000-b0403fff : 0000:01:00.0 b0400000-b0403fff : r8169 b0500000-b05fffff : PCI Bus 0000:02 b0500000-b0501fff : 0000:02:00.0 b0500000-b0501fff : iwlwifi b0600000-b06fffff : PCI Bus 0000:01 b0600000-b0600fff : 0000:01:00.0 b0600000-b0600fff : r8169 b0700000-b070ffff : 0000:00:14.0 b0700000-b070ffff : xhci_hcd b0710000-b0713fff : 0000:00:03.0 b0710000-b0713fff : ICH HD audio b0714000-b0717fff : 0000:00:1b.0 b0714000-b0717fff : ICH HD audio b0718000-b071801f : 0000:00:16.0 b0718000-b071801f : mei_me b0719000-b07190ff : 0000:00:1f.3 b071b000-b071b7ff : 0000:00:1f.2 b071b000-b071b7ff : ahci b071c000-b071c3ff : 0000:00:1d.0 b071c000-b071c3ff : ehci_hcd e0000000-efffffff : PCI MMCONFIG 0000 [bus 00-ff] e0000000-efffffff : reserved e0000000-efffffff : pnp 00:08 fe101000-fe112fff : reserved feb00000-feb0ffff : reserved fec00000-fec00fff : reserved fec00000-fec003ff : IOAPIC 0 fed00000-fee00fff : reserved fed00000-fed003ff : HPET 0 fed10000-fed17fff : pnp 00:08 fed18000-fed18fff : pnp 00:08 fed19000-fed19fff : pnp 00:08 fed1c000-fed1ffff : pnp 00:08 fed1f410-fed1f414 : iTCO_wdt fed20000-fed3ffff : pnp 00:08 fed90000-fed93fff : pnp 00:08 fee00000-fee00fff : Local APIC ff000000-ff000fff : pnp 00:08 ffc00000-ffffffff : reserved 100000000-25f5fffff : System RAM 25f600000-25fffffff : RAM buffer [7.5.] PCI information ('lspci -vvv' as root) 00:00.0 Host bridge: Intel Corporation Haswell-ULT DRAM Controller (rev 09) Subsystem: Dell Device 05ec Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information: Len=0c <?> 00:02.0 VGA compatible controller: Intel Corporation Haswell-ULT Integrated Graphics Controller (rev 09) (prog-if 00 [VGA controller]) Subsystem: Dell Device 05ec Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 63 Region 0: Memory at b0000000 (64-bit, non-prefetchable) [size=4M] Region 2: Memory at a0000000 (64-bit, prefetchable) [size=256M] Region 4: I/O ports at 4000 [size=64] Expansion ROM at <unassigned> [disabled] Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4122 Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a4] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: i915 00:03.0 Audio device: Intel Corporation Haswell-ULT HD Audio Controller (rev 09) Subsystem: Dell Device 05ec Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 65 Region 0: Memory at b0710000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [60] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4162 Capabilities: [70] Express (v1) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag- RBE- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- Kernel driver in use: snd_hda_intel 00:14.0 USB controller: Intel Corporation Lynx Point-LP USB xHCI HC (rev 04) (prog-if 30 [XHCI]) Subsystem: Dell Device 05ec Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 58 Region 0: Memory at b0700000 (64-bit, non-prefetchable) [size=64K] Capabilities: [70] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] MSI: Enable+ Count=1/8 Maskable- 64bit+ Address: 00000000fee0f00c Data: 41a1 Kernel driver in use: xhci_hcd 00:16.0 Communication controller: Intel Corporation Lynx Point-LP HECI #0 (rev 04) Subsystem: Dell Device 05ec Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 61 Region 0: Memory at b0718000 (64-bit, non-prefetchable) [size=32] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [8c] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0f00c Data: 41d1 Kernel driver in use: mei_me 00:1b.0 Audio device: Intel Corporation Lynx Point-LP HD Audio Controller (rev 04) Subsystem: Dell Device 05ec Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 64 Region 0: Memory at b0714000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [60] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0f00c Data: 4152 Capabilities: [70] Express (v1) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag- RBE- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 Status: NegoPending- InProgress- Kernel driver in use: snd_hda_intel 00:1c.0 PCI bridge: Intel Corporation Lynx Point-LP PCI Express Root Port 3 (rev e4) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00003000-00003fff Memory behind bridge: b0600000-b06fffff Prefetchable memory behind bridge: 00000000b0400000-00000000b04fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #3, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <16us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #2, PowerLimit 10.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4171 Capabilities: [90] Subsystem: Dell Device 05ec Capabilities: [a0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100 v0] #00 Capabilities: [200 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ PortCommonModeRestoreTime=40us PortTPowerOnTime=10us Kernel driver in use: pcieport 00:1c.3 PCI bridge: Intel Corporation Lynx Point-LP PCI Express Root Port 4 (rev e4) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: b0500000-b05fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #4, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <16us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #3, PowerLimit 10.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4191 Capabilities: [90] Subsystem: Dell Device 05ec Capabilities: [a0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100 v0] #00 Capabilities: [200 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ PortCommonModeRestoreTime=40us PortTPowerOnTime=10us Kernel driver in use: pcieport 00:1d.0 USB controller: Intel Corporation Lynx Point-LP USB EHCI #1 (rev 04) (prog-if 20 [EHCI]) Subsystem: Dell Device 05ec Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 0: Memory at b071c000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Capabilities: [98] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: ehci-pci 00:1f.0 ISA bridge: Intel Corporation Lynx Point-LP LPC Controller (rev 04) Subsystem: Dell Device 05ec Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information: Len=0c <?> Kernel driver in use: lpc_ich 00:1f.2 SATA controller: Intel Corporation Lynx Point-LP SATA Controller 1 [AHCI mode] (rev 04) (prog-if 01 [AHCI 1.0]) Subsystem: Dell Device 05ec Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 60 Region 0: I/O ports at 4088 [size=8] Region 1: I/O ports at 4094 [size=4] Region 2: I/O ports at 4080 [size=8] Region 3: I/O ports at 4090 [size=4] Region 4: I/O ports at 4060 [size=32] Region 5: Memory at b071b000 (32-bit, non-prefetchable) [size=2K] Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0c00c Data: 41c1 Capabilities: [70] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a8] SATA HBA v1.0 BAR4 Offset=00000004 Kernel driver in use: ahci 00:1f.3 SMBus: Intel Corporation Lynx Point-LP SMBus Controller (rev 04) Subsystem: Dell Device 05ec Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin C routed to IRQ 11 Region 0: Memory at b0719000 (64-bit, non-prefetchable) [size=256] Region 4: I/O ports at 4040 [size=32] 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8101E/RTL8102E PCI Express Fast Ethernet controller (rev 07) Subsystem: Dell Device 05ec Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 59 Region 0: I/O ports at 3000 [size=256] Region 2: Memory at b0600000 (64-bit, non-prefetchable) [size=4K] Region 4: Memory at b0400000 (64-bit, prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0800c Data: 41b1 Capabilities: [70] Express (v2) Endpoint, MSI 01 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Via message/WAKE# DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [b0] MSI-X: Enable- Count=4 Masked- Vector table: BAR=4 offset=00000000 PBA: BAR=4 offset=00000800 Capabilities: [d0] Vital Product Data No end tag found Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [160 v1] Device Serial Number 01-00-00-00-36-4c-e0-00 Capabilities: [170 v1] Latency Tolerance Reporting Max snoop latency: 0ns Max no snoop latency: 0ns Kernel driver in use: r8169 02:00.0 Network controller: Intel Corporation Wireless 7260 (rev 73) Subsystem: Intel Corporation Wireless-N 7260 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 62 Region 0: Memory at b0500000 (64-bit, non-prefetchable) [size=8K] Capabilities: [c8] Power Management version 3 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0400c Data: 41e1 Capabilities: [40] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 unlimited ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr+ NoSnoop+ FLReset- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 <32us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR+, OBFF Via WAKE# DevCtl2: Completion Timeout: 16ms to 55ms, TimeoutDis-, LTR+, OBFF Disabled LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [140 v1] Device Serial Number fc-f8-ae-ff-ff-a8-4f-9e Capabilities: [14c v1] Latency Tolerance Reporting Max snoop latency: 0ns Max no snoop latency: 0ns Capabilities: [154 v1] Vendor Specific Information: ID=cafe Rev=1 Len=014 <?> Kernel driver in use: iwlwifi [7.6.] SCSI information (from /proc/scsi/scsi) Attached devices: Host: scsi0 Channel: 00 Id: 00 Lun: 00 Vendor: ATA Model: WDC WD10JPVX-75J Rev: 01.0 Type: Direct-Access ANSI SCSI revision: 05 Host: scsi1 Channel: 00 Id: 00 Lun: 00 Vendor: HL-DT-ST Model: DVD+-RW GU90N Rev: A100 Type: CD-ROM ANSI SCSI revision: 05 Host: scsi3 Channel: 00 Id: 00 Lun: 00 Vendor: Generic- Model: xD/SD/M.S. Rev: 1.00 Type: Direct-Access ANSI SCSI revision: 02 [7.7.] Other information that might be relevant to the problem (please look in /proc and include all information that you think to be relevant): 1 1136 14 149 1523 1631 22 2596 3 39 480 52 63 78 9 cpuinfo ioports meminfo slabinfo vmallocinfo 10 1144 1444 1494 1528 1640 23 26 301 40 489 53 642 787 907 crypto irq misc softirqs vmstat 100 1193 1450 1497 153 17 2323 2675 31 41 49 54 7 79 919 devices kallsyms modules stat zoneinfo 101 12 1460 15 1538 175 2357 2681 32 42 490 55 707 791 936 diskstats kcore mounts swaps 102 1209 1461 150 1541 176 2358 2682 33 43 5 56 741 8 979 dma key-users mtrr sys 103 1223 1463 1505 1562 18 2365 2683 339 436 50 564 743 81 acpi driver kmsg net sysrq-trigger 1091 13 1464 1508 1591 19 24 27 34 44 504 57 75 819 asound execdomains kpagecount pagetypeinfo sysvipc 11 1300 147 151 1597 1908 2400 28 35 45 505 572 755 848 buddyinfo fb kpageflags partitions timer_list 1109 1338 1470 1511 16 1980 2403 29 36 46 506 576 76 852 bus filesystems latency_stats sched_debug timer_stats 1113 1340 1474 1515 1601 2 2486 293 37 47 507 59 765 857 cgroups fs loadavg schedstat tty 1127 1380 1478 152 1607 20 25 2954 371 478 51 61 766 858 cmdline interrupts locks scsi uptime 1132 1395 148 1520 1625 21 2575 2973 38 48 511 62 77 861 consoles iomem mdstat self version [X.] Other notes, patches, fixes, workarounds: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1324330

2 10

Jump to page:

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

Alsa-devel May 2014