August 2009 - Alsa-devel - mailman.alsa-project.org

[alsa-devel] [ASoc] TDM over one SSC channel on AT91 possible?
by Friedrich Lobenstock 24 Jun '11

24 Jun '11

Hello! The background: I'm just designing an ATMEL AT91RM9200 based board which got two TLV320AIC33 on board. It is either possible to hook up the two TLV320AIC33 to a separate SSC (synchronous serial control) channel each or use one SSC channel and configure it for TDM (time division multiplex) mode. There is already a driver for TLV320AIC14k/TLV320AIC2k in the development tree, so adding support for the TLV320AIC33 should be feasible. What I'm not sure about is the fact if ASOC is prepared for using channels, especially SSC, in TDM mode. Is the core ASOC structure prepared to handle that? Would we be better off instantiate one drive twice each time with different parameters for the SSC channel? Thanks for any feedback. -- MfG / Regards Friedrich Lobenstock _________________________________________________________ SCOTTY Group Austria GmbH a SCOTTY Group plc company, http://www.scottygroup.com/ _________________________________________________________

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[alsa-devel] idt STAC927x adat supported (sigmatel HDA codec) ?
by Eric 03 Mar '11

03 Mar '11

Is the ADAT output of the IDT (sigmatel) STAC927x HDA codec supported in alsa ? If not could someone please try to add this incredibly nice feature in the existing alsa driver ? Thank you very much

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[alsa-devel] davinci-i2c,pcm updates
by Troy Kisky 27 Sep '10

27 Sep '10

This patch set is against git://git.alsa-project.org/alsa-kernel.git but the last patch in series won't compile until the sram allocator patch is available.

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Re: [alsa-devel] Patchmix-style application for EMU cards
by Camilo Polymeris 30 Aug '10

30 Aug '10

Hello > That is more or less what I had figured out, but it how are playback_1 to > > _16 channels routed to DSP0-15? It seems that it depends on the setting > of > > Front, Surround, LFE, etc. mixer controls. If they are turned up, I > don't > > understand what happens, sound to playback channels appears on various > DSP > > buses, at different levels. > > Really? Well, I didn't much experiment with surround mode. In source code, > I > can see that there are up to playback 8 channels at hw:0,0 with can be > controlled by faders in alsamixer. I tried surround40 and surroun51 on my > emu1616m and it worked as expected. The channles were mapped to first > couple > of DSP ports in a correct order. In fact this should work the same as > audigy > does, except the result is passed to DSP ports instead of physical > outputs. > On my card, playback channels 1 & 2 (hw:0,3) appear on all DSP busses associated with surround. Say you turn up the "Side" fader in alsamixer, channels 1 & 2 will appear at the relevant DSPs (6-7, I think) Whatever, for now I am just keeping all surround controls down (that is, Front, Surround, Center, Side & LFE). > Anyway, I think if there is another layer of routing done in audigy DSP, > it > shouldn't be used in EMU specific application. Or at least not for now. > The > most important thing is to provide all the switches and FPGA routing > scheme > for each EMU model. Or, to be precise, three routing schemes for each EMU > model, because for "double speed" (e.g. 96kHz) and "quadro speed" (e.g. > 192kHz) modes of operation the numebr of both physical and virtual > channels > changes. > I think the switches and enums for the card models are rather trivial, one can handle it with a customized version of qamix (done with a simple XML file), for example. A separate application would not be necessary for only that. > > If I turn the Front/Surround/LFE/etc. faders down, I can mix playback > > channels to DSP using the "Multichannel PCM Send/Routing/Volume" faders, > in > > a more or less intuitive way, besides that routing values do not map > > directly to DSP buses (i.e. 14-15 map to DSP0-1, but 2-3 map to DSP2-3). > Handling of this controls motivated me to write the application in the first place. No sound at all will appear if I don't set the appropiate controls for each playback channel: Multichannel PCM Volume (full), Multichannel PCM Send (an index of 8 controls, the first 4 select the target DSP) & Multichannel PCM Send Volume (again faders 0-3 of 8) By the way, only DSP0-7 work in this way. I have no idea how to make DSP8-31 work. On which card you did tested it? The driver was primary written for the > 1820M/1212M V1, so some things may not work well on other models and need > to > be fixed. I have a 1212m, don't know which version, but I think it's V1-- it does have firewire. I am using driver version 1.0.16. Thanks, Camilo.

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[alsa-devel] [PATCH] ARM: DaVinci: Audio support for DA850/OMAP-L138 EVM
by Chaithrika U S 20 Jan '10

20 Jan '10

Define resources for McASP used on DA850/OMAP-L138 EVM, add platform device defintion and Pin Mux configurations. Signed-off-by: Chaithrika U S <chaithrika(a)ti.com> --- Applies on DaVinci GIT tree. This patch is dependent on the following patch which I have submitted earlier: [PATCH v2] ARM: DaVinci: Audio support for DA830 EVM arch/arm/mach-davinci/board-da850-evm.c | 29 ++++++++++++++++++++++ arch/arm/mach-davinci/da850.c | 39 ++++++++++++++++++++++++++++++ arch/arm/mach-davinci/devices-da8xx.c | 34 +++++++++++++++++++++++++- arch/arm/mach-davinci/include/mach/asp.h | 7 +++++ arch/arm/mach-davinci/include/mach/mux.h | 25 +++++++++++++++++++ 5 files changed, 133 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index d989346..52bfe4c 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -38,6 +38,28 @@ static struct davinci_uart_config da850_evm_uart_config __initdata = { .enabled_uarts = 0x7, }; +/* davinci da850 evm audio machine driver */ +static u8 da850_iis_serializer_direction[] = { + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, + INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE, + RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, +}; + +static struct snd_platform_data da850_evm_snd_data = { + .tx_dma_offset = 0x2000, + .rx_dma_offset = 0x2000, + .op_mode = DAVINCI_MCASP_IIS_MODE, + .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), + .tdm_slots = 2, + .serial_dir = da850_iis_serializer_direction, + .eventq_no = EVENTQ_1, + .version = MCASP_VERSION_2, + .txnumevt = 1, + .rxnumevt = 1, +}; + + static __init void da850_evm_init(void) { struct davinci_soc_info *soc_info = &davinci_soc_info; @@ -86,6 +108,13 @@ static __init void da850_evm_init(void) */ __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); + + ret = da8xx_pinmux_setup(da850_mcasp_pins); + if (ret) + pr_warning("da850_evm_init: mcasp mux setup failed: %d\n", + ret); + + da8xx_init_mcasp(0, &da850_evm_snd_data); } #ifdef CONFIG_SERIAL_8250_CONSOLE diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 4a43ae2..e33b226 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -289,6 +289,13 @@ static struct clk emac_clk = { .lpsc = DA8XX_LPSC1_CPGMAC, }; +static struct clk mcasp_clk = { + .name = "mcasp", + .parent = &pll0_sysclk2, + .lpsc = DA8XX_LPSC1_McASP0, + .psc_ctlr = 1, +}; + static struct davinci_clk da850_clks[] = { CLK(NULL, "ref", &ref_clk), CLK(NULL, "pll0", &pll0_clk), @@ -326,6 +333,7 @@ static struct davinci_clk da850_clks[] = { CLK(NULL, "arm", &arm_clk), CLK(NULL, "rmii", &rmii_clk), CLK("davinci_emac.1", NULL, &emac_clk), + CLK("davinci-mcasp.0", NULL, &mcasp_clk), CLK(NULL, NULL, NULL), }; @@ -370,6 +378,30 @@ static const struct mux_config da850_pins[] = { MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) + /* McASP function */ + MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) + MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) + MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false) + MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false) + MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false) + MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false) + MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false) + MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false) + MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false) + MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false) + MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false) + MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false) + MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false) + MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false) + MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false) + MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false) + MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false) + MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false) + MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false) + MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false) + MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false) + MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false) + MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false) #endif }; @@ -406,6 +438,13 @@ const short da850_cpgmac_pins[] __initdata = { -1 }; +const short da850_mcasp_pins[] __initdata = { + DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, + DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE, + DA850_AXR_11, DA850_AXR_12, + -1 +}; + /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { [IRQ_DA8XX_COMMTX] = 7, diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index fe0baaf..1882eef 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -309,6 +309,34 @@ static struct platform_device da830_mcasp1_device = { .resource = da830_mcasp1_resources, }; +static struct resource da850_mcasp_resources[] = { + { + .name = "mcasp", + .start = DAVINCI_DA8XX_MCASP0_REG_BASE, + .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1, + .flags = IORESOURCE_MEM, + }, + /* TX event */ + { + .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, + .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT, + .flags = IORESOURCE_DMA, + }, + /* RX event */ + { + .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT, + .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device da850_mcasp_device = { + .name = "davinci-mcasp", + .id = 0, + .num_resources = ARRAY_SIZE(da850_mcasp_resources), + .resource = da850_mcasp_resources, +}; + int __init da8xx_register_emac(void) { return platform_device_register(&da8xx_emac_device); @@ -316,8 +344,12 @@ int __init da8xx_register_emac(void) void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata) { - if (id == 1) { /* DA830/OMAP-L137 has 3 instances of McASP */ + /* DA830/OMAP-L137 has 3 instances of McASP */ + if (cpu_is_davinci_da830() && id == 1) { da830_mcasp1_device.dev.platform_data = pdata; platform_device_register(&da830_mcasp1_device); + } else if (cpu_is_davinci_da850()) { + da850_mcasp_device.dev.platform_data = pdata; + platform_device_register(&da850_mcasp_device); } } diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h index f3c97ac..18e4ce3 100644 --- a/arch/arm/mach-davinci/include/mach/asp.h +++ b/arch/arm/mach-davinci/include/mach/asp.h @@ -15,6 +15,9 @@ #define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 #define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 +/* Bases of da850/da830 McASP0 register banks */ +#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 + /* Bases of da830 McASP1 register banks */ #define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 @@ -29,6 +32,10 @@ #define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 #define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 +/* EDMA channels of da850/da830 McASP0 */ +#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 +#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 + /* EDMA channels of da830 McASP1 */ #define DAVINCI_DA830_DMA_MCASP1_AREVT 2 #define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index a676b2f..f50f5b2 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -748,6 +748,31 @@ enum davinci_da850_index { DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, + + /* McASP function */ + DA850_ACLKR, + DA850_ACLKX, + DA850_AFSR, + DA850_AFSX, + DA850_AHCLKR, + DA850_AHCLKX, + DA850_AMUTE, + DA850_AXR_15, + DA850_AXR_14, + DA850_AXR_13, + DA850_AXR_12, + DA850_AXR_11, + DA850_AXR_10, + DA850_AXR_9, + DA850_AXR_8, + DA850_AXR_7, + DA850_AXR_6, + DA850_AXR_5, + DA850_AXR_4, + DA850_AXR_3, + DA850_AXR_2, + DA850_AXR_1, + DA850_AXR_0, }; #ifdef CONFIG_DAVINCI_MUX -- 1.5.6

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[alsa-devel] Audio buffer mmap-ing on sh arch vs. cache aliasing problem
by Pawel MOLL 16 Jan '10

16 Jan '10

Hi Guys, Recently I was investigating an issue with capturing audio using USB Audio Class device on a sh4-based board. "Bad voice quality" was reported... Finally I have traced the problem to something which is (unfortunately) well known to sh developers as a D-cache aliasing (or synonym) problem. Briefly speaking: due to some MMU design decisions, one can have two different virtual address pointing to the same physical location, which is fine, but going via different cache slots! So if there was a value of "0" in the memory and user "A" will write "1" there, user "B" will still read "0"... The solution is to ensure all TLB entries (so virtual memory areas) are beginning from a 16kB-aligned virtual address. Otherwise it is necessary to flush the cache between accesses from "A" and "B" sides. And now. The USB Audio Class driver (sound/usb/usbaudio.c) is allocating the sound buffer like this... static int snd_pcm_alloc_vmalloc_buffer(struct snd_pcm_substream *subs, size_t size) { [...] runtime->dma_area = vmalloc(size); [...] } ... and vmalloc will return a page(4k)-aligned pointer, possibly not 16k-aligned one. This is the source of all evil ;-) When using RW transfers everything is fine, as data is memcopied between two independent buffers. In a case of MMAP mode we will end up with such a situation: 1. The driver will memcpy data from an URB to the buffer. It will populate several cache lines. Let's call it a "kernel cache". 2. As the library has mapped the non-16k-aligned address via different cache line ("user cache"), it will read some rubbish from the physical memory, populating the "user cache" by the way. 3. Some time later the "kernel cache" is flushed, writing the data to the memory. 4. Some new data from URB is entering "kernel cache". 5. The library will access mmap-ed area again, going via the "user cache", which may or may not reflect the correct data (depending on the fact was the "user cache" flushed or not) etc. Of course this cycle is completely not deterministic, so some of the "kernel cache" lines will be flushed before being accessed from user space, other not... The final effect is... hmm... bizarre :-) First, of course, you will get a (probably loud) glitch (rubbish from buffer's underlying memory, before the first valid data is written back), and then something that could be described as an "echo" ;-) I mean - you are capturing "1 2 3 4 5 6 7..." and the result is (G stands for Glitch ;-) "G 1 23 3 4 4 6 67..." As a quick-and-dirty work-around I have modified snd_pcm_alloc_vmalloc_buffer() to allocate always 12kB more and then use 16k-aligned pointer: static int snd_pcm_alloc_vmalloc_buffer(struct snd_pcm_substream *subs, size_t size) { struct snd_pcm_runtime *runtime = subs->runtime; if (runtime->dma_addr) { if (runtime->dma_bytes >= size) return 0; /* already large enough */ vfree((void *)runtime->dma_addr); } runtime->dma_addr = (unsigned long)vmalloc(size + 12 * 1024); if (!runtime->dma_addr) return -ENOMEM; runtime->dma_area = (void *)ALIGN(runtime->dma_addr, 16 * 1024); runtime->dma_bytes = size; return 0; } Of course it cannot be regarded as anything more as a hack. And definitely not as a solution... So my question is: Any idea how the "proper solution" should look like? I see no obvious method to get an arch-independent "mmap-compliant" buffer. This problem was found on a sh arch, using an USB Audio Class device, however out there some other architectures are suffering from this MMU "feature" as well (ie. see http://docs.hp.com/en/B3906-90006/ch07s09.html) and possibly other drivers could behave "wrongly" (quoted as the driver is actually innocent...) To be honest I just have absolutely no idea what to do with this all! :-O I hope I was clear enough in the description... Any feedback, advise, idea etc. will be more than appreciated. Cheers Paweł

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[alsa-devel] Intel G45 8-Channel LPCM over HDMI
by Alexander Werner 11 Dec '09

11 Dec '09

Hi, I'm planning to build a linux-based, small sized PC for hearing aid acousticians. It would be highly unfavorable, if the connection between Receiver and PC was analog, because of the lower quality and the high number of cables. I searched for a appropriate mainboard, and found the DG45FC, which fits my needs perfectly, apart from the missing audio over HDMI support. Is there any plan to support multichannel LPCM output over HDMI on the Intel G45 platform? If not, is there anyone willing to implement HDMI support for the G45 chipset if I donate the needed hardware (permanently)? But if there's no chance to implement it in the near future, has anyone experience with an onboard chipset with multichannel LPCM over HDMI and ALSA support? Thanks, Alexander Werner

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[alsa-devel] ALSA on Alienware M17x
by Adam Gray 06 Dec '09

06 Dec '09

Hi guys, I'm having a lot of trouble getting sound out of my Alienware M17x. I've attached the output from alsa-info. I'm running kernel version 2.6.28 with ALSA driver version 1.0.18. There's no sound at all from the speakers or the headphones. In alsamixer, all channels appear un-muted and turned up full. If you need any further information please let me know. Regards, Adam Gray

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Re: [alsa-devel] Testers wanted: New SB X-Fi driver
by Christian Esken 18 Nov '09

18 Nov '09

Am Sonntag 12 Juli 2009 10:24:35 schrieb Christian Esken: > Am Montag 06 Juli 2009 08:26:11 schrieb Takashi Iwai: > > At Sun, 5 Jul 2009 13:29:48 +0200, > > > > Christian Esken wrote: > > > Am Sonntag 05 Juli 2009 09:44:33 schrieb Takashi Iwai: > > > > At Sun, 5 Jul 2009 00:19:55 +0200, > > > > > > > > Christian Esken wrote: > > > > > Am Samstag 27 Juni 2009 14:05:45 schrieb Christian Esken: > > > > > > Hello, > > > > > > > > > > > > unfortunately I cannot playback anything (PCM) with the new SB > > > > > > X-Fi driver. Driver: > > > > > > ftp://ftp.kernel.org/pub/linux/kernel/people/tiwai/snapshot/alsa- > > > > > > driver-snapshot.tar.bz2 > > > > > > Distribution: openSuSE 11.1 > > > > > > Kernel: 2.6.27.23-0.1-xen > > > > > > > > > > > > My card is a "X-Fi Titanium" (PCI device code: 1102:000b). The > > > > > > card is recognized by the driver, and any mixer (alsamixer, kmix) > > > > > > also recognizes the card. > > > > > > > > > > > > But playing back isn't possible. I tried speaker-test, audacity, > > > > > > amarok and aplay. Most applications hang, some also produce an > > > > > > error in the /var/log/messages (see > > > > > > below). > > > > > > > > > > > > I then used "./configure --with-debug=full --with-cards=ctxfi" > > > > > > due to the possible hd-audio conflict, but it didn't make a > > > > > > difference. > > > > > > > > > > > > Is there anything else I could try? > > > > > > > > > > I tested the same openSuSE version with a non-Xen 64 bit kernel, > > > > > and it doesn't work either. > > > > > > > > > > And I tried with this: > > > > > Driver: alsa-driver-20090704.tar.bz2 > > > > > Distribution: Kubuntu Karmic Alpha-2 > > > > > Kernel: 2.6.30 (32 Bit) > > > > > > > > > > Under the latter setup the X-Fi Titanium works (Simple 2 channel > > > > > test with speaker-test, audacity, amarok). :-)) > > > > > > > > How many RAM do you have? > > > > Could you boot with the limited memory size? > > > > > > It is just 2GB. So I am not limited by the 32 bit barrier. > > > > > > So booting with "limited" memory size doesn't make sense, right? > > > > Supposedly. Is it emu20k1 or emu20k2? > > I checked it again: It is a 20k2 chip. > > /var/log/boot.msg says: > <7>ALSA /home/chris/Desktop/alsa-driver/pci/ctxfi/ctatc.c:1268: ctxfi: chip > 20K2 model SB0880 (1102:0041) is found > > > http://pci-ids.ucw.cz/mods/PC/1102/000b shows 1102:0041 as "X-Fi Titanium > series [EMU20k2]". I did now test it with a different 64 Bit Linux distribution, and it works correctly: Driver: alsa-driver-20090712.tar.bz2 Distribution: Kubuntu Karmic Alpha-2 Kernel: 2.6.30 (64 Bit) All in all, I can produce a working environment with recent 32 and 64 bit kernels. This is good news. :-) Below is the summary on the tested distributions. Christian So we got this: Kubuntu Karmic Alpha-2 32 Bit, 2.0.30 (works) Kubuntu Karmic Alpha-2 64 Bit, 2.0.30 (works) SuSE 11.1 64 Bit, 2.0.27 (does not work) SuSE 11.1 64 Bit, 2.0.27 XEN (does not work) SuSE 11.2 Milestone3 64Bit, 2.0.30 (test canceled, due to unrelated problems) => I'll see whether I can redo the SuSE11.2 tests, after doing a bugreport at openSuSE.

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[alsa-devel] [RFC][PATCH] ARM: OMAP: McBSP: Use register cache
by Janusz Krzysztofik 14 Nov '09

14 Nov '09

Change the way McBSP registers are updated: use cached values instead of relying upon those read back from the device. With this patch, I have finally managed to get rid of all random playback/recording hangups on my OMAP1510 based Amstrad Delta (buggy?) hardware. Before that, I could suspect that values read back from McBSP registers before updating them happened to be errornous. I think there is one important point that makes this patch worth of applying, apart from my hardware quality. With the current code, if it ever happens to any machine, no matter if OMAP1510 or newer, to read incorrect value from a McBSP register, this wrong value will get written back without any checking. That can lead to hardware damage if, for example, an input pin is turned into output as a result. Created against linux-2.6.31-rc5 Tested on Amstrad Delta Signed-off-by: Janusz Krzysztofik --- --- linux-2.6.31-rc5/arch/arm/plat-omap/include/mach/mcbsp.h.orig 2009-08-11 23:43:25.000000000 +0200 +++ linux-2.6.31-rc5/arch/arm/plat-omap/include/mach/mcbsp.h 2009-08-11 23:45:46.000000000 +0200 @@ -377,6 +377,8 @@ struct omap_mcbsp { struct omap_mcbsp_platform_data *pdata; struct clk *iclk; struct clk *fclk; + + struct omap_mcbsp_reg_cfg reg_cache; }; extern struct omap_mcbsp **mcbsp_ptr; extern int omap_mcbsp_count; --- linux-2.6.31-rc5/arch/arm/plat-omap/mcbsp.c.orig 2009-08-11 23:43:25.000000000 +0200 +++ linux-2.6.31-rc5/arch/arm/plat-omap/mcbsp.c 2009-08-11 23:45:35.000000000 +0200 @@ -91,6 +91,7 @@ static void omap_mcbsp_dump_reg(u8 id) static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) { struct omap_mcbsp *mcbsp_tx = dev_id; + struct omap_mcbsp_reg_cfg *reg_cache = &mcbsp_tx->reg_cache; u16 irqst_spcr2; irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2); @@ -101,7 +102,7 @@ static irqreturn_t omap_mcbsp_tx_irq_han irqst_spcr2); /* Writing zero to XSYNC_ERR clears the IRQ */ OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2, - irqst_spcr2 & ~(XSYNC_ERR)); + reg_cache->spcr2 &= ~(XSYNC_ERR)); } else { complete(&mcbsp_tx->tx_irq_completion); } @@ -112,6 +113,7 @@ static irqreturn_t omap_mcbsp_tx_irq_han static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) { struct omap_mcbsp *mcbsp_rx = dev_id; + struct omap_mcbsp_reg_cfg *reg_cache = &mcbsp_rx->reg_cache; u16 irqst_spcr1; irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1); @@ -122,7 +124,7 @@ static irqreturn_t omap_mcbsp_rx_irq_han irqst_spcr1); /* Writing zero to RSYNC_ERR clears the IRQ */ OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1, - irqst_spcr1 & ~(RSYNC_ERR)); + reg_cache->spcr1 &= ~(RSYNC_ERR)); } else { complete(&mcbsp_rx->tx_irq_completion); } @@ -167,6 +169,7 @@ static void omap_mcbsp_rx_dma_callback(i void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) { struct omap_mcbsp *mcbsp; + struct omap_mcbsp_reg_cfg *reg_cache; void __iomem *io_base; if (!omap_mcbsp_check_valid_id(id)) { @@ -174,26 +177,27 @@ void omap_mcbsp_config(unsigned int id, return; } mcbsp = id_to_mcbsp_ptr(id); + reg_cache = &mcbsp->reg_cache; io_base = mcbsp->io_base; dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n", mcbsp->id, mcbsp->phys_base); /* We write the given config */ - OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2); - OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1); - OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2); - OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1); - OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2); - OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1); - OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2); - OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1); - OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2); - OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1); - OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0); + OMAP_MCBSP_WRITE(io_base, SPCR2, reg_cache->spcr2 = config->spcr2); + OMAP_MCBSP_WRITE(io_base, SPCR1, reg_cache->spcr1 = config->spcr1); + OMAP_MCBSP_WRITE(io_base, RCR2, reg_cache->rcr2 = config->rcr2); + OMAP_MCBSP_WRITE(io_base, RCR1, reg_cache->rcr1 = config->rcr1); + OMAP_MCBSP_WRITE(io_base, XCR2, reg_cache->xcr2 = config->xcr2); + OMAP_MCBSP_WRITE(io_base, XCR1, reg_cache->xcr1 = config->xcr1); + OMAP_MCBSP_WRITE(io_base, SRGR2, reg_cache->srgr2 = config->srgr2); + OMAP_MCBSP_WRITE(io_base, SRGR1, reg_cache->srgr1 = config->srgr1); + OMAP_MCBSP_WRITE(io_base, MCR2, reg_cache->mcr2 = config->mcr2); + OMAP_MCBSP_WRITE(io_base, MCR1, reg_cache->mcr1 = config->mcr1); + OMAP_MCBSP_WRITE(io_base, PCR0, reg_cache->pcr0 = config->pcr0); if (cpu_is_omap2430() || cpu_is_omap34xx()) { - OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr); - OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr); + OMAP_MCBSP_WRITE(io_base, XCCR, reg_cache->xccr = config->xccr); + OMAP_MCBSP_WRITE(io_base, RCCR, reg_cache->rccr = config->rccr); } } EXPORT_SYMBOL(omap_mcbsp_config); @@ -232,6 +236,7 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type); int omap_mcbsp_request(unsigned int id) { struct omap_mcbsp *mcbsp; + struct omap_mcbsp_reg_cfg *reg_cache; int err; if (!omap_mcbsp_check_valid_id(id)) { @@ -239,6 +244,7 @@ int omap_mcbsp_request(unsigned int id) return -ENODEV; } mcbsp = id_to_mcbsp_ptr(id); + reg_cache = &mcbsp->reg_cache; spin_lock(&mcbsp->lock); if (!mcbsp->free) { @@ -261,8 +267,8 @@ int omap_mcbsp_request(unsigned int id) * Make sure that transmitter, receiver and sample-rate generator are * not running before activating IRQs. */ - OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0); - OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0); + OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, reg_cache->spcr1 = 0); + OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, reg_cache->spcr2 = 0); if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { /* We need to get IRQs here */ @@ -335,42 +341,38 @@ EXPORT_SYMBOL(omap_mcbsp_free); void omap_mcbsp_start(unsigned int id, int tx, int rx) { struct omap_mcbsp *mcbsp; + struct omap_mcbsp_reg_cfg *reg_cache; void __iomem *io_base; int idle; - u16 w; if (!omap_mcbsp_check_valid_id(id)) { printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); return; } mcbsp = id_to_mcbsp_ptr(id); + reg_cache = &mcbsp->reg_cache; io_base = mcbsp->io_base; - mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7; - mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7; + mcbsp->rx_word_length = (reg_cache->rcr1 >> 5) & 0x7; + mcbsp->tx_word_length = (reg_cache->xcr1 >> 5) & 0x7; - idle = !((OMAP_MCBSP_READ(io_base, SPCR2) | - OMAP_MCBSP_READ(io_base, SPCR1)) & 1); + idle = !((reg_cache->spcr2 | reg_cache->spcr1) & 1); if (idle) { /* Start the sample generator */ - w = OMAP_MCBSP_READ(io_base, SPCR2); - OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6)); + OMAP_MCBSP_WRITE(io_base, SPCR2, reg_cache->spcr2 |= (1 << 6)); } /* Enable transmitter and receiver */ - w = OMAP_MCBSP_READ(io_base, SPCR2); - OMAP_MCBSP_WRITE(io_base, SPCR2, w | (tx & 1)); + OMAP_MCBSP_WRITE(io_base, SPCR2, reg_cache->spcr2 |= (tx & 1)); - w = OMAP_MCBSP_READ(io_base, SPCR1); - OMAP_MCBSP_WRITE(io_base, SPCR1, w | (rx & 1)); + OMAP_MCBSP_WRITE(io_base, SPCR1, reg_cache->spcr1 |= (rx & 1)); udelay(100); if (idle) { /* Start frame sync */ - w = OMAP_MCBSP_READ(io_base, SPCR2); - OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7)); + OMAP_MCBSP_WRITE(io_base, SPCR2, reg_cache->spcr2 |= (1 << 7)); } /* Dump McBSP Regs */ @@ -381,9 +383,9 @@ EXPORT_SYMBOL(omap_mcbsp_start); void omap_mcbsp_stop(unsigned int id, int tx, int rx) { struct omap_mcbsp *mcbsp; + struct omap_mcbsp_reg_cfg *reg_cache; void __iomem *io_base; int idle; - u16 w; if (!omap_mcbsp_check_valid_id(id)) { printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); @@ -391,23 +393,20 @@ void omap_mcbsp_stop(unsigned int id, in } mcbsp = id_to_mcbsp_ptr(id); + reg_cache = &mcbsp->reg_cache; io_base = mcbsp->io_base; /* Reset transmitter */ - w = OMAP_MCBSP_READ(io_base, SPCR2); - OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(tx & 1)); + OMAP_MCBSP_WRITE(io_base, SPCR2, reg_cache->spcr2 &= ~(tx & 1)); /* Reset receiver */ - w = OMAP_MCBSP_READ(io_base, SPCR1); - OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(rx & 1)); + OMAP_MCBSP_WRITE(io_base, SPCR1, reg_cache->spcr1 &= ~(rx & 1)); - idle = !((OMAP_MCBSP_READ(io_base, SPCR2) | - OMAP_MCBSP_READ(io_base, SPCR1)) & 1); + idle = !((reg_cache->spcr2 | reg_cache->spcr1) & 1); if (idle) { /* Reset the sample rate generator */ - w = OMAP_MCBSP_READ(io_base, SPCR2); - OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6)); + OMAP_MCBSP_WRITE(io_base, SPCR2, reg_cache->spcr2 &= ~(1 << 6)); } } EXPORT_SYMBOL(omap_mcbsp_stop); @@ -557,6 +556,7 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word); int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) { struct omap_mcbsp *mcbsp; + struct omap_mcbsp_reg_cfg *reg_cache; void __iomem *io_base; omap_mcbsp_word_length tx_word_length; omap_mcbsp_word_length rx_word_length; @@ -567,6 +567,7 @@ int omap_mcbsp_spi_master_xmit_word_poll return -ENODEV; } mcbsp = id_to_mcbsp_ptr(id); + reg_cache = &mcbsp->reg_cache; io_base = mcbsp->io_base; tx_word_length = mcbsp->tx_word_length; rx_word_length = mcbsp->rx_word_length; @@ -580,9 +581,11 @@ int omap_mcbsp_spi_master_xmit_word_poll spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); if (attempts++ > 1000) { /* We must reset the transmitter */ - OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST)); + OMAP_MCBSP_WRITE(io_base, SPCR2, + reg_cache->spcr2 &= (~XRST)); udelay(10); - OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); + OMAP_MCBSP_WRITE(io_base, SPCR2, + reg_cache->spcr2 |= XRST); udelay(10); dev_err(mcbsp->dev, "McBSP%d transmitter not " "ready\n", mcbsp->id); @@ -601,9 +604,11 @@ int omap_mcbsp_spi_master_xmit_word_poll spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); if (attempts++ > 1000) { /* We must reset the receiver */ - OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST)); + OMAP_MCBSP_WRITE(io_base, SPCR1, + reg_cache->spcr1 &= (~RRST)); udelay(10); - OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); + OMAP_MCBSP_WRITE(io_base, SPCR1, + reg_cache->spcr1 |= RRST); udelay(10); dev_err(mcbsp->dev, "McBSP%d receiver not " "ready\n", mcbsp->id); @@ -623,6 +628,7 @@ EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) { struct omap_mcbsp *mcbsp; + struct omap_mcbsp_reg_cfg *reg_cache; u32 clock_word = 0; void __iomem *io_base; omap_mcbsp_word_length tx_word_length; @@ -635,6 +641,7 @@ int omap_mcbsp_spi_master_recv_word_poll } mcbsp = id_to_mcbsp_ptr(id); + reg_cache = &mcbsp->reg_cache; io_base = mcbsp->io_base; tx_word_length = mcbsp->tx_word_length; @@ -649,9 +656,11 @@ int omap_mcbsp_spi_master_recv_word_poll spcr2 = OMAP_MCBSP_READ(io_base, SPCR2); if (attempts++ > 1000) { /* We must reset the transmitter */ - OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST)); + OMAP_MCBSP_WRITE(io_base, SPCR2, + reg_cache->spcr2 &= (~XRST)); udelay(10); - OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); + OMAP_MCBSP_WRITE(io_base, SPCR2, + reg_cache->spcr2 |= XRST); udelay(10); dev_err(mcbsp->dev, "McBSP%d transmitter not " "ready\n", mcbsp->id); @@ -670,9 +679,11 @@ int omap_mcbsp_spi_master_recv_word_poll spcr1 = OMAP_MCBSP_READ(io_base, SPCR1); if (attempts++ > 1000) { /* We must reset the receiver */ - OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST)); + OMAP_MCBSP_WRITE(io_base, SPCR1, + reg_cache->spcr1 &= (~RRST)); udelay(10); - OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); + OMAP_MCBSP_WRITE(io_base, SPCR1, + reg_cache->spcr1 |= RRST); udelay(10); dev_err(mcbsp->dev, "McBSP%d receiver not " "ready\n", mcbsp->id);

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