[Sound-open-firmware] [PATCH V3 1/3] platform: add sof_ipc_window for byt, hsw and bdw

[Xiuli Pan]

From: Pan Xiuli <xiuli.pan at linux.intel.com>

Add sof_ipc_window for all platforms, and add IPC send after boot
compelted. Also remove the deprecated ready window.

Signed-off-by: Pan Xiuli <xiuli.pan at linux.intel.com>
---
Test with:
Mininow max rt5651 GP-MRB nocodec
SOF master: 1693b66bb1d804ded975767cc1e5911e6ff9c93c
SOF-Tool master: a02abb799405d0e4ad0d6bb46eacf6fbe958c06e
https://github.com/plbossart/sound/tree/topic/sof-v4.14:
9513a73b981bc1917705671ec54402a7e21672eb

---
 src/platform/baytrail/platform.c | 45 ++++++++++++++++++++++++++++++++++++----
 src/platform/haswell/platform.c  | 45 ++++++++++++++++++++++++++++++++++++----
 2 files changed, 82 insertions(+), 8 deletions(-)

diff --git a/src/platform/baytrail/platform.c b/src/platform/baytrail/platform.c
index 4709fcd..2c4bfee 100644
--- a/src/platform/baytrail/platform.c
+++ b/src/platform/baytrail/platform.c
@@ -59,10 +59,6 @@ static const struct sof_ipc_fw_ready ready = {
 		.size = sizeof(struct sof_ipc_fw_ready),
 	},
 	/* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
-	.dspbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_DSPBOX_OFFSET,
-	.hostbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_HOSTBOX_OFFSET,
-	.dspbox_size = MAILBOX_DSPBOX_SIZE,
-	.hostbox_size = MAILBOX_HOSTBOX_SIZE,
 	.version = {
 		.build = REEF_BUILD,
 		.minor = REEF_MINOR,
@@ -74,6 +70,45 @@ static const struct sof_ipc_fw_ready ready = {
 	/* TODO: add capabilities */
 };
 
+#define NUM_BYT_WINDOWS		4
+static const struct sof_ipc_window sram_window = {
+	.ext_hdr	= {
+		.hdr.cmd = SOF_IPC_FW_READY,
+		.hdr.size = sizeof(struct sof_ipc_window) +
+			sizeof(struct sof_ipc_window_elem) * NUM_BYT_WINDOWS,
+		.type	= SOF_IPC_EXT_WINDOW,
+	},
+	.num_windows	= NUM_BYT_WINDOWS,
+	.window[0]	= {
+		.type	= SOF_IPC_REGION_UPBOX,
+		.id	= 0,	/* map to host window 0 */
+		.flags	= 0, // TODO: set later
+		.size	= MAILBOX_DSPBOX_SIZE,
+		.offset	= MAILBOX_DSPBOX_OFFSET,
+	},
+	.window[1]	= {
+		.type	= SOF_IPC_REGION_DOWNBOX,
+		.id	= 0,	/* map to host window 0 */
+		.flags	= 0, // TODO: set later
+		.size	= MAILBOX_HOSTBOX_SIZE,
+		.offset	= MAILBOX_HOSTBOX_OFFSET,
+	},
+	.window[2]	= {
+		.type	= SOF_IPC_REGION_DEBUG,
+		.id	= 0,	/* map to host window 0 */
+		.flags	= 0, // TODO: set later
+		.size	= MAILBOX_DEBUG_SIZE,
+		.offset	= MAILBOX_DEBUG_OFFSET,
+	},
+	.window[3]	= {
+		.type	= SOF_IPC_REGION_TRACE,
+		.id	= 0,	/* map to host window 0 */
+		.flags	= 0, // TODO: set later
+		.size	= MAILBOX_TRACE_SIZE,
+		.offset	= MAILBOX_TRACE_OFFSET,
+	},
+};
+
 static struct work_queue_timesource platform_generic_queue = {
 	.timer	 = {
 		.id = TIMER3,	/* external timer */
@@ -93,6 +128,8 @@ int platform_boot_complete(uint32_t boot_message)
 	uint64_t outbox = MAILBOX_HOST_OFFSET >> 3;
 
 	mailbox_dspbox_write(0, &ready, sizeof(ready));
+	mailbox_dspbox_write(sizeof(ready), &sram_window,
+			     sram_window.ext_hdr.hdr.size);
 
 	/* now interrupt host to tell it we are done booting */
 	shim_write(SHIM_IPCDL, SOF_IPC_FW_READY | outbox);
diff --git a/src/platform/haswell/platform.c b/src/platform/haswell/platform.c
index 5f56a05..97b38af 100644
--- a/src/platform/haswell/platform.c
+++ b/src/platform/haswell/platform.c
@@ -58,10 +58,6 @@ static const struct sof_ipc_fw_ready ready = {
 		.size = sizeof(struct sof_ipc_fw_ready),
 	},
 	/* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */
-	.dspbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_DSPBOX_OFFSET,
-	.hostbox_offset = MAILBOX_HOST_OFFSET + MAILBOX_HOSTBOX_OFFSET,
-	.dspbox_size = MAILBOX_DSPBOX_SIZE,
-	.hostbox_size = MAILBOX_HOSTBOX_SIZE,
 	.version = {
 		.build = REEF_BUILD,
 		.minor = REEF_MINOR,
@@ -73,6 +69,45 @@ static const struct sof_ipc_fw_ready ready = {
 	/* TODO: add capabilities */
 };
 
+#define NUM_HSW_WINDOWS		4
+static const struct sof_ipc_window sram_window = {
+	.ext_hdr	= {
+		.hdr.cmd = SOF_IPC_FW_READY,
+		.hdr.size = sizeof(struct sof_ipc_window) +
+			sizeof(struct sof_ipc_window_elem) * NUM_HSW_WINDOWS,
+		.type	= SOF_IPC_EXT_WINDOW,
+	},
+	.num_windows	= NUM_HSW_WINDOWS,
+	.window[0]	= {
+		.type	= SOF_IPC_REGION_UPBOX,
+		.id	= 0,	/* map to host window 0 */
+		.flags	= 0, // TODO: set later
+		.size	= MAILBOX_DSPBOX_SIZE,
+		.offset	= MAILBOX_DSPBOX_OFFSET,
+	},
+	.window[1]	= {
+		.type	= SOF_IPC_REGION_DOWNBOX,
+		.id	= 0,	/* map to host window 0 */
+		.flags	= 0, // TODO: set later
+		.size	= MAILBOX_HOSTBOX_SIZE,
+		.offset	= MAILBOX_HOSTBOX_OFFSET,
+	},
+	.window[2]	= {
+		.type	= SOF_IPC_REGION_DEBUG,
+		.id	= 0,	/* map to host window 0 */
+		.flags	= 0, // TODO: set later
+		.size	= MAILBOX_DEBUG_SIZE,
+		.offset	= MAILBOX_DEBUG_OFFSET,
+	},
+	.window[3]	= {
+		.type	= SOF_IPC_REGION_TRACE,
+		.id	= 0,	/* map to host window 0 */
+		.flags	= 0, // TODO: set later
+		.size	= MAILBOX_TRACE_SIZE,
+		.offset	= MAILBOX_TRACE_OFFSET,
+	},
+};
+
 static struct work_queue_timesource platform_generic_queue = {
 	.timer	 = {
 		.id = TIMER2,	/* external timer using SSP */
@@ -92,6 +127,8 @@ int platform_boot_complete(uint32_t boot_message)
 	uint32_t outbox = MAILBOX_HOST_OFFSET >> 3;
 
 	mailbox_dspbox_write(0, &ready, sizeof(ready));
+	mailbox_dspbox_write(sizeof(ready), &sram_window,
+			     sram_window.ext_hdr.hdr.size);
 
 	/* now interrupt host to tell it we are done booting */
 	shim_write(SHIM_IPCD, outbox | SHIM_IPCD_BUSY);
-- 
2.7.4