[Sound-open-firmware] [PATCH 1/4] [RFC]DMIC: Add PDM microphones (DMIC) support to DAI
Seppo Ingalsuo
seppo.ingalsuo at linux.intel.com
Mon Apr 30 18:04:16 CEST 2018
This patch adds the DMIC audio capture driver for SOF DAI component use.
The DMIC feature allows to directly attach one to (typically) four PDM
digital microphones into Intel SoC without a separate codec IC. This is
supported by APL and most successor platforms.
Corresponding patches are needed for kernel driver and topology to enable
this feature.
Tested in
APL UP squared board without connected microphones
SOF git master 3ad69eb715a09de9a0b91c56c9cca8a79ead00a9
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo at linux.intel.com>
---
configure.ac | 6 +
src/audio/dai.c | 5 +
src/drivers/Makefile.am | 6 +-
src/drivers/dmic.c | 1331 +++++++++++++++++++++++++++++++++++++++++++++++
src/include/sof/dmic.h | 318 +++++++++++
src/include/sof/io.h | 8 +
src/include/sof/trace.h | 3 +-
src/include/uapi/ipc.h | 61 ++-
8 files changed, 1734 insertions(+), 4 deletions(-)
create mode 100644 src/drivers/dmic.c
create mode 100644 src/include/sof/dmic.h
diff --git a/configure.ac b/configure.ac
index d67c154..49e58a5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -44,6 +44,12 @@ if test "$have_rimage" = "yes"; then
fi
AM_CONDITIONAL(BUILD_RIMAGE, test "$have_rimage" = "yes")
+# Disable DMIC driver if requested, by default build for supported platforms
+AC_ARG_ENABLE([dmic], AS_HELP_STRING([--disable-dmic], [Disable DMIC driver]))
+AS_IF([test "x$enable_dmic" != "xno"], [
+ AC_DEFINE([CONFIG_DMIC], [1], [Configure to build DMIC driver])
+])
+
# Architecture support
AC_ARG_WITH([arch],
AS_HELP_STRING([--with-arch], [Specify DSP architecture]),
diff --git a/src/audio/dai.c b/src/audio/dai.c
index 7905665..1eeecd2 100644
--- a/src/audio/dai.c
+++ b/src/audio/dai.c
@@ -639,6 +639,11 @@ static int dai_config(struct comp_dev *dev, struct sof_ipc_dai_config *config)
break;
}
break;
+ case SOF_DAI_INTEL_DMIC:
+ /* TODO: No hardwired values here. */
+ dd->config.burst_elems = 2;
+ dev->frame_bytes = 8;
+ break;
default:
/* other types of DAIs not handled for now */
trace_dai_error("de2");
diff --git a/src/drivers/Makefile.am b/src/drivers/Makefile.am
index 99232a3..5d0c5b3 100644
--- a/src/drivers/Makefile.am
+++ b/src/drivers/Makefile.am
@@ -13,12 +13,14 @@ endif
if BUILD_APOLLOLAKE
libdrivers_a_SOURCES += \
- hda-dma.c
+ hda-dma.c \
+ dmic.c
endif
if BUILD_CANNONLAKE
libdrivers_a_SOURCES += \
- hda-dma.c
+ hda-dma.c \
+ dmic.c
endif
libdrivers_a_CFLAGS = \
diff --git a/src/drivers/dmic.c b/src/drivers/dmic.c
new file mode 100644
index 0000000..d6b623b
--- /dev/null
+++ b/src/drivers/dmic.c
@@ -0,0 +1,1331 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Seppo Ingalsuo <seppo.ingalsuo at linux.intel.com>
+ */
+
+#include <sof/stream.h>
+#include <sof/dmic.h>
+#include <sof/interrupt.h>
+#include <sof/math/numbers.h>
+#include <sof/audio/format.h>
+
+#if defined DMIC_HW_VERSION
+
+#include <sof/audio/coefficients/pdm_decim/pdm_decim_table.h>
+
+#if defined MODULE_TEST
+#include <stdio.h>
+#endif
+
+#define DMIC_MAX_MODES 45
+
+/* HW FIR pipeline needs 5 additional cycles per channel for internal
+ * operations. This is used in MAX filter length check.
+ */
+#define DMIC_FIR_PIPELINE_OVERHEAD 5
+
+/* Force a 48 kHz config while kernel driver IPC is under construction. Remove
+ * or undefine when it's available.
+ */
+#define DMIC_FORCE_CONFIG
+
+struct decim_modes {
+ int clkdiv[DMIC_MAX_MODES];
+ int mcic[DMIC_MAX_MODES];
+ int mfir[DMIC_MAX_MODES];
+ int num_of_modes;
+};
+
+struct matched_modes {
+ int clkdiv[DMIC_MAX_MODES];
+ int mcic[DMIC_MAX_MODES];
+ int mfir_a[DMIC_MAX_MODES];
+ int mfir_b[DMIC_MAX_MODES];
+ int num_of_modes;
+};
+
+struct dmic_configuration {
+ struct pdm_decim *fir_a;
+ struct pdm_decim *fir_b;
+ int clkdiv;
+ int mcic;
+ int mfir_a;
+ int mfir_b;
+ int cic_shift;
+ int fir_a_shift;
+ int fir_b_shift;
+ int fir_a_length;
+ int fir_b_length;
+ int32_t fir_a_scale;
+ int32_t fir_b_scale;
+};
+
+struct pdm_controllers_configuration {
+ uint32_t cic_control;
+ uint32_t cic_config;
+ uint32_t mic_control;
+ uint32_t fir_control_a;
+ uint32_t fir_config_a;
+ uint32_t dc_offset_left_a;
+ uint32_t dc_offset_right_a;
+ uint32_t out_gain_left_a;
+ uint32_t out_gain_right_a;
+ uint32_t fir_control_b;
+ uint32_t fir_config_b;
+ uint32_t dc_offset_left_b;
+ uint32_t dc_offset_right_b;
+ uint32_t out_gain_left_b;
+ uint32_t out_gain_right_b;
+};
+
+/* Configuration ABI version, increment if not compatible with previous
+ * version.
+ */
+#define DMIC_IPC_VERSION 1
+
+/* Minimum OSR is always applied for 48 kHz and less sample rates */
+#define DMIC_MIN_OSR 50
+
+/* These are used as guideline for configuring > 48 kHz sample rates. The
+ * minimum OSR can be relaxed down to 40 (use 3.84 MHz clock for 96 kHz).
+ */
+#define DMIC_HIGH_RATE_MIN_FS 64000
+#define DMIC_HIGH_RATE_OSR_MIN 40
+
+/* Used if scaling FIR coeffcients for HW */
+#define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
+#define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)
+
+/* tracing */
+#define trace_dmic(__e) trace_event(TRACE_CLASS_DMIC, __e)
+#define trace_dmic_error(__e) trace_error(TRACE_CLASS_DMIC, __e)
+#define tracev_dmic(__e) tracev_event(TRACE_CLASS_DMIC, __e)
+
+/* Base addresses (in PDM scope) of 2ch PDM controllers and coefficient RAM. */
+static const uint32_t base[4] = {PDM0, PDM1, PDM2, PDM3};
+static const uint32_t coef_base_a[4] = {PDM0_COEFFICIENT_A, PDM1_COEFFICIENT_A,
+ PDM2_COEFFICIENT_A, PDM3_COEFFICIENT_A};
+static const uint32_t coef_base_b[4] = {PDM0_COEFFICIENT_B, PDM1_COEFFICIENT_B,
+ PDM2_COEFFICIENT_B, PDM3_COEFFICIENT_B};
+
+#if defined MODULE_TEST
+#define IO_BYTES_GLOBAL (PDM0 - OUTCONTROL0)
+#define IO_BYTES_MIDDLE (PDM1 - PDM0)
+#define IO_BYTES_LAST (PDM0_COEFFICIENT_B + PDM_COEF_RAM_B_LENGTH - PDM0)
+#define IO_BYTES (((DMIC_HW_CONTROLLERS) - 1) * (IO_BYTES_MIDDLE) \
+ + (IO_BYTES_LAST) + (IO_BYTES_GLOBAL))
+#define IO_LENGTH ((IO_BYTES) >> 2)
+
+static uint32_t dmic_io[IO_LENGTH];
+
+static void dmic_write(struct dai *dai, uint32_t reg, uint32_t value)
+{
+ printf("W %04x %08x\n", reg, value);
+ dmic_io[reg >> 2] = value;
+}
+
+static uint32_t dmic_read(struct dai *dai, uint32_t reg)
+{
+ uint32_t value = dmic_io[reg >> 2];
+
+ printf("R %04x %08x\n", reg, value);
+ return value;
+}
+
+static void dmic_update_bits(struct dai *dai, uint32_t reg, uint32_t mask,
+ uint32_t value)
+{
+ uint32_t new_value;
+ uint32_t old_value = dmic_io[reg >> 2];
+
+ new_value = (old_value & (~mask)) | value;
+ dmic_io[reg >> 2] = new_value;
+ printf("W %04x %08x\n", reg, new_value);
+}
+#else
+
+static void dmic_write(struct dai *dai, uint32_t reg, uint32_t value)
+{
+ io_reg_write(dai_base(dai) + reg, value);
+}
+
+static uint32_t dmic_read(struct dai *dai, uint32_t reg)
+{
+ return io_reg_read(dai_base(dai) + reg);
+}
+
+static void dmic_update_bits(struct dai *dai, uint32_t reg, uint32_t mask,
+ uint32_t value)
+{
+ io_reg_update_bits(dai_base(dai) + reg, mask, value);
+}
+#endif
+
+/* This function returns a raw list of potential microphone clock and decimation
+ * modes for achieving requested sample rates. The search is constrained by
+ * decimation HW capabililies and setup parameters. The parameters such as
+ * microphone clock min/max and duty cycle requirements need be checked from
+ * used microphone component datasheet.
+ */
+static void find_modes(struct decim_modes *modes,
+ struct sof_ipc_dai_dmic_params *prm, uint32_t fs)
+{
+ int clkdiv_min;
+ int clkdiv_max;
+ int clkdiv;
+ int c1;
+ int c2;
+ int du_min;
+ int du_max;
+ int pdmclk;
+ int osr;
+ int mfir;
+ int mcic;
+ int ioclk_test;
+ int osr_min = DMIC_MIN_OSR;
+ int i = 0;
+
+ /* Defaults, empty result */
+ modes->num_of_modes = 0;
+
+ /* The FIFO is not requested if sample rate is set to zero. Just
+ * return in such case with num_of_modes as zero.
+ */
+ if (fs == 0)
+ return;
+
+ /* Override DMIC_MIN_OSR for very high sample rates, use as minimum
+ * the nominal clock for the high rates.
+ */
+ if (fs >= DMIC_HIGH_RATE_MIN_FS)
+ osr_min = DMIC_HIGH_RATE_OSR_MIN;
+
+ /* Check for sane pdm clock, min 100 kHz, max ioclk/2 */
+ if (prm->pdmclk_max < DMIC_HW_PDM_CLK_MIN ||
+ prm->pdmclk_max > DMIC_HW_IOCLK / 2) {
+ trace_dmic_error("pmx");
+ return;
+ }
+ if (prm->pdmclk_min < DMIC_HW_PDM_CLK_MIN ||
+ prm->pdmclk_min > prm->pdmclk_max) {
+ trace_dmic_error("pmn");
+ return;
+ }
+
+ /* Check for sane duty cycle */
+ if (prm->duty_min > prm->duty_max) {
+ trace_dmic_error("pdu");
+ return;
+ }
+ if (prm->duty_min < DMIC_HW_DUTY_MIN ||
+ prm->duty_min > DMIC_HW_DUTY_MAX) {
+ trace_dmic_error("pdn");
+ return;
+ }
+ if (prm->duty_max < DMIC_HW_DUTY_MIN ||
+ prm->duty_max > DMIC_HW_DUTY_MAX) {
+ trace_dmic_error("pdx");
+ return;
+ }
+
+ /* Min and max clock dividers */
+ clkdiv_min = ceil_divide(DMIC_HW_IOCLK, prm->pdmclk_max);
+ clkdiv_min = MAX(clkdiv_min, DMIC_HW_CIC_DECIM_MIN);
+ clkdiv_max = DMIC_HW_IOCLK / prm->pdmclk_min;
+
+ /* Loop possible clock dividers and check based on resulting
+ * oversampling ratio that CIC and FIR decimation ratios are
+ * feasible. The ratios need to be integers. Also the mic clock
+ * duty cycle need to be within limits.
+ */
+ for (clkdiv = clkdiv_min; clkdiv <= clkdiv_max; clkdiv++) {
+ c1 = clkdiv >> 1;
+ c2 = clkdiv - c1;
+ du_min = 100 * c1 / clkdiv;
+ du_max = 100 * c2 / clkdiv;
+ pdmclk = DMIC_HW_IOCLK / clkdiv;
+ osr = pdmclk / fs;
+
+ /* Check that OSR constraints is met and clock duty cycle does
+ * not exceed microphone specification. If exceed proceed to
+ * next clkdiv.
+ */
+ if (osr < osr_min || du_min < prm->duty_min ||
+ du_max > prm->duty_max)
+ continue;
+
+ /* Loop FIR decimation factors candidates. If the
+ * integer divided decimation factors and clock dividers
+ * as multiplied with sample rate match the IO clock
+ * rate the division was exact and such decimation mode
+ * is possible. Then check that CIC decimation constraints
+ * are met. The passed decimation modes are added to array.
+ */
+ for (mfir = DMIC_HW_FIR_DECIM_MIN;
+ mfir <= DMIC_HW_FIR_DECIM_MAX; mfir++) {
+ mcic = osr / mfir;
+ ioclk_test = fs * mfir * mcic * clkdiv;
+
+ if (ioclk_test == DMIC_HW_IOCLK &&
+ mcic >= DMIC_HW_CIC_DECIM_MIN &&
+ mcic <= DMIC_HW_CIC_DECIM_MAX &&
+ i < DMIC_MAX_MODES) {
+ modes->clkdiv[i] = clkdiv;
+ modes->mcic[i] = mcic;
+ modes->mfir[i] = mfir;
+ i++;
+ modes->num_of_modes = i;
+ }
+ }
+ }
+}
+
+/* The previous raw modes list contains sane configuration possibilities. When
+ * there is request for both FIFOs A and B operation this function returns
+ * list of compatible settings.
+ */
+static void match_modes(struct matched_modes *c, struct decim_modes *a,
+ struct decim_modes *b)
+{
+ int idx[DMIC_MAX_MODES];
+ int idx_length;
+ int i;
+ int n;
+ int m;
+
+ /* Check if previous search got results. */
+ c->num_of_modes = 0;
+ if (a->num_of_modes == 0 && b->num_of_modes == 0) {
+ /* Nothing to do */
+ return;
+ }
+
+ /* Check for request only for FIFO A or B. In such case pass list for
+ * A or B as such.
+ */
+ if (b->num_of_modes == 0) {
+ c->num_of_modes = a->num_of_modes;
+ for (i = 0; i < a->num_of_modes; i++) {
+ c->clkdiv[i] = a->clkdiv[i];
+ c->mcic[i] = a->mcic[i];
+ c->mfir_a[i] = a->mfir[i];
+ c->mfir_b[i] = 0;
+ }
+ return;
+ }
+
+ if (a->num_of_modes == 0) {
+ c->num_of_modes = b->num_of_modes;
+ for (i = 0; i < b->num_of_modes; i++) {
+ c->clkdiv[i] = b->clkdiv[i];
+ c->mcic[i] = b->mcic[i];
+ c->mfir_b[i] = b->mfir[i];
+ c->mfir_a[i] = 0;
+ }
+ return;
+ }
+
+ /* Merge a list of compatible modes */
+ i = 0;
+ for (n = 0; n < a->num_of_modes; n++) {
+ /* Find all indices of values a->clkdiv[n] in b->clkdiv[] */
+ idx_length = find_equal(idx, b->clkdiv, a->clkdiv[n],
+ b->num_of_modes, 0);
+ for (m = 0; m < idx_length; m++) {
+ if (b->mcic[idx[m]] == a->mcic[n]) {
+ c->clkdiv[i] = a->clkdiv[n];
+ c->mcic[i] = a->mcic[n];
+ c->mfir_a[i] = a->mfir[n];
+ c->mfir_b[i] = b->mfir[idx[m]];
+ i++;
+ }
+ }
+ c->num_of_modes = i;
+ }
+}
+
+/* Finds a suitable FIR decimation filter from the included set */
+static struct pdm_decim *get_fir(struct dmic_configuration *cfg, int mfir)
+{
+ int i;
+ int fs;
+ int cic_fs;
+ int fir_max_length;
+ struct pdm_decim *fir = NULL;
+
+ if (mfir <= 0)
+ return fir;
+
+ cic_fs = DMIC_HW_IOCLK / cfg->clkdiv / cfg->mcic;
+ fs = cic_fs / mfir;
+ /* FIR max. length depends on available cycles and coef RAM
+ * length. Exceeding this length sets HW overrun status and
+ * overwrite of other register.
+ */
+ fir_max_length = MIN(DMIC_HW_FIR_LENGTH_MAX,
+ DMIC_HW_IOCLK / fs / 2 - DMIC_FIR_PIPELINE_OVERHEAD);
+
+ for (i = 0; i < DMIC_FIR_LIST_LENGTH; i++) {
+ if (fir_list[i]->decim_factor == mfir &&
+ fir_list[i]->length <= fir_max_length) {
+ /* Store pointer, break from loop to avoid a
+ * Possible other mode with lower FIR length.
+ */
+ fir = fir_list[i];
+ break;
+ }
+ }
+
+ return fir;
+}
+
+/* Calculate scale and shift to use for FIR coefficients. Scale is applied
+ * before write to HW coef RAM. Shift will be programmed to HW register.
+ */
+static int fir_coef_scale(int32_t *fir_scale, int *fir_shift, int add_shift,
+ const int32_t coef[], int coef_length, int32_t gain)
+{
+ int32_t amax;
+ int32_t new_amax;
+ int32_t new_scale;
+ int32_t fir_gain;
+ int shift;
+ const int32_t coef_max_val = Q_CONVERT_FLOAT(0.9999, 20); /* Q1.20 */
+
+ /* Multiply gain passed from CIC with output full scale, result Q4.20 */
+ fir_gain = Q_MULTSR_32X32((int64_t)gain, DMIC_HW_SENS_Q23, 20, 23, 20);
+
+ /* Find the largest FIR coefficient value */
+ amax = find_max_abs_int32((int32_t *)coef, coef_length);
+
+ /* Scale with FIR gain */
+ new_amax = Q_MULTSR_32X32((int64_t)amax, fir_gain, 31, 20, 20);
+ if (new_amax <= 0)
+ return -EINVAL;
+
+ /* Needed scale for FIR taps, target is 0.9999 max */
+ new_scale = (int32_t)((((int64_t)coef_max_val << 20)) / new_amax);
+
+ /* Find shift value */
+ if (new_scale == 0)
+ return -EINVAL;
+
+ shift = 0;
+ while ((new_scale << shift) < (1 << 20))
+ shift++;
+
+ /* Add to shift in storate Q31 format and store to configuration */
+ *fir_shift = shift + add_shift;
+
+ /* Compensate shift value to scale and store to configuration
+ * as Q1.31. Also apply raw 32 bit to actual HW FIR coef
+ * precision.
+ */
+ *fir_scale = (fir_gain >> shift);
+ return 0;
+}
+
+/* This function selects with a simple criteria one mode to set up the
+ * decimator. For the settings chosen for FIFOs A and B output a lookup
+ * is done for FIR coefficients from the included coefficients tables.
+ * For some decimation factors there may be several length coefficient sets.
+ * It is due to possible restruction of decimation engine cycles per given
+ * sample rate. If the coefficients length is exceeded the lookup continues.
+ * Therefore the list of coefficient set must present the filters for a
+ * decimation factor in decreasing length order.
+ *
+ * Note: If there is no filter available an error is returned. The parameters
+ * should be reviewed for such case. If still a filter is missing it should be
+ * added into the included set. FIR decimation with a high factor usually
+ * needs compromizes into specifications and is not desirable.
+ */
+static int select_mode(struct dmic_configuration *cfg,
+ struct matched_modes *modes)
+{
+ int32_t g_cic;
+ int32_t g_tmp;
+ int32_t fir_in_max;
+ int32_t cic_out_max;
+ int32_t gain_to_fir;
+ int idx[DMIC_MAX_MODES];
+ int n = 1;
+ int mmin;
+ int count;
+ int *mfir;
+ int mcic;
+ int bits_cic;
+ int ret;
+
+ /* If there are more than one possibilities select a mode with lowest
+ * FIR decimation factor. If there are several select mode with highest
+ * ioclk divider to minimize microphone power consumption. The highest
+ * clock divisors are in the end of list so select the last of list.
+ * The minimum OSR criteria used in previous ensures that quality in
+ * the candidates should be sufficient.
+ */
+ if (modes->num_of_modes == 0) {
+ trace_dmic_error("nom");
+ return -EINVAL;
+ }
+
+ if (modes->mfir_a[0] > 0)
+ mfir = modes->mfir_a;
+ else
+ mfir = modes->mfir_b;
+
+ mmin = find_min(mfir, modes->num_of_modes);
+ count = find_equal(idx, mfir, mmin, modes->num_of_modes, 0);
+ n = idx[count - 1];
+
+ /* Get microphone clock and decimation parameters for used mode from
+ * the list.
+ */
+ cfg->clkdiv = modes->clkdiv[n];
+ cfg->mfir_a = modes->mfir_a[n];
+ cfg->mfir_b = modes->mfir_b[n];
+ cfg->mcic = modes->mcic[n];
+ cfg->fir_a = NULL;
+ cfg->fir_b = NULL;
+
+ /* Find raw FIR coefficients to match the decimation foctors of FIR
+ * A and B.
+ */
+ if (cfg->mfir_a > 0) {
+ cfg->fir_a = get_fir(cfg, cfg->mfir_a);
+ if (!cfg->fir_a) {
+ trace_dmic_error("fam");
+ trace_value(cfg->mfir_a);
+ return -EINVAL;
+ }
+ }
+
+ if (cfg->mfir_b > 0) {
+ cfg->fir_b = get_fir(cfg, cfg->mfir_b);
+ if (!cfg->fir_b) {
+ trace_dmic_error("fbm");
+ trace_value(cfg->mfir_b);
+ return -EINVAL;
+ }
+ }
+
+ /* Calculate CIC shift from the decimation factor specific gain.
+ */
+ mcic = cfg->mcic;
+ g_cic = mcic * mcic * mcic * mcic * mcic;
+ g_tmp = g_cic;
+ bits_cic = 1;
+ if (g_tmp < 0) {
+ /* Erroneus decimation factor and CIC gain */
+ trace_dmic_error("gci");
+ return -EINVAL;
+ }
+ while (g_tmp > 0) {
+ g_tmp = g_tmp >> 1;
+ bits_cic++;
+ }
+ cfg->cic_shift = bits_cic - DMIC_HW_BITS_FIR_INPUT;
+
+ /* Calculate remaining gain to FIR as Q4.20. */
+ fir_in_max = (1 << (DMIC_HW_BITS_FIR_INPUT - 1));
+ if (cfg->cic_shift >= 0)
+ cic_out_max = g_cic >> cfg->cic_shift;
+ else
+ cic_out_max = g_cic << -cfg->cic_shift;
+
+ gain_to_fir = (int32_t)((((int64_t) fir_in_max) << 20) / cic_out_max);
+
+ /* Calculate FIR scale and shift */
+ if (cfg->mfir_a > 0) {
+ cfg->fir_a_length = cfg->fir_a->length;
+ ret = fir_coef_scale(&cfg->fir_a_scale, &cfg->fir_a_shift,
+ cfg->fir_a->shift, cfg->fir_a->coef, cfg->fir_a->length,
+ gain_to_fir);
+ if (ret < 0) {
+ /* Invalid coefficient set found, should not happen. */
+ trace_dmic_error("ina");
+ return -EINVAL;
+ }
+ } else {
+ cfg->fir_a_scale = 0;
+ cfg->fir_a_shift = 0;
+ cfg->fir_a_length = 0;
+ }
+
+ if (cfg->mfir_b > 0) {
+ cfg->fir_b_length = cfg->fir_b->length;
+ ret = fir_coef_scale(&cfg->fir_b_scale, &cfg->fir_b_shift,
+ cfg->fir_b->shift, cfg->fir_b->coef, cfg->fir_b->length,
+ gain_to_fir);
+ if (ret < 0) {
+ /* Invalid coefficient set found, should not happen. */
+ trace_dmic_error("inb");
+ return -EINVAL;
+ }
+ } else {
+ cfg->fir_b_scale = 0;
+ cfg->fir_b_shift = 0;
+ cfg->fir_b_length = 0;
+ }
+
+ return 0;
+}
+
+/* The FIFO input packer mode (IPM) settings are somewhat different in
+ * HW versions. This helper function returns a suitable IPM bit field
+ * value to use.
+ */
+#if DMIC_HW_VERSION == 1
+
+static inline void ipm_helper(int *ipm, int stereo[], int swap[],
+ struct sof_ipc_dai_dmic_params *dmic)
+{
+ int pdm[DMIC_HW_CONTROLLERS];
+ int i;
+
+ /* Loop number of PDM controllers in the configuration. If mic A
+ * or B is enabled then a pdm controller is marked as active. Also it
+ * is checked whether the controller should operate as stereo or mono
+ * left (A) or mono right (B) mode. Mono right mode is setup as channel
+ * swapped mono left.
+ */
+ for (i = 0; i < dmic->number_of_pdm_controllers; i++) {
+ if (dmic->pdm[i].enable_mic_a > 0 ||
+ dmic->pdm[i].enable_mic_b > 0)
+ pdm[i] = 1;
+ else
+ pdm[i] = 0;
+
+ if (dmic->pdm[i].enable_mic_a > 0 &&
+ dmic->pdm[i].enable_mic_b > 0) {
+ stereo[i] = 1;
+ swap[i] = 0;
+ } else {
+ stereo[i] = 0;
+ if (dmic->pdm[i].enable_mic_a == 0)
+ swap[i] = 1;
+ else
+ swap[i] = 0;
+ }
+ }
+
+ /* IPM indicates active pdm controllers. */
+ *ipm = 0;
+
+ if (pdm[0] == 0 && pdm[1] > 0)
+ *ipm = 1;
+
+ if (pdm[0] > 0 && pdm[1] > 0)
+ *ipm = 2;
+}
+#endif
+
+#if DMIC_HW_VERSION == 2
+
+static inline void source_ipm_helper(int source[], int *ipm, int stereo[],
+ int swap[], struct sof_ipc_dai_dmic_params *dmic)
+{
+ int pdm[DMIC_HW_CONTROLLERS];
+ int i;
+ int n = 0;
+
+ /* Loop number of PDM controllers in the configuration. If mic A
+ * or B is enabled then a pdm controller is marked as active. Also it
+ * is checked whether the controller should operate as stereo or mono
+ * left (A) or mono right (B) mode. Mono right mode is setup as channel
+ * swapped mono left. The function returns also in array source[] the
+ * indice of enabled pdm controllers to be used for IPM configuration.
+ */
+ for (i = 0; i < dmic->number_of_pdm_controllers; i++) {
+ if (dmic->pdm[i].enable_mic_a > 0 ||
+ dmic->pdm[i].enable_mic_b > 0) {
+ pdm[i] = 1;
+ source[n] = i;
+ n++;
+ } else {
+ pdm[i] = 0;
+ swap[i] = 0;
+ }
+
+ if (dmic->pdm[i].enable_mic_a > 0 &&
+ dmic->pdm[i].enable_mic_b > 0) {
+ stereo[i] = 1;
+ swap[i] = 0;
+ } else {
+ stereo[i] = 0;
+ if (dmic->pdm[i].enable_mic_a == 0)
+ swap[i] = 1;
+ else
+ swap[i] = 0;
+ }
+ }
+
+ /* IPM bit field is set to count of active pdm controllers. */
+ *ipm = pdm[0];
+ for (i = 0; i < dmic->number_of_pdm_controllers; i++)
+ *ipm += pdm[i];
+}
+#endif
+
+static int configure_registers(struct dai *dai, struct dmic_configuration *cfg,
+ struct sof_ipc_dai_dmic_params *dmic)
+{
+ int stereo[DMIC_HW_CONTROLLERS];
+ int swap[DMIC_HW_CONTROLLERS];
+ uint32_t val;
+ int32_t ci;
+ uint32_t cu;
+ int ipm;
+ int of0;
+ int of1;
+ int fir_decim;
+ int fir_length;
+ int length;
+ int edge;
+ int dccomp;
+ int cic_start_a;
+ int cic_start_b;
+ int fir_start_a;
+ int fir_start_b;
+ int soft_reset;
+ int i;
+ int j;
+
+ struct dmic_pdata *pdata = dai_get_drvdata(dai);
+ int array_a = 0;
+ int array_b = 0;
+ int cic_mute = 0;
+ int fir_mute = 0;
+ int bfth = 1; /* Should be 3 for 8 entries, 1 is 2 entries */
+ int th = 0; /* Used with TIE=1 */
+
+ /* Normal start sequence */
+ dccomp = 1;
+ soft_reset = 1;
+ cic_start_a = 0;
+ cic_start_b = 0;
+ fir_start_a = 0;
+ fir_start_b = 0;
+
+#if DMIC_HW_VERSION == 2
+ int source[4] = {0, 0, 0, 0};
+#endif
+
+ /* pdata is set by dmic_probe(), error if it has not been set */
+ if (!pdata) {
+ trace_dmic_error("cfr");
+ return -EINVAL;
+ }
+
+ /* Sanity checks */
+ if (dmic->number_of_pdm_controllers > DMIC_HW_CONTROLLERS) {
+ trace_dmic_error("num");
+ return -EINVAL;
+ }
+
+ /* OUTCONTROL0 and OUTCONTROL1 */
+ trace_dmic("reg");
+ of0 = (dmic->fifo_bits_a == 32) ? 2 : 0;
+ of1 = (dmic->fifo_bits_b == 32) ? 2 : 0;
+
+#if DMIC_HW_VERSION == 1
+ ipm_helper(&ipm, stereo, swap, dmic);
+ val = OUTCONTROL0_TIE(0) |
+ OUTCONTROL0_SIP(0) |
+ OUTCONTROL0_FINIT(1) |
+ OUTCONTROL0_FCI(0) |
+ OUTCONTROL0_BFTH(bfth) |
+ OUTCONTROL0_OF(of0) |
+ OUTCONTROL0_IPM(ipm) |
+ OUTCONTROL0_TH(th);
+ dmic_write(dai, OUTCONTROL0, val);
+ trace_value(val);
+
+ val = OUTCONTROL1_TIE(0) |
+ OUTCONTROL1_SIP(0) |
+ OUTCONTROL1_FINIT(1) |
+ OUTCONTROL1_FCI(0) |
+ OUTCONTROL1_BFTH(bfth) |
+ OUTCONTROL1_OF(of1) |
+ OUTCONTROL1_IPM(ipm) |
+ OUTCONTROL1_TH(th);
+ dmic_write(dai, OUTCONTROL1, val);
+ trace_value(val);
+#endif
+
+#if DMIC_HW_VERSION == 2
+ source_ipm_helper(source, &ipm, stereo, swap, dmic);
+ val = OUTCONTROL0_TIE(0) |
+ OUTCONTROL0_SIP(0) |
+ OUTCONTROL0_FINIT(1) |
+ OUTCONTROL0_FCI(0) |
+ OUTCONTROL0_BFTH(3) |
+ OUTCONTROL0_OF(of0) |
+ OUTCONTROL0_NUMBER_OF_DECIMATORS(ipm) |
+ OUTCONTROL0_IPM_SOURCE_1(source[0]) |
+ OUTCONTROL0_IPM_SOURCE_2(source[1]) |
+ OUTCONTROL0_IPM_SOURCE_3(source[2]) |
+ OUTCONTROL0_IPM_SOURCE_4(source[3]) |
+ OUTCONTROL0_TH(3);
+ dmic_write(dai, OUTCONTROL0, val);
+ trace_value(val);
+
+ val = OUTCONTROL1_TIE(0) |
+ OUTCONTROL1_SIP(0) |
+ OUTCONTROL1_FINIT(1) |
+ OUTCONTROL1_FCI(0) |
+ OUTCONTROL1_BFTH(3) |
+ OUTCONTROL1_OF(of1) |
+ OUTCONTROL1_NUMBER_OF_DECIMATORS(ipm) |
+ OUTCONTROL1_IPM_SOURCE_1(source[0]) |
+ OUTCONTROL1_IPM_SOURCE_2(source[1]) |
+ OUTCONTROL1_IPM_SOURCE_3(source[2]) |
+ OUTCONTROL1_IPM_SOURCE_4(source[3]) |
+ OUTCONTROL1_TH(3);
+ dmic_write(dai, OUTCONTROL1, val);
+ trace_value(val);
+#endif
+
+ /* Mark enabled microphones into private data to be later used
+ * for starting correct parts of the HW.
+ */
+ for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+ pdata->enable[i] = (dmic->pdm[i].enable_mic_b << 1) |
+ dmic->pdm[i].enable_mic_a;
+ }
+
+ for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+ /* CIC */
+ val = CIC_CONTROL_SOFT_RESET(soft_reset) |
+ CIC_CONTROL_CIC_START_B(cic_start_b) |
+ CIC_CONTROL_CIC_START_A(cic_start_a) |
+ CIC_CONTROL_MIC_B_POLARITY(dmic->pdm[i].polarity_mic_a) |
+ CIC_CONTROL_MIC_A_POLARITY(dmic->pdm[i].polarity_mic_b) |
+ CIC_CONTROL_MIC_MUTE(cic_mute) |
+ CIC_CONTROL_STEREO_MODE(stereo[i]);
+ dmic_write(dai, base[i] + CIC_CONTROL, val);
+ trace_value(val);
+
+ val = CIC_CONFIG_CIC_SHIFT(cfg->cic_shift + 8) |
+ CIC_CONFIG_COMB_COUNT(cfg->mcic - 1);
+ dmic_write(dai, base[i] + CIC_CONFIG, val);
+ trace_value(val);
+
+ /* Mono right channel mic usage requires swap of PDM channels
+ * since the mono decimation is done with only left channel
+ * processing active.
+ */
+ edge = dmic->pdm[i].clk_edge;
+ if (swap[i])
+ edge = edge ^ 1;
+
+ val = MIC_CONTROL_PDM_CLKDIV(cfg->clkdiv - 2) |
+ MIC_CONTROL_PDM_SKEW(dmic->pdm[i].skew) |
+ MIC_CONTROL_CLK_EDGE(edge) |
+ MIC_CONTROL_PDM_EN_B(cic_start_b) |
+ MIC_CONTROL_PDM_EN_A(cic_start_a);
+ dmic_write(dai, base[i] + MIC_CONTROL, val);
+ trace_value(val);
+
+ /* FIR A */
+ fir_decim = MAX(cfg->mfir_a - 1, 0);
+ fir_length = MAX(cfg->fir_a_length - 1, 0);
+ val = FIR_CONTROL_A_START(fir_start_a) |
+ FIR_CONTROL_A_ARRAY_START_EN(array_a) |
+ FIR_CONTROL_A_DCCOMP(dccomp) |
+ FIR_CONTROL_A_MUTE(fir_mute) |
+ FIR_CONTROL_A_STEREO(stereo[i]);
+ dmic_write(dai, base[i] + FIR_CONTROL_A, val);
+ trace_value(val);
+
+ val = FIR_CONFIG_A_FIR_DECIMATION(fir_decim) |
+ FIR_CONFIG_A_FIR_SHIFT(cfg->fir_a_shift) |
+ FIR_CONFIG_A_FIR_LENGTH(fir_length);
+ dmic_write(dai, base[i] + FIR_CONFIG_A, val);
+ trace_value(val);
+
+ val = DC_OFFSET_LEFT_A_DC_OFFS(DCCOMP_TC0);
+ dmic_write(dai, base[i] + DC_OFFSET_LEFT_A, val);
+ trace_value(val);
+
+ val = DC_OFFSET_RIGHT_A_DC_OFFS(DCCOMP_TC0);
+ dmic_write(dai, base[i] + DC_OFFSET_RIGHT_A, val);
+ trace_value(val);
+
+ val = OUT_GAIN_LEFT_A_GAIN(0);
+ dmic_write(dai, base[i] + OUT_GAIN_LEFT_A, val);
+ trace_value(val);
+
+ val = OUT_GAIN_RIGHT_A_GAIN(0);
+ dmic_write(dai, base[i] + OUT_GAIN_RIGHT_A, val);
+ trace_value(val);
+
+ /* FIR B */
+ fir_decim = MAX(cfg->mfir_b - 1, 0);
+ fir_length = MAX(cfg->fir_b_length - 1, 0);
+ val = FIR_CONTROL_B_START(fir_start_b) |
+ FIR_CONTROL_B_ARRAY_START_EN(array_b) |
+ FIR_CONTROL_B_DCCOMP(dccomp) |
+ FIR_CONTROL_B_MUTE(fir_mute) |
+ FIR_CONTROL_B_STEREO(stereo[i]);
+ dmic_write(dai, base[i] + FIR_CONTROL_B, val);
+ trace_value(val);
+
+ val = FIR_CONFIG_B_FIR_DECIMATION(fir_decim) |
+ FIR_CONFIG_B_FIR_SHIFT(cfg->fir_b_shift) |
+ FIR_CONFIG_B_FIR_LENGTH(fir_length);
+ dmic_write(dai, base[i] + FIR_CONFIG_B, val);
+ trace_value(val);
+
+ val = DC_OFFSET_LEFT_B_DC_OFFS(DCCOMP_TC0);
+ dmic_write(dai, base[i] + DC_OFFSET_LEFT_B, val);
+ trace_value(val);
+ trace_value(val);
+
+ val = DC_OFFSET_RIGHT_B_DC_OFFS(DCCOMP_TC0);
+ dmic_write(dai, base[i] + DC_OFFSET_RIGHT_B, val);
+ trace_value(val);
+
+ val = OUT_GAIN_LEFT_B_GAIN(0);
+ dmic_write(dai, base[i] + OUT_GAIN_LEFT_B, val);
+ trace_value(val);
+
+ val = OUT_GAIN_RIGHT_B_GAIN(0);
+ dmic_write(dai, base[i] + OUT_GAIN_RIGHT_B, val);
+ trace_value(val);
+
+ /* Write coef RAM A with scaled coefficient in reverse order */
+ length = cfg->fir_a_length;
+ for (j = 0; j < length; j++) {
+ ci = (int32_t)Q_MULTSR_32X32(
+ (int64_t)cfg->fir_a->coef[j],
+ cfg->fir_a_scale, 31, 20, DMIC_HW_FIR_COEF_Q);
+ cu = FIR_COEF_A(ci);
+ dmic_write(dai, coef_base_a[i]
+ + ((length - j - 1) << 2), cu);
+ }
+
+ /* Write coef RAM B with scaled coefficient in reverse order */
+ length = cfg->fir_b_length;
+ for (j = 0; j < length; j++) {
+ ci = (int32_t)Q_MULTSR_32X32(
+ (int64_t)cfg->fir_b->coef[j],
+ cfg->fir_b_scale, 31, 20, DMIC_HW_FIR_COEF_Q);
+ cu = FIR_COEF_B(ci);
+ dmic_write(dai, coef_base_b[i]
+ + ((length - j - 1) << 2), cu);
+ }
+ }
+
+ /* Function dmic_start() uses these to start the used FIFOs */
+ if (cfg->mfir_a > 0)
+ pdata->fifo_a = 1;
+ else
+ pdata->fifo_a = 0;
+
+ if (cfg->mfir_b > 0)
+ pdata->fifo_b = 1;
+ else
+ pdata->fifo_b = 0;
+
+ return 0;
+}
+
+static int dmic_set_config(struct dai *dai, struct sof_ipc_dai_config *config)
+{
+ struct decim_modes modes_a;
+ struct decim_modes modes_b;
+ struct matched_modes modes_ab;
+ struct dmic_configuration cfg;
+ int ret;
+ struct sof_ipc_dai_dmic_params *prm = &config->dmic;
+ struct dmic_pdata *dmic = dai_get_drvdata(dai);
+
+ trace_dmic("dsc");
+
+#if defined DMIC_FORCE_CONFIG
+ /* This is a temporary workaound to set parameters while
+ * there is no driver and topology scripts support to
+ * set these. Also the PCM sample format(s) and sample rate(s)
+ * setting would be better to be common with other DAI types.
+ */
+ prm->driver_ipc_version = 1;
+ prm->pdmclk_min = 768000; /* Min 768 kHz */
+ prm->pdmclk_max = 4800000; /* Max 4.80 MHz */
+ prm->fifo_fs_a = 48000;
+ prm->fifo_fs_b = 0;
+ prm->fifo_bits_a = 32;
+ prm->fifo_bits_b = 0;
+ prm->duty_min = 40; /* Min. 40% */
+ prm->duty_max = 60; /* Max. 60% */
+ prm->number_of_pdm_controllers = 2;
+ prm->pdm[0].clk_edge = 0;
+ prm->pdm[0].enable_mic_a = 1; /* Left */
+ prm->pdm[0].enable_mic_b = 1; /* Right */
+ prm->pdm[0].polarity_mic_a = 0;
+ prm->pdm[0].polarity_mic_b = 0;
+ prm->pdm[0].skew = 0;
+ prm->pdm[1].clk_edge = 0;
+ prm->pdm[1].enable_mic_a = 0; /* Left */
+ prm->pdm[1].enable_mic_b = 0; /* Right */
+ prm->pdm[1].polarity_mic_a = 0;
+ prm->pdm[1].polarity_mic_b = 0;
+ prm->pdm[1].skew = 0;
+#endif
+
+ trace_value(prm->driver_ipc_version);
+ trace_value(prm->pdmclk_min);
+ trace_value(prm->pdmclk_max);
+ trace_value(prm->fifo_fs_a);
+ trace_value(prm->fifo_fs_b);
+ trace_value(prm->fifo_bits_a);
+ trace_value(prm->fifo_bits_b);
+ trace_value(prm->duty_min);
+ trace_value(prm->duty_max);
+ trace_value(prm->number_of_pdm_controllers);
+
+ if (prm->driver_ipc_version != DMIC_IPC_VERSION) {
+ trace_dmic_error("ver");
+ return -EINVAL;
+ }
+
+ /* Match and select optimal decimators configuration for FIFOs A and B
+ * paths. This setup phase is still abstract. Successful completion
+ * points struct cfg to FIR coefficients and contains the scale value
+ * to use for FIR coefficient RAM write as well as the CIC and FIR
+ * shift values.
+ */
+ find_modes(&modes_a, prm, prm->fifo_fs_a);
+ if (modes_a.num_of_modes == 0 && prm->fifo_fs_a > 0) {
+ trace_dmic_error("amo");
+ return -EINVAL;
+ }
+
+ find_modes(&modes_b, prm, prm->fifo_fs_b);
+ if (modes_b.num_of_modes == 0 && prm->fifo_fs_b > 0) {
+ trace_dmic_error("bmo");
+ return -EINVAL;
+ }
+
+ match_modes(&modes_ab, &modes_a, &modes_b);
+ ret = select_mode(&cfg, &modes_ab);
+ if (ret < 0) {
+ trace_dmic_error("smo");
+ return -EINVAL;
+ }
+
+ trace_dmic("cfg");
+ trace_value(cfg.clkdiv);
+ trace_value(cfg.mcic);
+ trace_value(cfg.mfir_a);
+ trace_value(cfg.mfir_b);
+ trace_value(cfg.fir_a_length);
+ trace_value(cfg.fir_b_length);
+ trace_value(cfg.cic_shift);
+ trace_value(cfg.fir_a_shift);
+ trace_value(cfg.fir_b_shift);
+
+ /* Struct reg contains a mirror of actual HW registers. Determine
+ * register bits configuration from decimator configuration and the
+ * requested parameters.
+ */
+ ret = configure_registers(dai, &cfg, prm);
+ if (ret < 0) {
+ trace_dmic_error("cor");
+ return -EINVAL;
+ }
+
+ dmic->state = COMP_STATE_PREPARE;
+
+ return 0;
+}
+
+/* start the DMIC for capture */
+static void dmic_start(struct dai *dai, int direction)
+{
+ struct dmic_pdata *dmic = dai_get_drvdata(dai);
+ int i;
+ int mic_a;
+ int mic_b;
+ int fir_a;
+ int fir_b;
+
+ if (direction != DAI_DIR_CAPTURE)
+ return;
+
+ /* enable port */
+ spin_lock(&dmic->lock);
+ trace_dmic("sta");
+ dmic->state = COMP_STATE_ACTIVE;
+
+ if (dmic->fifo_a) {
+ trace_dmic("ffa");
+ /* Clear FIFO A initialize, Enable interrupts to DSP,
+ * Start FIFO A packer.
+ */
+ dmic_update_bits(dai, OUTCONTROL0,
+ OUTCONTROL0_FINIT_BIT | OUTCONTROL0_SIP_BIT,
+ OUTCONTROL0_SIP_BIT);
+ }
+ if (dmic->fifo_b) {
+ trace_dmic("ffb");
+ /* Clear FIFO B initialize, Enable interrupts to DSP,
+ * Start FIFO B packer.
+ */
+ dmic_update_bits(dai, OUTCONTROL1,
+ OUTCONTROL1_FINIT_BIT | OUTCONTROL1_SIP_BIT,
+ OUTCONTROL1_SIP_BIT);
+ }
+
+ for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+ mic_a = dmic->enable[i] & 1;
+ mic_b = (dmic->enable[i] & 2) >> 1;
+ if (dmic->fifo_a)
+ fir_a = (dmic->enable[i] > 0) ? 1 : 0;
+ else
+ fir_a = 0;
+ if (dmic->fifo_b)
+ fir_b = (dmic->enable[i] > 0) ? 1 : 0;
+ else
+ fir_b = 0;
+
+ trace_dmic("mfn");
+ trace_value(mic_a);
+ trace_value(mic_b);
+ trace_value(fir_a);
+ trace_value(fir_b);
+
+ dmic_update_bits(dai, base[i] + CIC_CONTROL,
+ CIC_CONTROL_CIC_START_A_BIT |
+ CIC_CONTROL_CIC_START_B_BIT,
+ CIC_CONTROL_CIC_START_A(mic_a) |
+ CIC_CONTROL_CIC_START_B(mic_b));
+ dmic_update_bits(dai, base[i] + MIC_CONTROL,
+ MIC_CONTROL_PDM_EN_A_BIT |
+ MIC_CONTROL_PDM_EN_B_BIT,
+ MIC_CONTROL_PDM_EN_A(mic_a) |
+ MIC_CONTROL_PDM_EN_B(mic_b));
+
+ dmic_update_bits(dai, base[i] + FIR_CONTROL_A,
+ FIR_CONTROL_A_START_BIT, FIR_CONTROL_A_START(fir_a));
+ dmic_update_bits(dai, base[i] + FIR_CONTROL_B,
+ FIR_CONTROL_B_START_BIT, FIR_CONTROL_B_START(fir_b));
+ }
+
+ /* Clear soft reset for all/used PDM controllers. This should
+ * start capture in sync.
+ */
+ trace_dmic("unr");
+ for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+ dmic_update_bits(dai, base[i] + CIC_CONTROL,
+ CIC_CONTROL_SOFT_RESET_BIT, 0);
+ }
+
+ spin_unlock(&dmic->lock);
+
+ /* Currently there's no DMIC HW internal mutings and wait times
+ * applied into this start sequence. It can be implemented here if
+ * start of audio capture would contain clicks and/or noise and it
+ * is not suppressed by gain ramp somewhere in the capture pipe.
+ */
+ trace_dmic("run");
+}
+
+/* stop the DMIC for capture */
+static void dmic_stop(struct dai *dai)
+{
+ struct dmic_pdata *dmic = dai_get_drvdata(dai);
+ int i;
+
+ trace_dmic("sto")
+
+ spin_lock(&dmic->lock);
+
+ /* stop Rx if we are not capturing */
+ if (dmic->state != COMP_STATE_ACTIVE) {
+ /* Set every PDM controller to soft reset */
+ trace_dmic("sre");
+ for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+ dmic_update_bits(dai, base[i] + CIC_CONTROL,
+ CIC_CONTROL_SOFT_RESET_BIT, 0);
+ }
+
+ /* Stop FIFO packers and set FIFO initialize bits */
+ dmic_update_bits(dai, OUTCONTROL0,
+ OUTCONTROL0_SIP_BIT | OUTCONTROL0_FINIT_BIT,
+ OUTCONTROL0_FINIT_BIT);
+ dmic_update_bits(dai, OUTCONTROL1,
+ OUTCONTROL1_SIP_BIT | OUTCONTROL1_FINIT_BIT,
+ OUTCONTROL1_FINIT_BIT);
+
+ dmic->state = COMP_STATE_PREPARE;
+ }
+
+ /* Set soft reset for all PDM controllers.
+ */
+ trace_dmic("sre");
+ for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+ dmic_update_bits(dai, base[i] + CIC_CONTROL,
+ CIC_CONTROL_SOFT_RESET_BIT, CIC_CONTROL_SOFT_RESET_BIT);
+ }
+
+ spin_unlock(&dmic->lock);
+}
+
+/* save DMIC context prior to entering D3 */
+static int dmic_context_store(struct dai *dai)
+{
+ /* TODO: Nothing stored at the moment. Could read the registers into
+ * persisten memory if needed but the large coef RAM is not desirable
+ * to copy. It would be better to store selected mode parametesr from
+ * previous configuration request and re-program registers from
+ * scratch.
+ */
+ return 0;
+}
+
+/* restore DMIC context after leaving D3 */
+static int dmic_context_restore(struct dai *dai)
+{
+ /* Nothing restored at the moment. */
+ return 0;
+}
+
+static int dmic_trigger(struct dai *dai, int cmd, int direction)
+{
+ struct dmic_pdata *dmic = dai_get_drvdata(dai);
+
+ trace_dmic("tri");
+
+ /* dai private is set in dmic_probe(), error if not set */
+ if (!dmic) {
+ trace_dmic_error("trn");
+ return -EINVAL;
+ }
+
+ if (direction != DAI_DIR_CAPTURE) {
+ trace_dmic_error("cap");
+ return -EINVAL;
+ }
+
+ switch (cmd) {
+ case COMP_TRIGGER_START:
+ if (dmic->state == COMP_STATE_PREPARE ||
+ dmic->state == COMP_STATE_PAUSED) {
+ dmic_start(dai, direction);
+ } else {
+ trace_dmic_error("cst");
+ trace_value(dmic->state);
+ }
+ break;
+ case COMP_TRIGGER_RELEASE:
+ if (dmic->state == COMP_STATE_PREPARE) {
+ dmic_start(dai, direction);
+ } else {
+ trace_dmic_error("crl");
+ trace_value(dmic->state);
+ }
+ break;
+ case COMP_TRIGGER_STOP:
+ case COMP_TRIGGER_PAUSE:
+ dmic->state = COMP_STATE_PAUSED;
+ dmic_stop(dai);
+ break;
+ case COMP_TRIGGER_RESUME:
+ dmic_context_restore(dai);
+ break;
+ case COMP_TRIGGER_SUSPEND:
+ dmic_context_store(dai);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+/* TODO: No idea what should be done here. Currently only trace the
+ * status register that contains a few status and error bit fields.
+ */
+static void dmic_irq_handler(void *data)
+{
+ struct dai *dai = data;
+ uint32_t val;
+
+ /* Trace OUTSTAT0 register */
+ val = dmic_read(dai, OUTSTAT0);
+ trace_dmic("irq");
+
+ if (val & OUTSTAT0_ROR_BIT)
+ trace_dmic_error("eor"); /* Full fifo or PDM overrrun */
+
+ trace_value(dmic_read(dai, OUTSTAT0));
+
+ /* clear IRQ */
+ platform_interrupt_clear(dmic_irq(dai), 1);
+}
+
+static int dmic_probe(struct dai *dai)
+{
+ struct dmic_pdata *dmic;
+
+ trace_dmic("pro");
+
+ /* allocate private data */
+ dmic = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, sizeof(*dmic));
+ dai_set_drvdata(dai, dmic);
+
+ spinlock_init(&dmic->lock);
+
+ /* Set state, note there is no playback direction support */
+ dmic->state = COMP_STATE_READY;
+
+ /* register our IRQ handler */
+ interrupt_register(dmic_irq(dai), dmic_irq_handler, dai);
+
+ platform_interrupt_unmask(dmic_irq(dai), 1);
+ interrupt_enable(dmic_irq(dai));
+
+ return 0;
+}
+
+/* DMIC has no loopback support */
+static inline int dmic_set_loopback_mode(struct dai *dai, uint32_t lbm)
+{
+ return -EINVAL;
+}
+
+const struct dai_ops dmic_ops = {
+ .trigger = dmic_trigger,
+ .set_config = dmic_set_config,
+ .pm_context_store = dmic_context_store,
+ .pm_context_restore = dmic_context_restore,
+ .probe = dmic_probe,
+ .set_loopback_mode = dmic_set_loopback_mode,
+};
+
+#endif
diff --git a/src/include/sof/dmic.h b/src/include/sof/dmic.h
new file mode 100644
index 0000000..d86c0a7
--- /dev/null
+++ b/src/include/sof/dmic.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the Intel Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Seppo Ingalsuo <seppo.ingalsuo at linux.intel.com>
+ */
+
+#ifndef __INCLUDE_DMIC__
+#define __INCLUDE_DMIC__
+
+#include <sof/dai.h>
+#include <sof/io.h>
+
+#if defined CONFIG_DMIC
+
+#if defined CONFIG_APOLLOLAKE
+#define DMIC_HW_VERSION 1
+#define DMIC_HW_CONTROLLERS 2
+#define DMIC_HW_IOCLK 19200000
+#endif
+
+#if defined CONFIG_CANNONLAKE
+#define DMIC_HW_VERSION 1
+#define DMIC_HW_CONTROLLERS 2
+#define DMIC_HW_IOCLK 24000000
+#endif
+
+#endif
+
+#if defined DMIC_HW_VERSION
+
+/* Parameters used in modes computation */
+#define DMIC_HW_BITS_CIC 26
+#define DMIC_HW_BITS_FIR_COEF 20
+#define DMIC_HW_BITS_FIR_GAIN 20
+#define DMIC_HW_BITS_FIR_INPUT 22
+#define DMIC_HW_BITS_FIR_OUTPUT 24
+#define DMIC_HW_BITS_FIR_INTERNAL 26
+#define DMIC_HW_BITS_GAIN_OUTPUT 22
+#define DMIC_HW_FIR_LENGTH_MAX 250
+#define DMIC_HW_CIC_SHIFT_MIN -8
+#define DMIC_HW_CIC_SHIFT_MAX 4
+#define DMIC_HW_FIR_SHIFT_MIN 0
+#define DMIC_HW_FIR_SHIFT_MAX 8
+#define DMIC_HW_CIC_DECIM_MIN 5
+#define DMIC_HW_CIC_DECIM_MAX 31 /* Note: Limited by BITS_CIC */
+#define DMIC_HW_FIR_DECIM_MIN 2
+#define DMIC_HW_FIR_DECIM_MAX 20 /* Note: Practical upper limit */
+#define DMIC_HW_SENS_Q23 Q_CONVERT_FLOAT(0.95, 23) /* Q1.23 */
+#define DMIC_HW_PDM_CLK_MIN 100000 /* Note: Practical min value */
+#define DMIC_HW_DUTY_MIN 20 /* Note: Practical min value */
+#define DMIC_HW_DUTY_MAX 80 /* Note: Practical max value */
+
+/* DMIC register offsets */
+
+/* Global registers */
+#define OUTCONTROL0 0x0000
+#define OUTSTAT0 0x0004
+#define OUTDATA0 0x0008
+#define OUTCONTROL1 0x0100
+#define OUTSTAT1 0x0104
+#define OUTDATA1 0x0108
+#define PDM0 0x1000
+#define PDM0_COEFFICIENT_A 0x1400
+#define PDM0_COEFFICIENT_B 0x1800
+#define PDM1 0x2000
+#define PDM1_COEFFICIENT_A 0x2400
+#define PDM1_COEFFICIENT_B 0x2800
+#define PDM2 0x3000
+#define PDM2_COEFFICIENT_A 0x3400
+#define PDM2_COEFFICIENT_B 0x3800
+#define PDM3 0x4000
+#define PDM3_COEFFICIENT_A 0x4400
+#define PDM3_COEFFICIENT_B 0x4800
+#define PDM_COEF_RAM_A_LENGTH 0x0400
+#define PDM_COEF_RAM_B_LENGTH 0x0400
+
+/* Local registers in each PDMx */
+#define CIC_CONTROL 0x000
+#define CIC_CONFIG 0x004
+#define MIC_CONTROL 0x00c
+#define FIR_CONTROL_A 0x020
+#define FIR_CONFIG_A 0x024
+#define DC_OFFSET_LEFT_A 0x028
+#define DC_OFFSET_RIGHT_A 0x02c
+#define OUT_GAIN_LEFT_A 0x030
+#define OUT_GAIN_RIGHT_A 0x034
+#define FIR_CONTROL_B 0x040
+#define FIR_CONFIG_B 0x044
+#define DC_OFFSET_LEFT_B 0x048
+#define DC_OFFSET_RIGHT_B 0x04c
+#define OUT_GAIN_LEFT_B 0x050
+#define OUT_GAIN_RIGHT_B 0x054
+
+/* Register bits */
+
+#if DMIC_HW_VERSION == 1
+/* OUTCONTROL0 bits */
+#define OUTCONTROL0_TIE_BIT BIT(27)
+#define OUTCONTROL0_SIP_BIT BIT(26)
+#define OUTCONTROL0_FINIT_BIT BIT(25)
+#define OUTCONTROL0_FCI_BIT BIT(24)
+#define OUTCONTROL0_TIE(x) SET_BIT(27, x)
+#define OUTCONTROL0_SIP(x) SET_BIT(26, x)
+#define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
+#define OUTCONTROL0_FCI(x) SET_BIT(24, x)
+#define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
+#define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
+#define OUTCONTROL0_IPM(x) SET_BITS(17, 16, x)
+#define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
+
+/* OUTCONTROL1 bits */
+#define OUTCONTROL1_TIE_BIT BIT(27)
+#define OUTCONTROL1_SIP_BIT BIT(26)
+#define OUTCONTROL1_FINIT_BIT BIT(25)
+#define OUTCONTROL1_FCI_BIT BIT(24)
+#define OUTCONTROL1_TIE(x) SET_BIT(27, x)
+#define OUTCONTROL1_SIP(x) SET_BIT(26, x)
+#define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
+#define OUTCONTROL1_FCI(x) SET_BIT(24, x)
+#define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
+#define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
+#define OUTCONTROL1_IPM(x) SET_BITS(17, 16, x)
+#define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
+#endif
+
+#if DMIC_HW_VERSION == 2
+/* OUTCONTROL0 bits */
+#define OUTCONTROL0_TIE_BIT BIT(27)
+#define OUTCONTROL0_SIP_BIT BIT(26)
+#define OUTCONTROL0_FINIT_BIT BIT(25)
+#define OUTCONTROL0_FCI_BIT BIT(24)
+#define OUTCONTROL0_TIE(x) SET_BIT(27, x)
+#define OUTCONTROL0_SIP(x) SET_BIT(26, x)
+#define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
+#define OUTCONTROL0_FCI(x) SET_BIT(24, x)
+#define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
+#define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
+#define OUTCONTROL0_NUMBER_OF_DECIMATORS(x) SET_BITS(17, 15, x)
+#define OUTCONTROL0_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
+#define OUTCONTROL0_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
+#define OUTCONTROL0_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
+#define OUTCONTROL0_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
+#define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
+
+/* OUTCONTROL1 bits */
+#define OUTCONTROL1_TIE_BIT BIT(27)
+#define OUTCONTROL1_SIP_BIT BIT(26)
+#define OUTCONTROL1_FINIT_BIT BIT(25)
+#define OUTCONTROL1_FCI_BIT BIT(24)
+#define OUTCONTROL1_TIE(x) SET_BIT(27, x)
+#define OUTCONTROL1_SIP(x) SET_BIT(26, x)
+#define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
+#define OUTCONTROL1_FCI(x) SET_BIT(24, x)
+#define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
+#define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
+#define OUTCONTROL1_NUMBER_OF_DECIMATORS(x) SET_BITS(17, 15, x)
+#define OUTCONTROL1_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
+#define OUTCONTROL1_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
+#define OUTCONTROL1_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
+#define OUTCONTROL1_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
+#define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
+#endif
+
+/* OUTSTAT0 bits */
+#define OUTSTAT0_AFE_BIT BIT(31)
+#define OUTSTAT0_ASNE_BIT BIT(29)
+#define OUTSTAT0_RFS_BIT BIT(28)
+#define OUTSTAT0_ROR_BIT BIT(27)
+#define OUTSTAT0_FL_MASK MASK(6, 0)
+
+/* OUTSTAT1 bits */
+#define OUTSTAT1_AFE_BIT BIT(31)
+#define OUTSTAT1_ASNE_BIT BIT(29)
+#define OUTSTAT1_RFS_BIT BIT(28)
+#define OUTSTAT1_ROR_BIT BIT(27)
+#define OUTSTAT1_FL_MASK MASK(6, 0)
+
+/* CIC_CONTROL bits */
+#define CIC_CONTROL_SOFT_RESET_BIT BIT(16)
+#define CIC_CONTROL_CIC_START_B_BIT BIT(15)
+#define CIC_CONTROL_CIC_START_A_BIT BIT(14)
+#define CIC_CONTROL_MIC_B_POLARITY_BIT BIT(3)
+#define CIC_CONTROL_MIC_A_POLARITY_BIT BIT(2)
+#define CIC_CONTROL_MIC_MUTE_BIT BIT(1)
+#define CIC_CONTROL_STEREO_MODE_BIT BIT(0)
+
+#define CIC_CONTROL_SOFT_RESET(x) SET_BIT(16, x)
+#define CIC_CONTROL_CIC_START_B(x) SET_BIT(15, x)
+#define CIC_CONTROL_CIC_START_A(x) SET_BIT(14, x)
+#define CIC_CONTROL_MIC_B_POLARITY(x) SET_BIT(3, x)
+#define CIC_CONTROL_MIC_A_POLARITY(x) SET_BIT(2, x)
+#define CIC_CONTROL_MIC_MUTE(x) SET_BIT(1, x)
+#define CIC_CONTROL_STEREO_MODE(x) SET_BIT(0, x)
+
+/* CIC_CONFIG bits */
+#define CIC_CONFIG_CIC_SHIFT(x) SET_BITS(27, 24, x)
+#define CIC_CONFIG_COMB_COUNT(x) SET_BITS(15, 8, x)
+
+/* MIC_CONTROL bits */
+#define MIC_CONTROL_PDM_EN_B_BIT BIT(1)
+#define MIC_CONTROL_PDM_EN_A_BIT BIT(0)
+#define MIC_CONTROL_PDM_CLKDIV(x) SET_BITS(15, 8, x)
+#define MIC_CONTROL_PDM_SKEW(x) SET_BITS(7, 4, x)
+#define MIC_CONTROL_CLK_EDGE(x) SET_BIT(3, x)
+#define MIC_CONTROL_PDM_EN_B(x) SET_BIT(1, x)
+#define MIC_CONTROL_PDM_EN_A(x) SET_BIT(0, x)
+
+/* FIR_CONTROL_A bits */
+#define FIR_CONTROL_A_START_BIT BIT(7)
+#define FIR_CONTROL_A_ARRAY_START_EN_BIT BIT(6)
+#define FIR_CONTROL_A_MUTE_BIT BIT(1)
+#define FIR_CONTROL_A_START(x) SET_BIT(7, x)
+#define FIR_CONTROL_A_ARRAY_START_EN(x) SET_BIT(6, x)
+#define FIR_CONTROL_A_DCCOMP(x) SET_BIT(4, x)
+#define FIR_CONTROL_A_MUTE(x) SET_BIT(1, x)
+#define FIR_CONTROL_A_STEREO(x) SET_BIT(0, x)
+
+/* FIR_CONFIG_A bits */
+#define FIR_CONFIG_A_FIR_DECIMATION(x) SET_BITS(20, 16, x)
+#define FIR_CONFIG_A_FIR_SHIFT(x) SET_BITS(11, 8, x)
+#define FIR_CONFIG_A_FIR_LENGTH(x) SET_BITS(7, 0, x)
+
+/* DC offset compensation time constants */
+#define DCCOMP_TC0 0
+#define DCCOMP_TC1 1
+#define DCCOMP_TC2 2
+#define DCCOMP_TC3 3
+#define DCCOMP_TC4 4
+#define DCCOMP_TC5 5
+#define DCCOMP_TC6 6
+#define DCCOMP_TC7 7
+
+/* DC_OFFSET_LEFT_A bits */
+#define DC_OFFSET_LEFT_A_DC_OFFS(x) SET_BITS(21, 0, x)
+
+/* DC_OFFSET_RIGHT_A bits */
+#define DC_OFFSET_RIGHT_A_DC_OFFS(x) SET_BITS(21, 0, x)
+
+/* OUT_GAIN_LEFT_A bits */
+#define OUT_GAIN_LEFT_A_GAIN(x) SET_BITS(19, 0, x)
+
+/* OUT_GAIN_RIGHT_A bits */
+#define OUT_GAIN_RIGHT_A_GAIN(x) SET_BITS(19, 0, x)
+
+/* FIR_CONTROL_B bits */
+#define FIR_CONTROL_B_START_BIT BIT(7)
+#define FIR_CONTROL_B_ARRAY_START_EN_BIT BIT(6)
+#define FIR_CONTROL_B_MUTE_BIT BIT(1)
+#define FIR_CONTROL_B_START(x) SET_BIT(7, x)
+#define FIR_CONTROL_B_ARRAY_START_EN(x) SET_BIT(6, x)
+#define FIR_CONTROL_B_DCCOMP(x) SET_BIT(4, x)
+#define FIR_CONTROL_B_MUTE(x) SET_BIT(1, x)
+#define FIR_CONTROL_B_STEREO(x) SET_BIT(0, x)
+
+/* FIR_CONFIG_B bits */
+#define FIR_CONFIG_B_FIR_DECIMATION(x) SET_BITS(20, 16, x)
+#define FIR_CONFIG_B_FIR_SHIFT(x) SET_BITS(11, 8, x)
+#define FIR_CONFIG_B_FIR_LENGTH(x) SET_BITS(7, 0, x)
+
+/* DC_OFFSET_LEFT_B bits */
+#define DC_OFFSET_LEFT_B_DC_OFFS(x) SET_BITS(21, 0, x)
+
+/* DC_OFFSET_RIGHT_B bits */
+#define DC_OFFSET_RIGHT_B_DC_OFFS(x) SET_BITS(21, 0, x)
+
+/* OUT_GAIN_LEFT_B bits */
+#define OUT_GAIN_LEFT_B_GAIN(x) SET_BITS(19, 0, x)
+
+/* OUT_GAIN_RIGHT_B bits */
+#define OUT_GAIN_RIGHT_B_GAIN(x) SET_BITS(19, 0, x)
+
+/* FIR coefficients */
+#define FIR_COEF_A(x) SET_BITS(19, 0, x)
+#define FIR_COEF_B(x) SET_BITS(19, 0, x)
+
+#define dmic_irq(dmic) \
+ dmic->plat_data.irq
+
+/* DMIC private data */
+struct dmic_pdata {
+ spinlock_t lock; /* Spinlock that's used in registers IO */
+ uint16_t fifo_a;
+ uint16_t fifo_b;
+ uint16_t enable[DMIC_HW_CONTROLLERS];
+ uint32_t state;
+ completion_t drain_complete;
+ struct sof_ipc_dai_config config;
+ struct sof_ipc_dai_dmic_params params;
+};
+
+extern const struct dai_ops dmic_ops;
+
+#endif /* DMIC_HW_VERSION */
+#endif /* __INCLUDE_DMIC__ */
diff --git a/src/include/sof/io.h b/src/include/sof/io.h
index 3181d41..11f870a 100644
--- a/src/include/sof/io.h
+++ b/src/include/sof/io.h
@@ -33,6 +33,14 @@
#include <stdint.h>
+/* Macros for register bits access */
+#define BIT(b) (1 << (b))
+#define MASK(b_hi, b_lo) ((1 << ((b_hi)-(b_lo)+1)) - 1)
+#define SET_BIT(b, x) (((x) & 1) << (b))
+#define SET_BITS(b_hi, b_lo, x) \
+ (((x) & ((1 << ((b_hi)-(b_lo)+1)) - 1)) << (b_lo))
+
+
static inline uint32_t io_reg_read(uint32_t reg)
{
return *((volatile uint32_t*)reg);
diff --git a/src/include/sof/trace.h b/src/include/sof/trace.h
index 5409a1f..2fd77fe 100644
--- a/src/include/sof/trace.h
+++ b/src/include/sof/trace.h
@@ -71,7 +71,7 @@
#define TRACE_BOOT_PLATFORM_IPC (TRACE_BOOT_PLATFORM + 0x170)
#define TRACE_BOOT_PLATFORM_DMA (TRACE_BOOT_PLATFORM + 0x180)
#define TRACE_BOOT_PLATFORM_SSP (TRACE_BOOT_PLATFORM + 0x190)
-
+#define TRACE_BOOT_PLATFORM_DMIC (TRACE_BOOT_PLATFORM + 0x1a0)
/* trace event classes - high 8 bits*/
#define TRACE_CLASS_IRQ (1 << 24)
@@ -95,6 +95,7 @@
#define TRACE_CLASS_EQ_FIR (19 << 24)
#define TRACE_CLASS_EQ_IIR (20 << 24)
#define TRACE_CLASS_SA (21 << 24)
+#define TRACE_CLASS_DMIC (22 << 24)
/* move to config.h */
#define TRACE 1
diff --git a/src/include/uapi/ipc.h b/src/include/uapi/ipc.h
index 7d0a9a4..b32376d 100644
--- a/src/include/uapi/ipc.h
+++ b/src/include/uapi/ipc.h
@@ -273,9 +273,68 @@ struct sof_ipc_dai_hda_params {
} __attribute__((packed));
/* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
+
+/* This struct is defined per 2ch PDM controller available in the platform.
+ * Normally it is sufficient to set the used microphone specific enables to 1
+ * and keep other parameters as zero. The customizations are:
+ *
+ * 1. If a device mixes different microphones types with different polarity
+ * and/or the absolute polarity matters the PCM signal from a microphone
+ * can be inverted with the controls.
+ *
+ * 2. If the microphones in a stereo pair do not appear in captured stream
+ * in desired order due to board schematics choises they can be swapped with
+ * the clk_edge parameter.
+ *
+ * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter
+ * that delays the sampling time of data by half cycles of DMIC source clock
+ * can be tried for improvement. However there is no guarantee for this to fix
+ * data integrity problems.
+ */
+struct sof_ipc_dai_dmic_pdm_ctrl {
+ uint16_t enable_mic_a; /* Use A (left) channel mic (0 or 1)*/
+ uint16_t enable_mic_b; /* Use B (right) channel mic (0 or 1)*/
+ uint16_t polarity_mic_a; /* Optionally invert mic A signal (0 or 1) */
+ uint16_t polarity_mic_b; /* Optionally invert mic B signal (0 or 1) */
+ uint16_t clk_edge; /* Optionally swap data clock edge (0 or 1) */
+ uint16_t skew; /* Adjust PDM data sampling vs. clock (0..15) */
+} __attribute__((packed));
+
+/* This struct contains the global settings for all 2ch PDM controllers. The
+ * version number used in configuration data is checked vs. version used by
+ * device driver src/drivers/dmic.c need to match. It is incremented from
+ * initial value 1 if updates done for the to driver would alter the operation
+ * of the microhone.
+ *
+ * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max)
+ * parameters need to be set as defined in microphone data sheet. E.g. clock
+ * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
+ * multi-mode capable and there may be denied mic clock frequencies between
+ * the modes. In such case set the clock range limits of the desired mode to
+ * avoid the driver to set clock to an illegal rate.
+ *
+ * The duty cycle could be set to 48-52% if not known. Generally these
+ * parameters can be altered within data sheet specified limits to match
+ * required audio application performance power.
+ *
+ * The microphone clock needs to be usually about 50-80 times the used audio
+ * sample rate. With highest sample rates above 48 kHz this can relaxed
+ * somewhat.
+ */
struct sof_ipc_dai_dmic_params {
struct sof_ipc_hdr hdr;
- /* TODO */
+ uint32_t driver_ipc_version; /* Version (1..N) */
+ uint32_t pdmclk_min; /* Minimum microphone clock in Hz (100000..N) */
+ uint32_t pdmclk_max; /* Maximum microphone clock in Hz (min...N) */
+ uint32_t fifo_fs_a; /* FIFO A sample rate in Hz (8000..96000) */
+ uint32_t fifo_fs_b; /* FIFO B sample rate in Hz (8000..96000) */
+ /* TODO: FIFO word lengths can be retrieved from SOF_DAI_FMT */
+ uint16_t fifo_bits_a; /* FIFO A word length (16 or 24) */
+ uint16_t fifo_bits_b; /* FIFO B word length (16 or 24) */
+ uint16_t duty_min; /* Min. mic clock duty cycle in % (20..80) */
+ uint16_t duty_max; /* Max. mic clock duty cycle in % (min..80) */
+ uint32_t number_of_pdm_controllers; /* Number 2ch controllers (2) */
+ struct sof_ipc_dai_dmic_pdm_ctrl pdm[];
} __attribute__((packed));
/* general purpose DAI configuration */
--
2.14.1
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