[Sound-open-firmware] [PATCH] pipeline: use 1ms tick for low latency pipeline.

[Liam Girdwood]

Change tick from 1.3ms to 1ms to improve latency.

Signed-off-by: Liam Girdwood <liam.r.girdwood at linux.intel.com>
---
 src/audio/mixer.c                                 | 4 +++-
 src/audio/volume.c                                | 4 +++-
 src/platform/baytrail/include/platform/platform.h | 7 +++++--
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/src/audio/mixer.c b/src/audio/mixer.c
index e48b545..b244f50 100644
--- a/src/audio/mixer.c
+++ b/src/audio/mixer.c
@@ -203,9 +203,11 @@ static int mixer_copy(struct comp_dev *dev)
 {
 	struct mixer_data *md = comp_get_drvdata(dev);
 	struct comp_buffer *sink, *sources[5], *source;
-	uint32_t i = 0, cframes = 64;
+	uint32_t i = 0, cframes = PIPELINE_LL_FRAMES;
 	struct list_item * blist;
 
+	trace_mixer("Mix");
+
 	/* calculate the highest status between input streams */
 	list_for_item(blist, &dev->bsource_list) {
 		source = container_of(blist, struct comp_buffer, sink_list);
diff --git a/src/audio/volume.c b/src/audio/volume.c
index f5528cd..23db6a5 100644
--- a/src/audio/volume.c
+++ b/src/audio/volume.c
@@ -376,7 +376,9 @@ static int volume_copy(struct comp_dev *dev)
 {
 	struct comp_data *cd = comp_get_drvdata(dev);
 	struct comp_buffer *sink, *source;
-	uint32_t cframes = 64;
+	uint32_t cframes = PIPELINE_LL_FRAMES;
+
+	trace_comp("Vol");
 
 	/* volume components will only ever have 1 source and 1 sink buffer */
 	source = list_first_item(&dev->bsource_list, struct comp_buffer, sink_list);
diff --git a/src/platform/baytrail/include/platform/platform.h b/src/platform/baytrail/include/platform/platform.h
index 38fcc26..b58a3c0 100644
--- a/src/platform/baytrail/include/platform/platform.h
+++ b/src/platform/baytrail/include/platform/platform.h
@@ -55,13 +55,16 @@
 #define PLATFORM_MAX_STREAMS	5
 
 /* Platform Host DMA buffer config - these should align with DMA engine */
-#define PLAT_HOST_PERSIZE	256	/* must be multiple of DMA burst size */
+#define PLAT_HOST_PERSIZE	192	/* must be multiple of DMA burst size */
 #define PLAT_HOST_PERIODS	2	/* give enough latency for DMA refill */
 
 /* Platform Dev DMA buffer config - these should align with DMA engine */
-#define PLAT_DEV_PERSIZE	256	/* must be multiple of DMA+DEV burst size */
+#define PLAT_DEV_PERSIZE	192	/* must be multiple of DMA+DEV burst size */
 #define PLAT_DEV_PERIODS	2	/* give enough latency for DMA refill */
 
+/* Pipeline low latency frames per copy - TODO should come from config */
+#define PIPELINE_LL_FRAMES	48
+
 /* DMA channel drain timeout in microseconds */
 #define PLATFORM_DMA_TIMEOUT	1333
 
-- 
2.9.3