[PATCH v2] ASoC: Intel: sof_rt5682: add 512FS MCLK clock configuration

[Pierre-Louis Bossart]

On 1/19/22 11:40 PM, Mac Chiang wrote:
> codec system clock source support 512FS MCLK synchronous directly, so
> no need to set PLL configuration when MCLK 24.576MHz.
> 
> Suggested-by: Shuming Fan <shumingf at realtek.com>
> Signed-off-by: Mac Chiang <mac.chiang at intel.com>
> ---
> Changelog:
> 
> v2:
>   - apply mclk configuration to both rt5682vd and rt5682vs
>   - Thanks to Brent by suggesting pll_in condition if MCLK or
>     PLL requires.

Nice simplification, thanks!

Acked-by: Pierre-Louis Bossart <pierre-louis.bossart at linux.intel.com>

> ---
>  sound/soc/intel/boards/sof_rt5682.c | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c
> index bd6d2e7dea53..f4e833cbffe1 100644
> --- a/sound/soc/intel/boards/sof_rt5682.c
> +++ b/sound/soc/intel/boards/sof_rt5682.c
> @@ -369,11 +369,16 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream,
>  
>  	pll_out = params_rate(params) * 512;
>  
> -	/* Configure pll for codec */
> -	ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in,
> -				  pll_out);
> -	if (ret < 0)
> -		dev_err(rtd->dev, "snd_soc_dai_set_pll err = %d\n", ret);
> +	/* when MCLK is 512FS, no need to set PLL configuration additionally. */
> +	if (pll_in == pll_out)
> +		clk_id = RT5682S_SCLK_S_MCLK;
> +	else {
> +		/* Configure pll for codec */
> +		ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in,
> +					  pll_out);
> +		if (ret < 0)
> +			dev_err(rtd->dev, "snd_soc_dai_set_pll err = %d\n", ret);
> +	}
>  
>  	/* Configure sysclk for codec */
>  	ret = snd_soc_dai_set_sysclk(codec_dai, clk_id,
>