[PATCH v2] ASoC: codecs: add uspport for the TI SRC4392 codec

[Nathan Chancellor]

On Wed, Aug 17, 2022 at 03:44:33PM +1000, Matt Flax wrote:
> 
> On 17/8/22 04:00, Nathan Chancellor wrote:
> 
> > >     265			/* set the PLL for the digital receiver */
> > >     266			switch (src4xxx->mclk_hz) {
> > >     267			case 24576000:
> > >     268				pj = 0x22;
> > >     269				jd = 0x00;
> > >     270				d = 0x00;
> > >     271				break;
> > >     272			case 22579200:
> > >     273				pj = 0x22;
> > >     274				jd = 0x1b;
> > >     275				d = 0xa3;
> > >     276				break;
> > >   > 277			default:
> > >     278				/* don't error out here,
> > >     279				 * other parts of the chip are still functional
> > >     280				 */
> > >     281				dev_info(component->dev,
> > >     282					"Couldn't set the RCV PLL as this master clock rate is unknown\n");
> > In the final commit, there is a 'break' here. Should it be a 'return 0'
> > instead? Or should there be a different fix for these warnings?
> 
> The data sheet for the src4392 doesn't list defaults for these registers
> (loaded with pj, jd and d). The actual state of these registers is not known
> until we load them with something, arbitrary or not.
> 
> 	{  SRC4XXX_RCV_PLL_0F,		0x00  },  /* not spec. in the datasheet */
> 	{  SRC4XXX_RCV_PLL_10,		0xff  },  /* not spec. in the datasheet */
> 	{  SRC4XXX_RCV_PLL_11,		0xff  },  /* not spec. in the datasheet */
> 
> The state of DIR PLL registers aren't important if the user doesn't specify
> a known mclk frequency.  The implication is that the DIR will not function,
> however that is already implied by the user lacking to specify a known mclk
> frequency.
> 
> The other functions on the chip (port A/B I2S, SRC, DIT, etc) will behave as
> per usual, only the DIR will be dysfunctional.

So I suppose there is little point to all of the calls to regmap_write()
and regmap_update_bits() in the default case then, meaning a 'return 0'
would be appropriate? Sorry, I am having a hard time parsing what should
be done about the warnings, which are fatal for allmodconfig due to
CONFIG_WERROR.

Cheers,
Nathan

> > >     283			}
> > >     284			ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_0F, pj);
> > >     285			if (ret < 0)
> > >     286				dev_err(component->dev,
> > >     287					"Failed to update PLL register 0x%x\n",
> > >     288					SRC4XXX_RCV_PLL_0F);
> > >   > 289			ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_10, jd);
> > >     290			if (ret < 0)
> > >     291				dev_err(component->dev,
> > >     292					"Failed to update PLL register 0x%x\n",
> > >     293					SRC4XXX_RCV_PLL_10);
> > >   > 294			ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_11, d);
> > >     295			if (ret < 0)
> > >     296				dev_err(component->dev,
> > >     297					"Failed to update PLL register 0x%x\n",
> > >     298					SRC4XXX_RCV_PLL_11);
> > Cheers,
> > Nathan