[alsa-devel] [PATCH 2/2] ASoC: nau8825: provide clock divide for codec mater mode

[Mark Brown]

On Tue, Jan 03, 2017 at 11:04:50AM +0800, John Hsu wrote:
> On 1/1/2017 2:57 AM, Mark Brown wrote:

> > Why is the driver not able to configure these automatically, most
> > devices manage to do that OK?  Typically systems are fine with the
> > obvious divisions down from the root clock, the driver should at least
> > offer that as a default rather than requiring all machine drivers to
> > duplicate the divisor selection code.

> The system clock of codec is always 256FS. Therefore, the driver can
> make it automatically. If the codec is as master, the driver needs to
> divide the system clock to output the BCLK and FS. But there are too
> many combinations between BCLK and FS. The BCLK maybe is 32FS, 64FS,
> 128FS, etc. The driver needs machine information to do the division.
> Thus, I think the best way is to make decision by machine driver.

This all sounds totally standard - other drivers manage to provide a
default easily enough here.  You can determine a default BCLK by looking
at the number of channels and number of bits per sample to work out how
many BCLKs are going to be needed to clock that data out.
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