[alsa-devel] [PATCH v2] ASOC: wm8960: Add multiple MCLK frequency support

[chen liu]

2017-12-15 0:19 GMT+08:00 Charles Keepax <ckeepax at opensource.cirrus.com>:

> On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote:
>
> OK so looking over this some more with Mark's comments in mind
> the thing that troubles me is this. Currently there are two ways
> you can configure the clocking manually or automatically.
>
> The manual way using the set_dai_pll, set_dai_clkdiv and
> set_dai_sysclk calls.
>
> Automatically by calling set_dai_sysclk and set_dai_pll with
> WM8960_SYSCLK_AUTO and the driver will work it out for you. This
> option already supports setting the SYSCLK_DIV.
>
> I guess my first question would be can you get the result you
> desire by just using the automatic option?
>
> If not, it seems like what we are trying to do here is move the
> set_dai_clkdiv for SYSCLK_DIV to be automatic in both cases. The
> problem is that I suspect this handling interfers somewhat with the
> handling of these bits that is done in wm8960_configure_clocking
> through wm8960_configure_pll when we are doing things
> automatically. In which case I think you need to look at how to
> align these two clocking methods.
>

Hi Charles,

When the MCLK clock frequency cannot meet the SYSCLK clock
frequency of the wm8960 codec,we must use the PLL divider to
generate the clock frequency.

For what you are talking about setting the SYSCLK clock frequency
automatically and manually,the difference is that one uses the PLL
divider to generate the SYSCLK clock frequency and the other one
provides the SYSCLK clock frequency directly through the MCLK.

Although the driver already supports setting the SYSCLK_DIV register,
it can only be set to 1,thus causing the codec to not support multiple
MCLK clock frequency.(For more information, please see the wm8960
codec manual)

The important purpose of this patch is to support multiple MCLK
clock frequency.

Thanks again,
Chen.