[alsa-devel] [PATCH] ALSA: hda - disable dynamic clock gating on Broxton before reset

[Takashi Iwai]

On Fri, 29 Jan 2016 13:39:09 +0100,
libin.yang at linux.intel.com wrote:
> 
> From: Libin Yang <libin.yang at linux.intel.com>
> 
> On Broxton, to make sure the reset controller works properly,
> MISCBDCGE bit (bit 6) in CGCTL (0x48) of PCI configuration space
> need be cleared before reset and set back to 1 after reset.
> Otherwise, it may prevent the CORB/RIRB logic from being reset.
> 
> Signed-off-by: Libin Yang <libin.yang at linux.intel.com>

Applied, thanks.


Takashi


> ---
>  sound/pci/hda/hda_intel.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
> index aeaa9a5..12c5442 100644
> --- a/sound/pci/hda/hda_intel.c
> +++ b/sound/pci/hda/hda_intel.c
> @@ -90,6 +90,8 @@ enum {
>  #define NVIDIA_HDA_ENABLE_COHBIT      0x01
>  
>  /* Defines for Intel SCH HDA snoop control */
> +#define INTEL_HDA_CGCTL	 0x48
> +#define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
>  #define INTEL_SCH_HDA_DEVC      0x78
>  #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
>  
> @@ -536,10 +538,21 @@ static void hda_intel_init_chip(struct azx *chip, bool full_reset)
>  {
>  	struct hdac_bus *bus = azx_bus(chip);
>  	struct pci_dev *pci = chip->pci;
> +	u32 val;
>  
>  	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
>  		snd_hdac_set_codec_wakeup(bus, true);
> +	if (IS_BROXTON(pci)) {
> +		pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
> +		val = val & (~(INTEL_HDA_CGCTL_MISCBDCGE));
> +		pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
> +	}
>  	azx_init_chip(chip, full_reset);
> +	if (IS_BROXTON(pci)) {
> +		pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
> +		val = val | INTEL_HDA_CGCTL_MISCBDCGE;
> +		pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
> +	}
>  	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
>  		snd_hdac_set_codec_wakeup(bus, false);
>  
> -- 
> 1.9.1
>