[alsa-devel] [PATCH] ASoC: adau17x1: Cache writes when core clock is disabled

[Lars-Peter Clausen]

On 02/04/2016 03:05 PM, Andreas Irestål wrote:
> In some configurations, the dai registers get written before the bias
> level is changed in the codec driver. This leads to a situation where
> an initial write to the serial port register gets ignored, and future
> writes may as well, since regmap thinks that the codec already holds the
> value. More specifically, configuring the codec as i2s master would in
> fact result in the codec running as slave, a situation where no i2s
> clocks are generated and hence no data is transferred.
> 
> This change makes sure that regmap only caches writes when the core
> clock is disabled, and syncs regmap whenever enabling the core clock
> again.
> 
> Signed-off-by: Andreas Irestål <andire at axis.com>

Looks good, thanks for the patch.

Acked-by: Lars-Peter Clausen <lars at metafoo.de>


> ---
>  sound/soc/codecs/adau1761.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/sound/soc/codecs/adau1761.c b/sound/soc/codecs/adau1761.c
> index 2f12477..e7136b1 100644
> --- a/sound/soc/codecs/adau1761.c
> +++ b/sound/soc/codecs/adau1761.c
> @@ -456,13 +456,17 @@ static int adau1761_set_bias_level(struct snd_soc_codec *codec,
>  	case SND_SOC_BIAS_PREPARE:
>  		break;
>  	case SND_SOC_BIAS_STANDBY:
> +		regcache_cache_only(adau->regmap, false);
>  		regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
>  			ADAU17X1_CLOCK_CONTROL_SYSCLK_EN,
>  			ADAU17X1_CLOCK_CONTROL_SYSCLK_EN);
> +		if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
> +			regcache_sync(adau->regmap);
>  		break;
>  	case SND_SOC_BIAS_OFF:
>  		regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
>  			ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, 0);
> +		regcache_cache_only(adau->regmap, true);
>  		break;
>  
>  	}
> @@ -783,6 +787,10 @@ int adau1761_probe(struct device *dev, struct regmap *regmap,
>  	if (ret)
>  		return ret;
>  
> +	/* Enable cache only mode as we could miss writes before bias level
> +	 * reaches standby and the core clock is enabled */
> +	regcache_cache_only(regmap, true);
> +

There are a few register writes before this where the hardware configuration
is setup. When I look at my test setup those writes seem to go through, even
though they shouldn't according to what you say (and to what is written in
the datasheet).

On the other hand I've never seen the issue you are having either and I've
tested both master and slave configuration of the device. Maybe something
changed in the silicon in newer revisions of the device. Can you take a look
whether the hardware configuration is correctly applied for you?


>  	return snd_soc_register_codec(dev, &adau1761_codec_driver, dai_drv, 1);
>  }
>  EXPORT_SYMBOL_GPL(adau1761_probe);
>