[alsa-devel] [PATCH] ASoC: Document DAI signal polarity

[Lars-Peter Clausen]

On 09/30/2015 09:08 PM, Anatol Pomozov wrote:
>  - for I2S/left/right justified - frame starts with falling FSYNC edge

This is what most drivers implement:

I2S: Left channel starts with the falling edge, right channel starts with
the rising edge (data is delayed by one clock cycle)

Right/Left justified: Left channel starts with the rising edge, right
channel starts with the falling edge

DSP A/B: Frame starts with the rising edge. Channels are spaced by the
configured slot width (e.g. first channel at offset 0, second channel at
offset 16, third channel at offset 32, ...). If the slot with has not been
configured explicitly using the set_tdm_slots() API the slot with is the
number of bits in one single-channel sample (Return value of params_width()).

When using I2S or left/right justified in TDM mode channels are also spaced
by the configured slot width and the second edge should be ignored.