[alsa-devel] [PATCH] ASoC: fsl_ssi: bclk should never greater than 1/5 IPG clock rate

[Zidan Wang]

According to the referance menual, the bclk rate must be never greater
than 1/5 IPG clock rate. But clkrate is the system clock, afreq is the
bit clock.

Signed-off-by: Zidan Wang <zidan.wang at freescale.com>
---
 sound/soc/fsl/fsl_ssi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index e3abad5..4466bcb 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -677,16 +677,16 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
 		else
 			clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
 
+		clkrate /= factor;
+		afreq = clkrate / (i + 1);
+
 		/*
 		 * Hardware limitation: The bclk rate must be
 		 * never greater than 1/5 IPG clock rate
 		 */
-		if (clkrate * 5 > clk_get_rate(ssi_private->clk))
+		if (afreq * 5 > clk_get_rate(ssi_private->clk))
 			continue;
 
-		clkrate /= factor;
-		afreq = clkrate / (i + 1);
-
 		if (freq == afreq)
 			sub = 0;
 		else if (freq / afreq == 1)
-- 
1.9.1