[alsa-devel] [PATCH 1/2] ASoC: max98090: Correct pclk divisor settings

[Mark Brown]

On Mon, Nov 03, 2014 at 10:28:56AM -0800, Dylan Reid wrote:
> The Baytrail-based chromebooks have a 20MHz mclk, the code was setting
> the divisor incorrectly in this case.  According to the 98090
> datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20.
> Correct this and the surrounding clock ranges as well to match the
> datasheet.

Applied both, thanks.
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