[alsa-devel] [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations
broonie at kernel.org
Fri Apr 4 12:05:32 CEST 2014
On Fri, Apr 04, 2014 at 03:09:47PM +0800, Nicolin Chen wrote:
> The BCP bit in TCR4/RCR4 register rules as followings:
> 0 Bit clock is active high with drive outputs on rising edge
> and sample inputs on falling edge.
> 1 Bit clock is active low with drive outputs on falling edge
> and sample inputs on rising edge.
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