[alsa-devel] [PATCH] ASoC: fsl: imx-wm8962: Do FLL configuration in hw_params() and hw_kree()
b42378 at freescale.com
Thu Dec 5 12:07:28 CET 2013
On Thu, Dec 05, 2013 at 11:15:08AM +0000, Mark Brown wrote:
> On Thu, Dec 05, 2013 at 10:56:31AM +0800, Nicolin Chen wrote:
> > As far as I can understand, the point that all the outputs needs the device
> > to be clocked is undeniably true, but the external MCLK should be sufficient
> > to source the SYSCLK of WM8962. Does the bypass mode also need to set FLL
> > to get an accurate frequency?
> The device is going to need a clock that's in spec to make sure that the
> device performs in spec, if the device is clocked from a 32kHz clock
> (which is quite a common configuration and one that's supported by the
> machine driver since it gets the clock from DT) that's definitely not
> going to be the case and I'd not expect it to work at all sensibly.
Thank you for the explain. I understand now.
Then I think it would be plausible if I could refine this patch to
allow both set_bias_level() and hw_params/free() to control the FLL
while making them not break each other but coexist, right?
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