[alsa-devel] [PATCH] ASoC: fsl: imx-wm8962: Do FLL configuration in hw_params() and hw_free()
b42378 at freescale.com
Thu Dec 5 03:56:31 CET 2013
On Wed, Dec 04, 2013 at 07:02:11PM +0000, Mark Brown wrote:
> On Thu, Dec 05, 2013 at 12:54:08AM +0800, Nicolin Chen wrote:
> > Previously, we couldn't use hw_params() and hw_free() to open and close FLL
> > becuase there might be race between two simmultaneous substreams and cause
> > FLL configuration being changed and accordingly mulfunction. So we adopted
> > DAPM to control it since there won't be any race in DAPM. However, if we
> > want to playback a different sample rate file, we need to wait for DAPM to
> > change its bias_level to reconfigure FLL.
> > But after we introduced full symmetry protection in the soc-pcm, we don't
> > need to worry about the race any more. And the instance by using hw_params()
> > and hw_free() to control FLL would allow us to support flexible use cases,
> > 'aplay -Dhw:0 44k16bit.wav 48k24bit.wav 32k32bit.wav' for example.
> > Thus this patch mainly moves FLL configuration from set_bias_level() to
> > hw_params() and hw_free() so as to enchance the sound card's capability.
> That's not the only reason for using set_bias_level(), it's also used so
> that bypass paths from the CODEC inputs to outputs get the FLL started
> - all the outputs need the device to be clocked.
Thank you for reminding me of this case. And I still have a concern.
As far as I can understand, the point that all the outputs needs the device
to be clocked is undeniably true, but the external MCLK should be sufficient
to source the SYSCLK of WM8962. Does the bypass mode also need to set FLL
to get an accurate frequency?
Sorry I am not so familiar with the bypass path. So what I can imagine is
WM8962 just bypass input (DAC) to outputs (DAC) via MIXER or some routes
else, then there's no need for WM8962 to generate accurate BCLK and LRCLK.
Sir, could you please also shed some light on this point if it's not a
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