[alsa-devel] [PATCH 1/1] ASoC: wm8960: Fix PLL register writes

Mark Brown broonie at kernel.org
Sun Aug 18 17:37:21 CEST 2013

On Fri, Aug 16, 2013 at 06:36:28PM +0100, Mike Dyer wrote:
> Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part should be split across each register in 8bit chunks.

Applied, thanks.  Please remember to word wrap your commit messages
within paragraphs.
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