[alsa-devel] [PATCH v2 1/2] ARM: imx: clk: Split SSI clock into 'ipg' and 'per'

Fabio Estevam festevam at gmail.com
Tue Oct 9 06:21:10 CEST 2012


On Mon, Oct 8, 2012 at 8:47 PM, Fabio Estevam <festevam at gmail.com> wrote:
> Hi Sascha,
> On Mon, Oct 8, 2012 at 6:44 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> I am not sure it's good to work around that issue in the ssi driver. We
>> could also just enable the clock in the clk driver as it seems to be a
>> ccm related issue.
> Yes, it would be better if we could fix this in clk-imx27 instead, but
> I was not able to provide such fix yet.

The ssi1_sel clock is defined as:

clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks,

,where ssi_sel_clks is:
static const char *ssi_sel_clks[] = { "spll", "mpll", }

,which matches with the mx27 reference manual.

How do we tell the clk api to select spll or mpll as the source for ssi_sel?

I understand how to do this from register level, but not from the api.


Fabio Estevam

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