[alsa-devel] [PATCH 3/6] ASoC: wm8974: include MCLKDIV in pll_factors

Mark Brown broonie at opensource.wolfsonmicro.com
Fri Nov 9 15:55:15 CET 2012

On Fri, Nov 09, 2012 at 03:00:22PM +0100, Steffen Trumtrar wrote:

> To calculate the integer part of the frequency ratio, the whole output
> path has to be considered (post and pre are optional):

> 	    Ndiv = (pre * target * 4 * post) / source

> In the current implementation only the fixed- and pre-divider is
> considered, but the post-divider is omitted.
> To calculate Ndiv, this post divider has to be applied before any
> calculation happens. Otherwise Ndiv is considered to be to low in the
> later stages. This leads to a wrong value in the PLLN register, which
> in turn produces a wrong playback speed of the audio signal.

This changelog doesn't mention where you're using MCLKDIV here but it
does rather sound like the PLL configuration is not being done correctly
here.  The expectation is that when the PLL is configured the raw output
frequency from the PLL is specified.  The PLL is then specified as the
system clock with that rate and then any division required to make that
usable happens afterwards.

> +	case WM8974_MCLKDIV_1:
> +				reg = 1;
> +				break;

Please do follow the Linux coding style for kernel code.
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