[alsa-devel] [PATCH] ASoC: tlv320aic3x: add input clock selection

Prchal Jiří jiri.prchal at aksignal.cz
Tue Jun 26 12:21:28 CEST 2012


This patch adds input selection of main codec clock - from what pin.
Tested with TLV320AIC3106 on BCLK and MCLK.

Signed-off-by: Jiri Prchal <jiri.prchal at aksignal.cz>

--- /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c.orig
+++ /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.c
@@ -972,6 +972,10 @@
  	struct snd_soc_codec *codec = codec_dai->codec;
  	struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);

+	/* set clock on MCLK or GPIO2 or BCLK */
+	snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, clk_id);
+	snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, clk_id);
+
  	aic3x->sysclk = freq;
  	return 0;
  }

--- /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.h.orig
+++ /home/prchal/arm/fw-cdu/linux/linux-3.5-rc3/sound/soc/codecs/tlv320aic3x.h
@@ -178,6 +178,13 @@
  #define PLL_CLKIN_SHIFT		4
  #define MCLK_SOURCE		0x0
  #define PLL_CLKDIV_SHIFT	0
+#define PLLCLK_IN_MASK		0x30
+#define CLKDIV_IN_MASK		0xc0
+/* clock in source */
+#define CLKIN_MCLK		0
+#define CLKIN_GPIO2		1
+#define CLKIN_BCLK		2
+

  /* Software reset register bits */
  #define SOFT_RESET		0x80


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